TWI593083B - 在功率半導體中的電流感測器用的半導體裝置 - Google Patents

在功率半導體中的電流感測器用的半導體裝置 Download PDF

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TWI593083B
TWI593083B TW102105025A TW102105025A TWI593083B TW I593083 B TWI593083 B TW I593083B TW 102105025 A TW102105025 A TW 102105025A TW 102105025 A TW102105025 A TW 102105025A TW I593083 B TWI593083 B TW I593083B
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cell
transistor
semiconductor device
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TW201347142A (zh
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克利斯汀 普盧特克
湯瑪斯 賈克
提姆 豪爾
寇夫勒 岡瑟
盧依廷 霍爾格
沃特 弗蘭克
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羅伯特博斯奇股份有限公司
茵芬昂科技股份有限公司
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Description

在功率半導體中的電流感測器用的半導體裝置
本發明關於一種在功率半導體中的電流感測器用的半導體裝置，特別是用於一種雙極電晶體的功率半導體，其具有絕緣的閘極電極，亦稱絕緣閘極雙極電晶體(IGBT)。
功率半導體一般製成垂直構造且有多數電晶體的晶胞(Zelle,英：cell)。在此，一半導體基材的前側上形成閘極和射極構造，它們經由至少一個p-n過渡區與集極層(它設計成在後側上的整面的鍍金屬層的形式)連接，在功率電晶體的場合，這種晶胞構造在基材的很大範圍重複，因此可切換大電流，但在此要注意避免短路或過負載狀態，因此在一般習知技術在輸出端子設一旁路電阻，俾將主電流回路中可能發生的短路或超載狀態檢出。
此外在先前技術將射極的一區域或射極晶胞的一部分經一感測器端子分枝並利用流過該處的電流當作信號，典型的方式，感測器端子位在射極領域內且完全或部分地充以射極晶胞，在完全充滿的情形，感測器晶胞埋入主射極中的情形很狹小，且可預料到感測器晶胞的性質和主射極晶胞的性質很少不同，但利用射極端子和感測器端子的大比例，可預設感測器電流對主電流的固定比例，只作部分充滿的情形有一優點：這種 比例可較自由地設計，但為此，該狹小的埋入情形就失去，且會有一些無晶胞的區域，在其中在導通狀態時同樣會建構成電荷載體電漿。
當使用或設計一IGBT時要注意：在關掉狀態時流經射極的電荷載體不得使個別電晶體晶胞過載。在具有n個通道的IGBT的例子，流經射極的電荷載體的種類係由電洞造成，過載的危險及一閂住(Latch-up)的動作特別在於位於感測器區域及主射極區域邊緣的晶胞，因為在沒有射極接點的無晶胞區域中也形成一電荷載體電漿。此不含晶胞的中間區域(無晶胞領域)一方面係在感測器端子未完全充滿的情形存在，但也會由於必須將與此二射極區域連接的導電層隔開而造成。
本發明的目的在將由於在無晶胞領域中的電荷載體電漿之在關掉時流過的電洞對鄰界到無晶胞領域的晶胞的負載減少，同時使感測器晶胞能儘量狹窄地埋入到主射極中。
這種目的達成之道係利用一種在一功率半導體中的電流感測器用的半導體裝置，該半導體裝置在一基材上有電晶體晶胞的多重設置，該電晶體晶胞具有被絕緣的閘電極，其射極端子在一第一區域經一第一導體層與至少一輸出端子連接，而其射極端子在一第二區域經一第二導電層與至少一感測器端子連接，該感測器端子設在一第一晶胞領域界限外，該第一晶胞領域界限包圍住該第一區域的電晶體晶胞和第二區域的電晶體晶胞，其中在該第二區域的電晶體晶胞和該感測器端子之間形成一和與該第一晶胞領域界限相關的渠溝構造，有一個與該第一導電層連接的摻雜層沿著朝向該基材的一外緣的方向接到該渠溝構造。且此外，該渠溝構 造在第一區域的電晶體晶胞與第二區域的電晶體晶胞之間延續。
依本發明，由IGBT構成的射極分成二個晶胞組，一方面形成主晶胞，它們利用第一導電層與射極輸出端連接。此晶胞組蓋住電路裝置的基材面積的大部分。與第二導電層連接的較小部分當作感測器晶胞，且當作電流感測器，因此經由一外界電阻可產生一電壓信號，它可進一步處理以檢出短路電流及過電流，接到第一導電層的摻雜的領域用於將在關掉過程流出的電洞導離，因此它們不會對鄰接的主晶胞造成負荷，這點可能使鎖閂之虞提高，且會使晶片破壞。
本發明目的達成之道為：將感測器端子設在活性的晶胞區域在晶胞領域界限後，來自此端子區域的電洞經由此接到主發射器之導通層連接的摻雜領域而導離。因此，感測器領域的大小形狀可不受感測器端子的大小形影響。
依本發明另一設計，該第二區域的電晶體晶胞設成一多角形的形狀，且宜設成一半圓形或六角形、長方形或正方形的形狀。
這種裝置可用簡單方式用一般的設計程式形成重覆的構造，並用功率半導體的一般製造程序實施。
依本發明另一設計，該第一區域的電晶體晶胞至少部分地圍住該第二區域的電晶體晶胞，且宜圍住其三邊。
依本發明另一設計，該第一區域的電晶體晶胞完全圍住該第二區域的電晶體晶胞以及該第二導電層。
依本發明另一設計，該第二區域的電晶體晶胞設成在空間上與該第一區域的電晶體晶胞分開。
在此實施例中，電流感測器晶胞並非狹窄地埋入主晶胞中，而係遠離主晶胞用一本身之晶胞領域界限圍住。這點相當於一分開之較小的IGBT半導體，其電漿在啟開狀態時或在切換過程時各依間隔而與主IGBT很少或甚至不交替作用。然而該二部分經常仍可視為一IGBT晶片，因為它們沿朝向晶片邊緣的方向被一共同之邊緣封閉構造圍住。
依本發明另一設計，該感測器端子設成一絕緣層上方的鍍金屬面形式，其層厚度比一閘介電質的層厚度更大。
在此實施例，感測器端子可放在一厚氧化物上的任意位置。
依本發明另一設計，該第二區域的電晶體晶胞被一第二晶胞領域界限圍住。
這種實施例特別用於當感測器晶胞設成遠離主晶胞的場合。
依另一實施例，該感測器端子與該第二區域的電晶體晶胞(2)設在該晶胞領域界限外。
在此實施例中，在感測器端子和第二區域的電晶體晶胞間沒有雙渠溝構造。
第二導電層可在晶胞領域界限的區域中有一刻入部，在其中第一導電層與摻雜層連接，這點使在關掉過程流出的電洞更佳地導離。
本發明在以下利用實施例配合附圖詳細說明。
(1)‧‧‧電路裝置
(2)‧‧‧電晶體晶胞
(3)‧‧‧閘極電極
(4)‧‧‧基材
(5)‧‧‧集極端子
(6)‧‧‧緩衝層
(7)‧‧‧磊晶層
(8)‧‧‧盆槽
(9)‧‧‧島
(10)‧‧‧射極端子
(11)‧‧‧絕緣層
(12)‧‧‧第一區域
(13)‧‧‧第二區域
(14)‧‧‧晶胞領域界限
(15)(15’)‧‧‧p摻雜層
(16)‧‧‧第一導電層
(17)‧‧‧第二導電層
(18)‧‧‧感測器端子
(19)(19’)‧‧‧接點
(21)‧‧‧主晶胞
(22)‧‧‧感測器晶胞
(23)‧‧‧外界電阻
(24)‧‧‧信號
(25)‧‧‧輸出端子
(26)‧‧‧端子
(27)‧‧‧端子
(30)‧‧‧距離
圖1係電晶體晶胞的一橫截面圖；圖2a係依本發明一第一實施例的半導體裝置的一上視圖； 圖2b係依本發明該第一實施例的半導體裝置的另一上視圖；圖3係依圖2a的實施例的另一示意圖；圖4係依本發明另一實施例的一本發明半導體裝置的一上視圖；圖5係依本發明另一實施例的一本發明半導體裝置的一上視圖；圖6係依本發明另一實施例的一本發明半導體裝置的一上視圖；圖7係依本發明另一實施例的一本發明半導體裝置的一上視圖；圖8係依本發明另一實施例的一本發明半導體裝置的一上視圖。
圖式中或相同作用的元件用相同圖號表示。
圖1中顯示一電路裝置(1)的一視圖，它構成一基極晶胞以供多數電晶體晶胞(2)之用，其具有絕緣之閘極電極(3)(IGBT)。如圖1所示，一基材(4)[舉例而言，為p+摻雜]在後側有一集極端子(5)，它一般設成金屬層形式，在集極端子(5)和基材(4)上方設一緩衝層(6)(在此例為n摻雜)，其後跟著一同樣n摻雜的磊晶(Epitaxie)層(7)。p摻雜的盆槽(Wanne)(8)設入磊晶層(7)中，例如藉離子植入達成，在其中設有二個n-摻雜的島(9)，該島和p摻雜的盆槽(8)一齊部分地被一射極端子(10)蓋住。
閘極電極(3)被一由氧化矽形成之絕緣層(11)圍住，絕緣層也可設在電晶體晶胞(2)外。整體上，在圖示例子得到一種n型通道IGBT用的n+pnp構造，但也可考慮將本發明用在其他IGBT類型，例如一p型通道的IGBT或具垂直構造的IGBT。
在以下說明依本發明一第一實施例的電路裝置(1)，圖2a中顯示電路裝置(1)一上視圖，即具射極端子(10)的上側。如圖2a所示，電路 裝置(1)包含多數電晶體晶胞(2)，它們設在一第一區域(12)及一第二區域(13)中。圖2a所示的裝置只是舉例。
電晶體晶胞(2)大致完全蓋住第一區域(12)及第二區域(13)，且可設成任意圖案，它不一定須為規則者，第一區域(12)的電晶體晶胞(2)係並聯，且用於功率半導體。
第二區域(13)的電晶體晶胞(2)同樣並聯，且用於電流感測器，以下還要詳述。第一區域(12)的電晶體晶胞(2)可稱主晶胞，第二區域(13)者可稱感測器晶胞。
第一區域(12)的電晶體晶胞(2)和第二區域(13)的電晶體晶胞(2)被一第一晶胞領域界限圍住，其中晶胞領域界限用圖號(14)表示，第一晶胞領域界限(14)設計成基材中一渠溝形式，但也可用一雙渠溝構造，它由二個在基材中相鄰延伸的渠溝形成，第一晶胞領域界限(14)外的領域設有一p摻雜層。此摻雜層(15)在圖2a呈陰影線區域。
請看圖2b，在以下詳細說明第一區域(12)的電晶體晶胞(2)和第二區域(13)的電晶體晶胞(2)的接觸，接觸係晶由鍍金屬層達成，它們依圖1連接射極端子(10)。圖2b中，為了一目瞭然，第一區域(12)的電晶體晶胞(2)和第二區域(13)的電晶體晶胞(2)以及p摻雜的層(15)不示出。
第一區域(12)的電晶體晶胞(2)的射極端子經一第一導電層(16)連接，第一導電層(16)可經適當之輸出端子當作功率電晶體的輸出端，在其中提供第一區域(12)的電晶體晶胞(2)的輸出端。
第二區域(13)的電晶體晶胞(2)的射極端子(10)經一第二導電層(17)與至少一感測器端子連接。感測器端子可經一「結合金屬絲」與一外 界電阻連接(以下將說明)。第二導電層(17)也當作感測器端子，感測器端子在圖1中用圖號(18)示意表示，用此方式，在第二區域(13)的電晶體晶胞(2)的射極端子和感測器端子(18)間造成導電連接。
如圖2b所示，在第一導電層(16)和第二導電層(17)間有一漏縫。因此該區域的射極端子不互相連接。
如圖2a已說明者，在感測器端子(5)下方有p摻雜層(15)，它設在第一邊緣構造(14)的一外緣。此領域經接點(19)與第一導電層(16)連接，因此p摻雜層(15)可使關掉過程流出的電洞導離，所以它們不會造成第一區域的電晶體晶胞(2)的相鄰晶胞受負荷。
圖3中再用示意方式將圖1、圖2a及圖2b的電路裝置(1)再次簡述。第一區域(12)的電晶體晶胞(2)形成主晶胞IGBT(21)，第二區域(13)的電晶體晶胞(2)感測器晶胞IGBT(22)，二IGBT的各集極端子可與一端子(26)連接，閘極端子與另一端子(27)連接。主晶胞IGBT(21)的射極端子(10)與輸出端子(25)連接，感測器晶胞IGBT(22)的射極端子(10)經感測器端子(18)與一構件連接，舉例而言，它可為一外界電阻(23)，其中經由信號(24)可檢出輸出端子(25)的短路或過載狀態。
以下說明本發明其他實施例。在此主要說明與圖2的實施例的不同。
圖4中，除了第二區域(13)的電晶體晶胞(2)外，沿感測器端子(18)的方向設另一p摻雜區域(15’)，它與p摻雜區域(15)隔開，此另一p摻雜區域(15’)經其他接點(19’)與第二導電層(17)(圖4未示)連接。
圖5顯示第二區域(13)電晶體晶胞(2)的設置的一變更例，第 二區域(13)的電晶體晶胞(2)在此實施例設成長方形。此外也可考慮將第二區域(13)的電晶體晶胞(2)作其他設置，它可和製造程序合一，因此可將第二區域(13)的電晶體晶胞(2)設成任意之多角形，特別是半圓形或近似半圓的多角形，或長方形或正方形。
圖6顯示第一區域(12)的電晶體晶胞(2)的設置和第二區域(13)的電晶體晶胞(2)的設置。在此實施例中，第一區域(12)的電晶體晶胞(2)的設置和第一區域(13)的電晶體晶胞(2)的設置互相隔較大距離(30)。雖然在前述實施例，第一區域(12)的電晶體晶胞(2)和第二區域(13)的電晶體晶胞(2)之的距離只略大於第一區域(12)的電晶體晶胞(2)的直徑，在圖6的距離(30)舉例而言，可為電晶體晶胞(2)的直徑的十倍。
圖7顯示的實施例中，第二區域(13)的電晶體晶胞(2)被一第二晶胞領域界限(14)圍住，它可再做成雙渠溝構造，第二區域(13)的電晶體晶胞(2)不埋入第一區域(12)的電晶體晶胞(2)中或被它們部分圍住，而係設成遠離第一區域(12)的電晶體晶胞(2)。在此例設的厚氧化物層的一相關開口可使之連接到感測器端子(15)。
第二區域(13)的電晶體晶胞(2)被另一p摻雜層(15’)圍住，第一區域(12)的電晶體晶胞(2)在第一晶胞領域界限(14)外部p摻雜層(15)圍住，p摻雜層(15)(15’)互相隔開，p摻雜層(15)和上述實施例相似，用接點(19)與第一導電層(16)連接，另一p摻雜層(15’)經由另外的接點(19’)與第二導電層(17)連接。導電層(16)(17)再互相隔開，在此例，摻雜層(15)(15’)在接點(19’)互迫分開，但這些漏縫也可在(19)和(19’)間延伸，對於導電層(16)(17)間的間隔縫情形也是如此。
與此不同者，圖8中，第二區域(13)的電晶體晶胞(2)和感測器端子(18)一齊埋入第一區域(12)的電晶體晶胞(2)的場中。在此，晶胞領域界限(14)設成使它圍住感測器端子(18)。
(2)‧‧‧電晶體晶胞
(12)‧‧‧第一區域
(13)‧‧‧第二區域
(14)‧‧‧晶胞領域界限
(15)‧‧‧p摻雜層

Claims (8)

  1. 一種在一功率半導體中的電流感測器用的半導體裝置，該半導體裝置在一基材上有電晶體晶胞(2)的多重設置，該電晶體晶胞(2)具有被絕緣的閘電極，其射極端子(10)在一第一區域(12)經一第一導電層與至少一輸出端子(25)連接，而其射極端子(10)在一第二區域(13)經一第二導電層(17)與至少一感測器端子(18)連接，該感測器端子(18)設在一第一晶胞領域界限(14)外，該第一晶胞領域界限(14)包圍住該第一區域(2)的電晶體晶胞(2)和第二區域(13)的電晶體晶胞(2)，其中在該第二區域(13)的電晶體晶胞(2)和該感測器端子(18)之間形成一和與該第一晶胞領域界限(14)相關的渠溝構造，有一個與該第一導電層(16)連接的摻雜層(15)沿著朝向該基材(1)的一外緣的方向接到該渠溝構造，該摻雜層(18)設在該感測器端子下方。
  2. 如申請專利範圍第1項之半導體裝置，其中：該渠溝構造設計成一種雙渠溝構造形式。
  3. 如申請專利範圍第1或第2項之半導體裝置，其中：該第二區域(13)的電晶體晶胞(2)設成一半圓形、長方形或正方形或其他多角形的形狀。
  4. 如申請專利範圍第1或第2項之半導體裝置，其中：該第一區域(12)的電晶體晶胞(2)至少部分地圍住該第二區域(13)的電晶體晶胞(2)，且至少部分地圍住其三邊。
  5. 如申請專利範圍第1或第2項之半導體裝置，其中：該第一區域(12)的電晶體晶胞(2)完全圍住該第二區域(13)的電晶體晶胞(2)以及該第二導電層(17)。
  6. 如申請專利範圍第1或第2項之半導體裝置，其中：該第二區域(13)的電晶體晶胞(2)設成在空間上與該第一區域(12)的電晶體晶胞(2)分開。
  7. 如申請專利範圍第6項之半導體裝置，其中：該感測器端子(18)設成一絕緣層上方的鍍金屬面形式，其層厚度比一閘介電質的層厚度更大。
  8. 如申請專利範圍第6項之半導體裝置，其中：該第二區域(13)的電晶體晶胞(2)被一第二晶胞領域界限(14’)圍住。
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