CN104106136A - 在功率半导体中用于电流传感器的半导体布置 - Google Patents

在功率半导体中用于电流传感器的半导体布置 Download PDF

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CN104106136A
CN104106136A CN201380008975.2A CN201380008975A CN104106136A CN 104106136 A CN104106136 A CN 104106136A CN 201380008975 A CN201380008975 A CN 201380008975A CN 104106136 A CN104106136 A CN 104106136A
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semiconductor arrangement
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T·雅克
T·赫尔
C·普伦特克
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Robert Bosch GmbH
Infineon Technologies AG
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Abstract

本发明涉及一种用于功率半导体中的电流传感器的半导体布置，所述半导体布置在衬底(1)上包括具有绝缘栅电极的晶体管单元(2)的多重布置，所述晶体管单元的发射极端子(10)在第一区域(12)中通过第一导电层(16)与至少一个输出端子(25)连接，并且其发射极端子(10)在第二区域(13)中通过第二导电层(17)与至少一个传感器端子(18)连接，所述至少一个传感器端子布置在第一单元区域边界(14)之外，所述第一单元区域边界包围所述第一区域(12)的晶体管单元(2)和所述第二区域(13)的晶体管单元(2)，其中，在所述第二区域(13)的晶体管单元(2)和所述传感器端子(18)之间构造有属于所述第一单元区域边界(14)的沟槽结构，在朝所述衬底(1)的外部边缘的方向上，与所述第一导电层(16)连接的掺杂层(15)连接所述沟槽结构。

Description

在功率半导体中用于电流传感器的半导体布置
技术领域
本发明涉及一种在功率半导体中用于电流传感器、尤其用于具有绝缘栅电极的双极型晶体管、也称为绝缘栅双极晶体管(Insulated Gate BipolarTransistor，IGBT)的类型的功率半导体的半导体布置。
背景技术
功率半导体通常制造为竖直结构并且具有多个晶体管单元。其中，在半导体衬底的前侧上形成栅级结构和发射极结构，所述栅级结构和发射极结构通过至少一个p-n结与在背侧上构造为全面积的金属化部的集电极层连接。在功率晶体管中，所述单元结构在衬底的大的区域上重复，从而能够接通高的电流。然而，在此应注意避免短路状态或者过载状态。因此，从普遍的现有技术已知，在输出端子处安装分流电阻，以便探测在主电路中可能出现的短路或者过载状态。
此外，以下是现有技术：通过传感器端子分支出发射极的一个区域或者说发射极单元的一部分并且将在那里流动的电流作为信号使用。典型地，传感器端子位于发射极区域内并且完全地或者部分地以发射极单元填充。在完全填充的情况下，传感器单元非常紧贴地嵌入主发射极中，并且可以预期：传感器单元的行为仅仅少许地偏离主发射极单元的行为。但是，通过发射极端子和传感器端子的尺寸比例预给定传感器电流与主电流的固定比例。仅仅部分地填充的情况提供以下优点：更自由地设计该比例，但是为此失去紧贴的嵌入，并且存在无单元的区域，在所述无单元的区域中在导电的状态下也形成载流子等离子体。
在使用或者已经在设计IGBT时应注意：在关断情况下通过发射极流出的载流子不使各个晶体管单元过载。在具有n沟道的IGBT的例子中，通过发射极流出的载流子种类以空穴存在。特别是对于位于传感区域的和主发射极区域的边缘处的单元而言，存在过载的危险和闩锁效应(Latch-up)的触发，这是因为，在无单元的区域中在无发射极接触的情况下也形成载流子等离子体。一方面，所述不包含单元的中间区域(无单元的区域)在传感器端子不完全填充的情况下存在，但该中间区域也是由将与两个发射极区域连接的导电层隔开的必要性而引起。
发明内容
本发明的任务在于，减少与无单元的区域邻近的单元的通过位于无单元的区域中的载流子等离子体的在关断时流出的空穴引起的负荷，并且同时能够实现传感器单元尽可能紧贴地嵌入主发射极中。
所述任务通过用于功率半导体的半导体布置来解决，所述半导体布置在衬底上包括具有绝缘栅电极的晶体管单元的多重布置，所述晶体管单元的发射极端子在第一区域中通过第一导电层与至少一个输出端子连接，并且其发射极端子在第二区域中通过第二导电层与至少一个传感器端子连接。传感器端子布置在包围第一区域的晶体管单元和第二区域的晶体管单元的第一单元区域边界之外。在第二区域的晶体管单元和传感器端子之间构造有属于第一单元区域边界的沟槽结构，在朝衬底的外部边缘的方向上，与第一导电层连接的掺杂层连接所述沟槽结构，并且，此外，所述沟槽结构在第一区域的晶体管和第二区域的晶体管之间延伸。
根据本发明，由IGBT单元组成的发射极被分成两个单元组。一方面形成主单元，所述主单元借助于第一导电层与发射极输出端连接。该单元组占据电路布置的衬底区域的最大的部分。与第二导电层连接的、较小的部分作为传感器单元提供，并且作为电流传感器使用，从而通过外部的电阻能够产生电压信号，所述电压信号可被再处理以探测短路和过载电流。所述连接第一导电层的掺杂区域用于在关断时流出的空穴的导出(ableiten)，从而所述空穴不对邻近的主单元加负荷，这可能会导致锁定(Latch)事件的危险增大并且因此导致芯片的损坏。
通过以下方式解决本发明的任务：将传感器的端子置于有效的单元区域之外在单元区域边界后方。来自该端子区域的空穴通过连接到主发射极的导电层上的掺杂区域导走。因此，还能够与传感器端子的尺寸和形状无关地设计传感器区域的尺寸和形状。
根据本发明的另一种构型，第二区域的晶体管单元以任意的多边形的形状、优选以半圆或者接近半圆的多边形或者矩形或者正方形的形状布置。
所述布置可以借助于通常的布局程序以简单的方式构造为重复的结构，并且可借助于功率半导体的通用的制造工艺实现。
根据本发明的另一种构型，第一区域的晶体管单元至少部分地、优选在三个侧面上包围第二区域的晶体管单元。
根据本发明的另一种构型，第一区域的晶体管单元完全地包围第二区域的晶体管单元。
根据本发明的另一种构型，第二区域的晶体管单元与第一区域的晶体管单元在空间上隔开地布置。
在该实施方式中，电流传感器单元没有紧贴地嵌入主单元中，而是与主单元远离地以自身的单元区域边界被环绕。这相当于隔开的较小的IGBT半导体，所述较小的IGBT半导体的等离子体在接通的状态下或者在接通过程期间视间距而定地与主IBGT的等离子体少量地交互作用直至完全不交互作用。然而，两个部分始终还可以看作为一个IGBT芯片，因为它们在朝芯片的边缘的方向上被共同的边缘封闭结构环绕。
根据本发明的另一种构型，传感器端子作为金属化区域布置在绝缘层之上，所述绝缘层的层厚度大于栅级电介质的层厚度。
在这种实施方式中，传感器端子可被放置在厚氧化物之上的任意位置上。
根据本发明的另一种构型，第二区域的晶体管单元被第二单元区域边界环绕。
尤其在当传感器单元远离主单元布置时才使用该实施方式。
根据本发明的另一种构型，传感器端子和第二区域的晶体管单元布置在单元区域边界之外。
在该实施方式中，在传感器端子和第二区域的晶体管单元之间没有双沟槽结构。
第二导电层可以在单元区域边界的区域内具有切口，第一导电层与掺杂层在该切口中连接。这导致进一步地改善在关断过程中流出的空穴的导出。
附图说明
以下根据实施例参照附图详细解释本发明。附图示出：
图1在剖面图中示出晶体管单元；
图2a以俯视图示出根据本发明的根据本发明的第一实施方式的半导体布置；
图2b以另外的俯视图示出根据本发明的根据本发明的第一实施方式的半导体布置；
图3示出根据图2a的实施方式的另一示意图；
图4根据本发明的另一种实施方式以俯视图示出根据本发明的半导体布置；
图5根据本发明的另一种实施方式以俯视图示出根据本发明的半导体布置；
图6根据本发明的另一种实施方式以俯视图示出根据本发明的半导体布置；
图7根据本发明的另一种实施方式以俯视图示出根据本发明的半导体布置，和
图8根据本发明的另一种实施方式以俯视图示出根据本发明的半导体布置。
在附图中相同的或者起相同作用的元件设有一致的参考标记。
具体实施方式
在图1中示出电路布置1的剖面图，该电路布置为用于具有绝缘栅电极(IGBT)3的多个晶体管单元2的基础单元。如从图1中得知，例如p+型掺杂的衬底4在背侧上包括通常作为金属层施加的集电极端子5。在集电极端子5和衬底4之上施加在本例中n型掺杂的缓冲层6，在该缓冲层上紧接是同样n型掺杂的外延层7。在外延层7中，例如通过离子注入来布置p型掺杂的槽8，在所述槽中分别布置有两个n型掺杂的岛9，所述两个n型掺杂的与p型掺杂的槽8一同部分地被发射极端子10覆盖。
栅电极3被由硅氧化物所形成的绝缘层11环绕，所述绝缘层也可以布置在晶体管单元2之外。整体上，在所示出的例子中获得用于n沟道IGBT的n+pnp+结构。然而，也可考虑，在其他的IGBT类型中、例如在p沟道IGBT或者具有竖直结构的IGBT中应用本发明。
以下描述根据本发明的第一实施方式的电路布置1。在图2a中以俯视图、即以具有发射极端子10的上侧的俯视图示出电路布置1。如从图2a中可得知，电路布置1包括多个晶体管单元2，所述多个晶体管单元布置在第一区域12和第二区域13中。此外，在图2a中所示出的布置应理解为仅仅是示例性的。
晶体管单元2基本上完全地覆盖第一区域12或者第二区域13，并且能够以任意的图案布置，所述图案不是必须需要规则的。第一区域12的晶体管单元2并联连接并且用于功率半导体。
第二区域13的晶体管单元2同样并联连接并且用于电流传感器，如以下还将详细解释地那样。第一区域12的晶体管单元2可被称为主单元，而第二区域13的晶体管单元可被称作传感器单元。
第一区域12的晶体管单元2和第二区域13的晶体管单元2被第一单元区域边界环绕，其中，单元区域边界设有参考标记14。第一单元区域边界14以沟槽的形式构造在衬底中。但也是可能的是，使用由两个在衬底中并排地延伸的沟槽形成的双沟槽结构。在第一单元区域边界14之外的区域设有掺杂层15，所述掺杂层在所示出的实施例中为p型掺杂层。所述掺杂层15在图2a中表示为阴影区。
参照图2b，以下详细阐述第一区域12的晶体管单元2和第二区域13的晶体管单元2的接通。所述接通在金属化层之上进行，该金属化层将根据图1的发射极端子10连接起来。在图2b中，为了更好的可显示性，未未绘出第一区域12的晶体管单元2和第二区域13的晶体管单元2以及p型掺杂层15。
第一区域12的晶体管单元2的发射极端子通过第一导电层16连接。所述第一导电层16可通过合适的输出端子作为功率晶体管的输出端使用，在所述功率晶体管中提供第一区域12的晶体管单元2的输出端。
第二区域13的晶体管单元2的发射极端子10通过第二导电层17与至少一个传感器端子连接。所述传感器端子可通过键合引线与外部的电阻连接，如还将在下面阐述的那样。第二导电层17也作为传感器端子起作用。所述传感器端子在图1中示意性地通过参考标记18来表示。以此方式，在第二区域13的晶体管单元2的发射极端子和传感器端子18之间建立电连接。
如可从图2b中得知的那样，在第一导电层16和第二导电层17之间张开一个空隙，从而这些区域的发射极端子不相互连接。
如已经与图2a相关联地阐述的那样，p型掺杂层15位于传感器端子18下方，所述p型掺杂层布置在第一边缘结构4的外部边缘处。该区域通过触点19与第一导电层16连接。因此，p型掺杂层15能够实现在关断过程中流出的空穴的导出，从而所述空穴不对第一区域12的晶体管单元2的相邻的单元加负荷。
在图3中再次示意性地概括根据图1、图2a和2b的电路布置1。第一区域12的晶体管单元2形成主单元IGBT 21。第二区域13的晶体管2形成传感器单元IGBT 22。两个IGBT的相应的集电极端子能够与端子26连接，栅极端子能够与其他的端子27连接。主单元IGBT 21的发射级端子10与输出端子25连接。传感器单元IGBT 22的发射极端子10通过传感器端子18与例如可为外部的欧姆电阻23的结构元件连接，其中，通过信号24能够探测在输出端子25处的短路状态或者过载状态。
以下描述本发明的另外的实施方式。在此主要说明与图2所示出的实施例相关联的差别。
在图4中，在第二区域13的晶体管单元2旁边，沿着传感器端子18的方向布置有另一个p型掺杂的区域15’，其与所述p型掺杂的区域15隔开。所述另一个p型掺杂的区域15’通过另外的触点19’与第二导电层17(未在图4中示出)连接。
在图5中示出第二区域13的晶体管单元2的布置的变型。第二区域13的晶体管单元2在该实施方式中矩形地布置。此外，也可考虑，设置用于第二区域13的晶体管单元2的另外的布置，所述另外的布置能够与制造工艺兼容。因此，可能的是，第二区域13的晶体管单元2以任意的多边形的形状、优选以半圆或者接近半圆的多边形或者矩形或者正方形的形状布置。
在图6中示出第一区域12的晶体管单元2的和第二区域13的晶体管单元2的布置的另外的变型。在该实施方式中，第一区域12的晶体管单元2和第二区域13的晶体管单元2相对于彼此具有较大的间距30。由于在到目前为止所示出的实施方式中在第一区域12的晶体管单元2和第二区域13的晶体管单元2之间的间距仅仅略微超过晶体管单元2的直径，所以根据图6的间距30例如可以相当于晶体管单元2的直径的十倍。
在图7中示出一个实施例，在该实施例中，第二区域13的晶体管单元2被第二单元区域边界14’环绕，所述第二单元区域边界又可以实施为双沟槽结构。在此，第二区域13的晶体管单元2不嵌入第一区域12的晶体管单元2中或者不被其部分地环绕，而是远离第一区域12的晶体管单元2地布置。布置在该区域中的厚氧化物的相应的开口允许至传感器端子18的连接。
第二区域13的晶体管单元2被另外的p型掺杂层15’环绕。第一区域12的晶体管单元2在第一单元区域边界14之外被p型掺杂层15环绕。p型掺杂层15和15’相互隔开。p型掺杂层15类似于以上所描述的实施方式地借助于触点19与第一导电层16连接。另外的p型掺杂层15’通过另外的触点19’与第二导电层17连接。所述导电层16和17又相互隔开。在该例子中，掺杂层15和15’在触点19’附近隔开。但是，该空隙也同样可以在19和19’之间的其他地方延伸。类似的适用于在导电层16和17之间的分隔空隙。
与此不同，在图8中，第二区域13的晶体管单元2与传感器端子18一同嵌入第一区域12的晶体管单元2的区域中。在此，如此布置单元区域边界14，使得它环绕传感器端子18。

Claims (9)

1.一种用于功率半导体中的电流传感器的半导体布置，所述半导体布置在衬底(1)上包括具有绝缘栅电极的晶体管单元(2)的多重布置，所述晶体管单元的发射极端子(10)在第一区域(12)中通过第一导电层(16)与至少一个输出端子(25)连接，并且其发射极端子(10)在第二区域(13)中通过第二导电层(17)与至少一个传感器端子(18)连接，所述至少一个传感器端子布置在第一单元区域边界(14)之外，所述第一单元区域边界包围所述第一区域(12)的晶体管单元(2)和所述第二区域(13)的晶体管单元(2)，其中，在所述第二区域(13)的晶体管单元(2)和所述传感器端子(18)之间构造有属于所述第一单元区域边界(14)的沟槽结构，在朝所述衬底(1)的外部边缘的方向上，与所述第一导电层(16)连接的掺杂层(15)连接所述沟槽结构。
2.根据权利要求1所述的半导体布置，在所述半导体布置中所述沟槽结构构造为双沟槽结构。
3.根据权利要求1或2所述的半导体布置，在所述半导体布置中所述第二区域(13)的晶体管单元(2)以多边形的形状、优选以半圆或者六边形或者矩形或者正方形的形状布置。
4.根据权利要求1至3中任一项所述的半导体布置，在所述半导体布置中所述第一区域(12)的晶体管单元(2)至少部分地、优选在三个侧面上包围所述第二区域(13)的晶体管单元(2)。
5.根据权利要求1至3中任一项所述的半导体布置，在所述半导体布置中所述第一区域(12)的晶体管单元(2)完全地包围所述第二区域(13)的晶体管单元(2)和所述第二导电层(17)。
6.根据权利要求1至5中任一项所述的半导体布置，在所述半导体布置中所述第二区域(13)的晶体管单元(2)与所述第一区域(12)的晶体管单元(2)在空间上隔开地布置。
7.根据权利要求6的半导体布置，在所述半导体布置中，所述传感器端子(18)作为金属化区域布置在绝缘层之上，所述绝缘层的层厚度大于栅级电介质(11)的层厚度。
8.根据权利要求6或7的半导体布置，在所述半导体布置中所述第二区域(13)的晶体管单元(2)被第二单元区域边界(14’)环绕。
9.根据权利要求1至8中任一项所述的半导体布置，在所述半导体布置中所述传感器端子(18)和所述第二区域(13)的晶体管单元(2)布置在所述单元区域边界(14)之外。
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