EP2275860B1 - Dichtungs- und Verdrahtungsanordnung für ein Anzeigesystem des Aktivmatrix-Typs - Google Patents

Dichtungs- und Verdrahtungsanordnung für ein Anzeigesystem des Aktivmatrix-Typs Download PDF

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Publication number
EP2275860B1
EP2275860B1 EP10182874.7A EP10182874A EP2275860B1 EP 2275860 B1 EP2275860 B1 EP 2275860B1 EP 10182874 A EP10182874 A EP 10182874A EP 2275860 B1 EP2275860 B1 EP 2275860B1
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EP
European Patent Office
Prior art keywords
wiring lines
substrate
display device
sealing member
lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP10182874.7A
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English (en)
French (fr)
Other versions
EP2275860A2 (de
EP2275860A3 (de
Inventor
Shunpai Yamazaki
Jun Koyama
Mitsuaki Osame
Kazutaka Inukai
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Publication date
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Publication of EP2275860A2 publication Critical patent/EP2275860A2/de
Publication of EP2275860A3 publication Critical patent/EP2275860A3/de
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Publication of EP2275860B1 publication Critical patent/EP2275860B1/de
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/02—Details
    • H05B33/04—Sealing arrangements, e.g. against humidity
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/841—Self-supporting sealing arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/842—Containers
    • H10K50/8426—Peripheral sealing arrangements, e.g. adhesives, sealants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/871—Self-supporting sealing arrangements
    • H10K59/8722—Peripheral sealing arrangements, e.g. adhesives, sealants

Definitions

  • the present invention relates to a display device having a sealing structure. Specifically, the invention relates to an active matrix display device using a semiconductor element (an element formed of a semiconductor thin film) and to electronic equipment employing the active matrix display device as its display unit.
  • a semiconductor element an element formed of a semiconductor thin film
  • An electro-optical device such as an EL display device having an EL element has lately been attracting attention as a flat display.
  • the EL element has a structure in which an EL layer is sandwiched between a pair of electrodes (an anode and a cathode).
  • the EL layer generally takes a laminate structure.
  • a typical example of the laminate structure is the one proposed by Tang et al. of Eastman Kodak Company, and consists of a hole transportation layer, a light emitting layer and an electron transportation layer. This structure has so high a light emission efficiency that it is employed in almost all of EL display devices that are under development at present.
  • the EL layer laminate structure examples include a structure consisting of a hole injection layer, a hole transportation layer, a light emitting layer, and an electron transportation layer which are layered in this order on an anode, and a structure consisting of a hole injection layer, a hole transportation layer, a light emitting layer, an electron transportation layer, and an electron injection layer which are layered in this order on an anode.
  • the light emitting layer may be doped with a fluorescent pigment or the like.
  • an EL layer all of the layers provided between a cathode and an anode are collectively called an EL layer. Accordingly, the hole injection layer, a hole transportation layer, a light emitting layer, an electron transportation layer, an electron injection layer, etc. mentioned above are all included in the EL layer.
  • a given voltage is applied to the EL layer structured as above from the pair of electrodes, whereby recombination of carriers takes place in the light emitting layer to emit light.
  • An EL element emitting light is referred to herein as EL element being driven.
  • the EL element in this specification refers to a light emitting element composed of an anode, an EL layer, and a cathode.
  • the EL element in this specification refers to both a light emitting element that utilizes light emission from a singlet exciton (fluorescence) and a light emitting element that utilizes light emission from a triplet exciton (phosphorescence).
  • An active matrix structure is given as one of structures for EL display devices.
  • Fig. 9 shows an example of the structure of a pixel portion in an active matrix EL display device.
  • each pixel has thin film transistors (hereinafter referred to as TFTs).
  • TFTs thin film transistors
  • Each pixel has a switching TFT 901 whose gate electrode is connected to one of gate signal lines (G1 to Gy) for inputting a selection signal from a gate signal line driving circuit.
  • the switching TFT 901 in each pixel has a source region and a drain region one of which is connected to one of source signal lines (S1 to Sx) for inputting a signal from a source signal line driving circuit and the other of which is connected to a gate electrode of an EL driving TFT 902 and to one of electrodes of a capacitor 903 that is provided in each pixel.
  • the other electrode of the capacitor 903 is connected to one of power supply lines (V1 to Vx).
  • the EL driving TFT 902 provided in each pixel has a source region and a drain region one of which is connected to one of the power supply lines (V1 to Vx) and the other of which is connected to an EL element 904 that is provided in each pixel.
  • the switching TFT 901 that is connected to the gate signal line G1 is turned ON. If the source signal line driving circuit inputs a signal to the source signal lines Si to Sx at this point, the EL driving TFT 902 is turned ON in every pixel to which the signal is inputted. Thus a current flows into the EL element 904 from its associated power supply line (one of V1 to Vx), causing the EL element 904 to emit light. This operation is repeated for all of the gate signal lines G1 to Gy to display an image.
  • the EL element 904 has an anode, a cathode, and an EL layer that is provided between the anode and the cathode. If the anode of the EL element 904 is connected to the source region or the drain region of the EL driving TFT 902, the anode of the EL element 904 serves as a pixel electrode whereas the cathode thereof serves as an opposite electrode. On the other hand, if the cathode of the EL element 904 is connected to the source region or the drain region of the EL driving TFT 902, the cathode of the EL element 904 serves as the pixel electrode whereas the anode thereof serves as the opposite electrode.
  • the electric potential of the opposite electrode is called herein as an opposite electric potential.
  • a power supply for giving the opposite electric potential to the opposite electrode is called an opposite power supply.
  • the electric potential difference between the electric potential of the pixel electrode and the electric potential of the opposite electrode corresponds to an EL driving voltage, which is applied to the EL layer.
  • An organic EL layer has a problem of being degraded by moisture or oxygen. For that reason, it is common to seal the device after the EL layer is formed by a UV-curable resin in a nitrogen atmosphere instead of exposing the device to the air.
  • Figs. 4A and 4B show an example of sealing the EL display device.
  • Fig. 4A is a top view of the EL display device.
  • a pixel portion 402 having EL elements, a gate signal line driving circuit 403, and a source signal line driving circuit 404 are formed on an insulating substrate 41.
  • a sealing member 401 is formed on the insulating substrate 41 so as to surround the pixel portion 402, the gate signal line driving circuit 403 and the source signal line driving circuit 404.
  • an opening (not shown) is formed as an inlet for injecting a filer 43 later.
  • a spacer (not shown) is sprayed to bond a covering member 42.
  • the sealing member 401 is cured by irradiation of ultraviolet rays, the filler 43 is filled in a region enclosed with the covering member 42 and the sealing member 401.
  • the inlet for the filler 43 is then sealed by an end-sealing material (not shown).
  • Fig. 4B is a sectional view taken along the line A-A' in Fig. 4A .
  • components shown in Fig. 4B are limited to a TFT 413 constituting the gate signal line driving circuit 403, and an EL driving TFT 414 and an EL element 417 which constitute the pixel portion 402.
  • the insulating substrate 41 is referred to as pixel substrate.
  • the EL element 417 is composed of a pixel electrode 407, an EL layer 416, and an opposite electrode 408.
  • the covering member 42 is set in place by the sealing member 401.
  • the filler 43 is sealed in a space between the pixel substrate 41 and the covering member 42.
  • a hygroscopic substance (not shown) is added to the filler 43. In this way, degradation of the EL element 417 due to moisture is avoided.
  • Denoted by 406 is a gate insulating film for the TFT 413 and for the EL driving TFT 414, and 415 denotes an interlayer insulating film.
  • a signal to be inputted to the pixel portion 402, the gate signal line driving circuit 403, and the source signal line driving circuit 404 is inputted through wiring lines 412 (412a to 412c) from an FPC (flexible printed circuit) substrate 410 (see Fig. 4A ).
  • the wiring lines 412 run between the pixel substrate 41 and the sealing member 401 to connect the FPC substrate 410 with the driving circuits.
  • the FPC substrate 410 is connected at an external input terminal 409 to the wiring lines 412 through an anisotropic conductive film (not shown).
  • Any EL display device has to seal its EL element by bonding a pixel substrate to a covering member using a sealing member in order to prevent degradation of the EL element.
  • portions where the sealing member and the driving circuits are formed do not display an image.
  • these portions that are not used to display an image occupy a great proportion to hinder the display devices from reducing their sizes.
  • JP 11 052 394 discloses a liquid crystal display in which the seal is cured by irradiation with UV light from the active matrix side.
  • the counter substrate a has a black matrix in the region of the seal. Uniform irradiation is facilitated by arranging slits or ITO transparent bridges in the wiring lines where they cross the seal perpendicularly. These lines run between the seal and the substrate at the their intersection with the seal.
  • the present invention has been made in view of the above and an object of the present invention is therefore to reduce the area of portions other than a pixel portion in a display device.
  • wiring lines are formed in a portion of a pixel substrate which is covered with a sealing member.
  • the width of each of the wiring lines is set to a width that allows the sealing member on the wiring lines to be sufficiently exposed to ultraviolet rays when the sealing member is irradiated with ultraviolet rays through the wiring lines.
  • the area where the wiring lines around the pixel portion and the driving circuits occupy and the area where the sealing member occupies are thus reduced in the display device, whereby the display device can be made smaller.
  • the description given here is about an EL display device with wiring lines formed in a portion of a pixel substrate which is covered with a sealing member.
  • the portion of the pixel substrate which is covered with the sealing member is called a sealed region.
  • Fig. 1A shows a top view of an EL display device according to the present invention.
  • a pixel substrate 701 On a pixel substrate 701, a pixel portion 711, a gate signal line driving circuit 702, and a source signal line driving circuit 703 are formed.
  • a sealing member 704 is formed surrounding the pixel portion and the driving circuits, so that a covering member 705 is bonded by the sealing member.
  • FPC substrates 706 are connected to the top face of the pixel substrate 701 by external input terminals 707.
  • Wiring lines 708 are a plurality of wiring lines such as signal lines and power supply lines, which receive signals from the FPC substrates 706 through the external input terminals 707 to transmit the signals to the gate signal line driving circuit 702.
  • Wiring lines 709 are a plurality of wiring lines such as signal lines and power supply lines, which receive signals from the FPC substrates 706 through the external input terminals 707 to transmit the signals to the source signal line driving circuit 703.
  • Wiring lines 710 (wiring lines 710a and wiring lines 710b) are a plurality of wiring lines such as power supply lines, which receive signals from the FPC substrates 706 through the external input terminals 707 to transmit the signals to the pixel portion 711.
  • the wiring lines 708 to 710 are formed in the sealed region.
  • Fig. 1B is a sectional view taken along the line A-A' in Fig. 1A .
  • components shown in Fig. 1B are limited to a TFT 712 as an element constituting the gate signal line driving circuit 702, and an EL driving TFT 713 and an EL element 721 as elements that constitute the pixel portion 711.
  • Either a source region of the EL driving TFT 713 or a drain region thereof is connected to a pixel electrode 714 of the EL element 721 in order to control a current flowing into the EL element 721.
  • 716 in Fig. 1B is an interlayer insulating film, 715, an EL layer, 717, an insulating film, 718, an opposite electrode, 719, a filler, and 720, a gate insulating film.
  • the interlayer insulating film 716 is formed of an inorganic material here.
  • the wiring lines 708 and the wiring lines 710a and 710b are formed from the same material that is used to form source wiring lines and drain wiring lines of the TFT 712 and of the EL driving TFT 713.
  • wiring lines 708 to 710 explanations of the wiring lines 709 are omitted because the wiring lines 709 are formed in the same way as the wiring lines 708 and the wiring lines 710a and 710b.
  • the sealing member 704 is often formed from a UV-curable material.
  • a material often used for the covering member 705 is a material having a light-shielding property. Therefore the sealing member 704 cannot be exposed and cured when the sealing member 704 is irradiated with ultraviolet rays from the covering member 705 side. Thus the irradiation of ultraviolet rays has to be made from the pixel substrate 701 side through the wiring lines 708 and the wiring lines 710a and 710b to expose the sealing member 704.
  • wiring lines 708 and the wiring lines 710a and 710b wiring lines having a narrower width are used as video signal lines and pulse lines.
  • power supply lines for supplying current to power supply lines for the pixel portion and power supply lines for the source signal line driving circuit and the gate signal line driving circuit have to be wiring lines having a width greater than the video signal lines and the pulse lines because a voltage inputted to these power supply lines is larger than a voltage inputted to the video signal lines and the pulse lines.
  • wiring lines having a large width is an obstacle when irradiating the sealing member with ultraviolet rays through the wiring lines, for the sealing member under the shade of the wiring lines is not irradiated with a sufficient amount of ultraviolet rays. Then there is a possibility is that the sealing member is not cured satisfactorily.
  • the present invention therefore provides wiring lines having the following configuration.
  • a schematic diagram of the configuration is shown in Fig. 3A.
  • Fig. 3A corresponds to an enlarged view of a part of the sealed region in Figs. 1A and 1B , and the part is denoted by 666.
  • Fig. 3A focuses on one power supply line 777 out of the wiring lines (first wiring lines) 710b.
  • the power supply line 777 is composed of wiring lines (second wiring lines) A1 to A6 connected in parallel to one another. Now, a description is given to the case where the sealing member 704 is irradiated with ultraviolet rays through the wiring line 777 configured as above.
  • one power supply line 777 here is composed of six wiring lines A1 to A6 connected in parallel to one another, the present invention is not limited thereto.
  • one wiring line may be composed of n (n is a natural number equal to or greater than 2) wiring lines (second wiring lines) A1 to An connected in parallel to one another.
  • Fig. 3B is a sectional view taken along the line A-A' in Fig. 3A .
  • the same reference symbols denote the same components.
  • portions of the sealing member on the wiring lines A1 to A6, which are denoted by 660 are shaded.
  • a width L of each wiring line is sufficiently small and a spacing S between two wiring lines is large enough, the ultraviolet rays irradiated reach the shaded portions 660.
  • portions 600 right on the wiring lines are not exposed to the ultraviolet rays, the portions 600 are small enough as compared with the case where the width of a wiring line is large and, overall, the sealing member can be exposed sufficiently.
  • the width L of each of the wiring lines A1 to A6 is 100 ⁇ m to 200 ⁇ m whereas the spacing S between adjacent lines in the wiring lines A1 to A6 is 50 ⁇ m to 150 ⁇ m, and L/S is within 0.7 to 1.5. If wiring lines configured as above are used, the sealing member on these wiring lines is sufficiently exposed to ultraviolet rays through the wiring lines, so that the sealing member is cured satisfactorily.
  • the width L of each of the wiring lines A1 to A6 is equal to or less than 150 ⁇ m whereas the spacing L between adjacent lines in the wiring lines A1 to A6 is equal to or more than 100 ⁇ m, and L/S is 1.5 or less.
  • the sealing member on the wiring lines can be cured enough.
  • the one power line 777 is focused out of the wiring lines 710b in Figs. 3A and 3B , a similar configuration can be applied to the other wiring lines formed in the sealed region which can cause a trouble if their width is set improperly.
  • the wiring lines can be formed in the sealed region. This reduces the area of the regions other than the pixel portion, thereby making it possible to reduce the display device in size.
  • Fig. 2A is a top view of an EL display device according to the present invention.
  • a pixel substrate 701 On a pixel substrate 701, a pixel portion 711, a gate signal line driving circuit 702, and a source signal line driving circuit 703 are formed.
  • a sealing member 704 is formed surrounding the pixel portion and the driving circuits, so that a covering member 705 is bonded by the sealing member.
  • FPC substrates 706 are connected to the top face of the pixel substrate 701 by external input terminals 707.
  • Wiring lines 708 are a plurality of wiring lines such as signal lines and power supply lines, which receive signals from the FPC substrates 706 through the external input terminals 707 to transmit the signals to the gate signal line driving circuit 702.
  • Wiring lines 709 are a plurality of wiring lines such as signal lines and power supply lines, which receive signals from the FPC substrates 706 through the external input terminals 707 to transmit the signals to the source signal line driving circuit 703.
  • Wiring lines 710a and wiring lines 710b are a plurality of wiring lines such as power supply lines, which receive signals from the FPC substrates 706 through the external input terminals 707 to transmit the signals to the pixel portion 711.
  • the wiring lines 708 to 710 are formed in the sealed region.
  • Fig. 2B is a sectional view taken along the line A-A' in Fig. 2A .
  • components shown in Fig. 2B are limited to a TFT 712 as an element constituting the gate signal line driving circuit 702, and an EL driving TFT 713 and an EL element 721 as elements that constitute the pixel portion 711.
  • Either a source region of the EL driving TFT 713 or a drain region thereof is connected to a pixel electrode 714 of the EL element 721 in order to control a current flowing into the EL element 721.
  • 716 in Fig. 2B is an interlayer insulating film, 715, an EL layer, 717, an insulating film, 718, an opposite electrode, 719, a filler, and 720, a gate insulating film.
  • the interlayer insulating film 716 is formed of an organic material here.
  • the wiring lines 708 and the wiring lines 710a and 710b are formed from the same material that is used to form source wiring lines and drain wiring lines of the TFT 712 and of the EL driving TFT' 713.
  • wiring lines 708 to 710 explanations of the wiring lines 709 are omitted because the wiring lines 709 are formed in the same way as the wiring line 708 and the wiring lines 710a and 710b.
  • the interlayer insulating film 716 is formed of an organic material, and adhesion is poor between the organic material and the wiring lines 708 and the wiring lines 710a and 710b if they are formed directly on the organic material. Forming the wiring lines directly on the organic material also has a problem of degrading the wiring lines 708 and the wiring lines 710a and 710b, for impurities are introduced from the organic material to the material used to form the wiring lines 708 and the wiring lines 710a and 710b. For that reason, the wiring lines 708 and the wiring lines 710a and 710b have to be formed after removing the interlayer insulating film 716 formed of an organic material.
  • the step of removing the interlayer insulating film 716 from a part where the wiring lines 708 and the wiring lines 710a and 710b are to be formed can be carried out when source wiring lines and drain wiring lines of the TFT 712 and the pixel TFT 713 are formed and contact holes reaching source regions of the TFTs 712 and 713 are formed.
  • the sealing member 704 is often formed from a UV-curable material.
  • a material often used for the covering member 705 is a material having a light-shielding property. Therefore the sealing member 704 cannot be cured when the sealing member 704 is irradiated with ultraviolet rays from the covering member side. Thus the irradiation of ultraviolet rays has to be made from the pixel substrate 701 side through the wiring lines 708 and the wiring lines 710a and 710b to cure the sealing member 704.
  • a wide wiring line is used for the wiring lines 708 and the wiring lines 710a and 710b, portions of the sealing member 704 which are shaded by the wiring lines cannot receive a sufficient amount of ultraviolet irradiation. Then the possibility is that the sealing member 704 is not cured satisfactorily.
  • this embodiment does not use a single wide wiring line for the wiring lines 708 and the wiring lines 710a and 710b.
  • Employed instead are a plurality of wiring lines connected in parallel to one another as shown in Figs. 3A and 3B .
  • the width L of each of the plural wiring lines is 100 ⁇ m to 200 ⁇ m whereas the spacing S between adjacent lines in the plural wiring lines is 50 ⁇ m to 150 ⁇ m, and the ratio of the width L of each of the plural wiring lines to the spacing S between adjacent lines in the plural wiring lines, namely, L/S is within 0.7 to 1.5. If wiring lines configured as above are used, the sealing member on these wiring lines is sufficiently exposed to ultraviolet rays through the wiring lines, so that the sealing member is cured satisfactorily.
  • the width L of each of the plural wiring lines is equal to or less than 150 ⁇ m whereas the spacing S between adjacent lines in the plural wiring lines is equal to or more than 100 ⁇ m, and L/S is 1.5 or less.
  • the sealing member on the wiring lines can be cured enough.
  • the wiring lines can be formed in the sealed region. This reduces the area of the regions other than the pixel portion, thereby making it possible to reduce the display device in size.
  • This embodiment describes a wiring example of power supply lines for supplying current to power supply lines for a pixel portion of an active matrix EL display device.
  • a current for driving the EL element 721 flows through the power supply lines of the wiring lines 710a and 710b to be inputted to the power supply lines for the pixel portion 711.
  • the power supply lines for the pixel portion 711 are supplied with current from two sources, namely, from the power supply lines of the wiring lines 710a and from the power supply lines of the wiring lines 710b.
  • the power supply lines for the pixel portion 402 is supplied with current from one source, namely, from the power supply lines of the wiring lines 412a.
  • the pixel portion of the active matrix EL display device according to the present invention is supplied with current at two points in the pixel portion.
  • Figs. 5A and 5B schematically illustrate wiring examples for the power supply lines. Shown in Fig. 5A is a case where one external input terminal connected to one FPC substrate is provided to supply current to the pixel portion at one point in the pixel portion.
  • Fig. 5B shows a case where an external input terminal is divided into two each connected to an FPC substrate (a first FPC substrate and a second FPC substrate) and provided in different places to supply current to the pixel portion at two points in the pixel portion.
  • Shown as the power supply lines are anode lines connected to the anodes of the EL elements and cathode lines connected to the cathodes thereof.
  • one external input terminal 707 is provided.
  • Fig. 5A one external input terminal 707 is provided.
  • the external input terminal 707 is divided into two so that two parts are provided in different places (near one end of a longer side of the substrate and near the other end of the longer side of the substrate) and a set of anode lines and cathode lines connects one part with the pixel portion while the other set of anode lines and cathode lines connects the other part with the pixel portion.
  • the power supply lines on the far side of the input port of the anode lines and the cathode lines have an wiring resistance increased in accordance with a length R1. With the wiring resistance increased, the electric potential declines and hence the voltage applied to the EL elements by the power supply lines is lowered, thereby inviting reduction in image quality.
  • Fig. 5B there are an input port 1 of the anode lines and the cathode lines and an input port 2 that is provided apart from the input port 1.
  • the power supply lines are thus receive current both from the input port 1 and from the input port 2. This prevents voltage reduction due to increase in wiring resistance, whereby degradation of image quality can be controlled.
  • the distance between two external input terminal parts is set to equal to or more than half the length of the longer side of the substrate on which the pixel portion is formed. This enhances the effect of controlling the degradation of image quality caused by voltage reduction due to the increase in wiring resistance.
  • the external input terminal may be provided in one place without dividing it if an increase in wiring resistance is ignorable, or does not matter.
  • This embodiment can be carried out in combination with Embodiment Mode or Embodiment 1.
  • Described in this embodiment is a liquid crystal display device adopting the method of forming wiring lines in a sealed region.
  • the liquid crystal display device is driven by the active matrix method, for example.
  • each pixel has TFTs.
  • Each pixel has a pixel TFT 1002 whose gate electrode is connected to one of gate signal lines (G1 to Gy) for receiving a selection signal from a gate signal line driving circuit.
  • the pixel TFT 1002 in each pixel has a source region and a drain region one of which is connected to one of source signal lines (S1 to Sx) for receiving a signal from a source signal line driving circuit and the other of which is connected to one of electrodes of a capacitor storage 1001 and to one of two electrodes sandwiching a liquid crystal 1003.
  • the signal When a signal is inputted to the gate signal line G1, the signal is inputted to the gate electrode of every pixel TFT 1002 that is connected to the gate signal line G1 to turn these pixel TFTs ON. If a signal is inputted from the source signal lines (S1 to Sx) to a pixel whose pixel TFT 1002 is turned ON, an electric charge is held in the capacitor storage 1001. With the electric charge held in the capacitor storage, a voltage is applied to the electrodes sandwiching the liquid crystal 1003. The applied voltage is used to control the orientation of liquid crystal molecules, thereby controlling the amount of transmitting light. This operation is repeated for all of the gate signal lines (G1 to Gy) to display an image.
  • the liquid crystal display device displays an image by controlling the orientation of liquid crystal through application of voltage to the two electrodes sandwiching the liquid crystal.
  • the liquid crystal has to be sealed in a space between two insulating substrates which respectively have electrodes and which are adhered to each other by a sealing member in a manner that makes their electrodes face each other.
  • Figs. 6A and 6B show in schematic diagrams the two substrates of the liquid crystal display device with the liquid crystal sealed therebetween.
  • Fig. 6A is a top view of the liquid crystal display device.
  • An epoxy resin is used for a sealing member 301.
  • An orientation film (not shown) is formed on a substrate 31 and subjected to rubbing treatment.
  • the sealing member 301 is formed surrounding a pixel portion 302, a gate signal line driving circuit 303, and a source signal line driving circuit 304.
  • an opening (not shown) is formed in a part of the sealing member 301 as an inlet for injecting the liquid crystal later.
  • a spacer (not shown) is sprayed and the substrate 31 is bonded to another substrate 32.
  • the diameter of the spacer determines the distance between the substrate 31 and the substrate 32. After the distance is fixed, the substrate 31 is adhered to the substrate 32 by curing the sealing member 301 with irradiation of ultraviolet rays through the substrate 31 or the substrate 32, or heating.
  • the sealing member 301 When the sealing member 301 is cured by heating in order to bond the substrate 31 to the substrate 32, the heat treatment has to be performed while pressurizing. This method causes the substrate 31 and the substrate 32 to thermally expand and the displacement in bonding the substrates is a serious problem. Thermal curing also takes a longer time. Therefore, the sealing member is often cured by irradiation of ultraviolet rays rather than thermally cured.
  • a liquid crystal 33 is injected from the liquid crystal inlet, which is closed by an end-sealing material (not shown) so that the liquid crystal 33 does not leak to the exterior thereof.
  • the end-sealing material is a UV-curable material, not a thermally curable material. This is because the liquid crystal 33 is degraded if the device is heated after the liquid crystal 33 is injected.
  • the sealing member 301 and the end-sealing material also serve to block the passage of substances that contaminate the liquid crystal, such as moisture containing ions.
  • wiring lines for transmitting signals to be inputted respectively to the source signal line driving circuit and the gate signal line driving circuit are Described next.
  • Video signals or other signals from the external are inputted to the gate signal line driving circuit 303 and the source signal line driving circuit 304 to constitute signals that are to be inputted to the pixel portion 302.
  • the signals to be inputted to the gate signal line driving circuit 303 and the source signal line driving circuit 304 from the external are inputted by an FPC substrate 310 bonded to an external input terminal 309 that is placed on the pixel substrate 31.
  • the FPC substrate 310 is connected at the external input terminal 309 through an anisotropic conductive film (not shown) to wiring lines 312 that are formed on the pixel substrate.
  • the wiring lines 312 (312a, 312b, and 312c) run in the sealing member 301 to be connected to the gate signal line driving circuit 303 and the source signal line driving circuit 304.
  • the wiring lines 312a are wiring lines that receive signals from the FPC substrate 310 through the external input terminal 309 to transmit the signals to the gate signal line driving circuit 303.
  • the wiring lines 312b are wiring lines that receive signals from the FPC substrate 310 through the external input terminal 309 to transmit the signals to the source signal line driving circuit 304.
  • the wiring lines 312a and 312b are formed in a part of the pixel substrate 31 which is covered by the sealing member 301 (the sealed region).
  • Fig. 6B is a sectional view taken along the line B-B' in Fig. 6A .
  • the same components are denoted by the same reference symbols in Figs. 6A and 6B .
  • components shown in Fig. 6B are limited to a TFT 114 constituting the gate signal line driving circuit 303, and a pixel TFT 314 constituting the pixel portion 302.
  • the substrate 31 on which the TFTs constituting the pixel portion and the driving circuits are formed is referred to as pixel substrate.
  • An electrode 307 set on the pixel substrate is referred to as pixel electrode.
  • the other substrate, 32, is called an opposite substrate.
  • An electrode 308 set on the opposite substrate side is called an opposite electrode. The voltage applied to the pixel electrode 307 and the opposite electrode 308 is controlled to display an image.
  • Fig. 6B Denoted by 306 in Fig. 6B is a gate insulating film of each of the TFT 114 and the pixel TFT 314.
  • Reference symbol 315 denotes an interlayer insulating film and 112 denotes a light-shielding layer.
  • the orientation film is not shown in Fig. 6B .
  • the pixel TFT 314 has a source region and a drain region one of which is connected to the pixel electrode 307 to control the voltage applied to the pixel electrode 307.
  • the interlayer insulating film 315 is formed of an inorganic material here.
  • the wiring lines 312 are formed from the same material that is used to form source wiring lines and drain wiring lines of the TFT 114 and of the pixel TFT 314.
  • the sealing member 301 Assuming that the sealing member 301 is formed from a UV-curable material, the sealing member 301 cannot be cured when the sealing member 301 is irradiated with ultraviolet rays from the opposite substrate 32 side because of the light-shielding layer 112. Thus the irradiation of ultraviolet rays has to be made from the pixel substrate 31 side through the wiring lines 312a to cure the sealing member 301. However, if a wide wiring line is used for the wiring lines 312a, portions of the sealing member 301 which are shaded by the wiring lines cannot receive a sufficient amount of ultraviolet irradiation. Then the possibility is that the sealing member 301 is not cured satisfactorily.
  • this embodiment does not use a single wide wiring line for the wiring lines 312a.
  • Employed instead are a plurality of wiring lines connected in parallel to one another as shown in Figs. 3A and 3B .
  • the width L of each of the plural wiring lines is 100 ⁇ m to 200 ⁇ m whereas the spacing S between adjacent lines in the plural wiring lines is 50 ⁇ m to 150 ⁇ m, and the ratio of the width L of each of the plural wiring lines to the spacing S between adjacent lines in the plural wiring lines, namely, L/S, is within 0.7 to 1.5. If wiring lines configured as above are used, the sealing member on these wiring lines is sufficiently exposed to ultraviolet rays through the wiring lines, so that the sealing member is cured satisfactorily.
  • the width L of each of the plural wiring lines is equal to or less than 150 ⁇ m whereas the spacing S between adjacent lines in the plural wiring lines is equal to or more than 100 ⁇ m, and L/S is 1.5 or less.
  • the sealing member on the wiring lines can be cured enough.
  • the wiring lines 312a do not block the ultraviolet rays irradiated, and hence a wide wiring line may be used as 312a.
  • the wiring lines can be formed in the sealed region. This reduces the area of the regions other than the pixel portion, thereby making it possible to reduce the display device in size.
  • FIG. 7A and 7B A description given in this embodiment with reference to Figs. 7A and 7B is about a display device having a structure different from the one described in Embodiment 3. Components in Figs. 7A and 7B that are identical with those in Figs. 6A and 6B are denoted by the same reference symbols.
  • Fig. 7A is a top view of a liquid crystal display device according to the present invention.
  • a pixel substrate 31 On a pixel substrate 31, a pixel portion 302, a gate signal line driving circuit 303, and a source signal line driving circuit 304 are formed.
  • a sealing member 301 is formed surrounding the pixel portion and the driving circuits, so that an opposite substrate 32 is bonded to the substrate 31 and a liquid crystal 33 is sealed therebetween.
  • An FPC substrate 310 is connected to the top face of the pixel substrate 31 by an external input terminal 309.
  • Wiring lines 312a are wiring lines that receive signals from the FPC substrate 310 through the external input terminal 309 to transmit the signals to the gate signal line driving circuit 303.
  • Wiring lines 312b are wiring lines that receive signals from the FPC substrate 310 through the external input terminal 309 to transmit the signals to the source signal line driving circuit 304.
  • the wiring lines 312a and 312b are formed in the sealed region.
  • Fig. 7B is a sectional view taken along the line B-B' in Fig. 7A .
  • the same components are denoted by the same reference symbols in Figs. 7A and 7B .
  • components shown in Fig. 7B are limited to a TFT 114 as an element constituting the gate signal line driving circuit 303, and a pixel TFT 314 as an element constituting the pixel portion 302.
  • the pixel TFT 314 has a source region and a drain region one of which is connected to a pixel electrode 307 to control the voltage applied to the pixel electrode 307.
  • the wiring lines 312 are formed from the same material that is used to form source wiring lines and drain wiring lines of the TFT 114 and of the pixel TFT 314.
  • An interlayer insulating film 315 is formed of an organic material here.
  • the interlayer insulating film 315 is formed of an organic material, and adhesion is poor between the organic material and the wiring lines 312 if they are formed directly on the organic material. Forming the wiring lines directly on the organic material also has a problem of degrading the wiring lines 312, for impurities are introduced from the organic material to the material used to form the wiring lines 312. For that reason, the wiring lines 312 have to be formed after removing the interlayer insulating film 315 formed of an organic material.
  • the step of removing the interlayer insulating film 315 from a part where the wiring lines 312a are to be formed can be carried out when the source wiring lines and the drain wiring lines of the TFT 114 and the pixel TFT 314 are formed and contact holes reaching source regions or drain regions of the TFTs 114 and 314 are formed.
  • the sealing member 301 Assuming that the sealing member 301 is formed from a UV-curable material, the sealing member 301 cannot be cured when the sealing member 301 is irradiated with ultraviolet rays from the opposite substrate 32 side because of the light-shielding layer 112. Thus the irradiation of ultraviolet rays has to be made from the pixel substrate 31 side through the wiring lines 312a to cure the sealing member 301. However, if a wide wiring line is used for the wiring lines 312a, portions of the sealing member 301 which are shaded by the wiring lines cannot receive a sufficient amount of ultraviolet irradiation. Then the possibility is that the sealing member 301 is not cured satisfactorily.
  • this embodiment does not use a single wide wiring line for the wiring lines 312a.
  • Employed instead are a plurality of wiring lines connected in parallel to one another as shown in Figs. 3A and 3B .
  • the width L of each of the plural wiring lines is 100 ⁇ m to 200 ⁇ m whereas the spacing S between adjacent lines in the plural wiring lines is 50 ⁇ m to 150 ⁇ m, and the ratio of the width L of each of the plural wiring lines to the spacing S between adjacent lines in the plural wiring lines, namely, L/S, is within 0.7 to 1.5. If wiring lines configured as above are used, the sealing member on these wiring lines is sufficiently exposed to ultraviolet rays through the wiring lines, so that the sealing member is cured satisfactorily.
  • the width L of each of the plural wiring lines is equal to or less than 150 ⁇ m whereas the spacing S between adjacent lines in the plural wiring lines is equal to or more than 100 ⁇ m, and L/S is 1.5 or less.
  • the sealing member on the wiring lines can be cured enough.
  • the wiring lines 312a do not block the ultraviolet rays irradiated, and hence a wide wiring line may be used as 312a.
  • the wiring lines can be formed in the sealed region. This reduces the area of the regions other than the pixel portion, thereby making it possible to reduce the display device in size.
  • the electronic equipments which incorporate the electronic display device manufactured by applying the present invention as the display medium, are explained below.
  • Such electronic equipments include a video camera, a digital camera, a head mounted display (goggle type display), a game machine, a car navigation system, a personal computer, a portable information terminal (a mobile computer, a portable telephone, an electronic book and the like) and the like. Examples of those are shown in Fig. 8 .
  • Fig. 8A shows a personal computer, which contains a main body 2001, a casing 2002, a display portion 2003, a keyboard 2004 and the like.
  • the display device of the present invention can be used in the display portion 2003 of the personal computer.
  • Fig. 8B shows a video camera, which contains a main body 2101, a display portion 2102, a sound input portion 2103, operation switches 2104, a battery 2105, an image receiving portion 2106 and the like.
  • the display device of the present invention can be used in the display portion 2102 of the video camera.
  • Fig. 8C shows a portion (right side) of a head mounted type display device, which contains a main body 2301, a signal cable 2302, a head fixing band 2303, a screen monitor 2304, an optical system 2305, a display portion 2306 and the like.
  • the display device of the present invention can be used in the display portion 2306 of the head mounted type display device,
  • Fig. 8D shows an image playback device equipped with a recording medium (specifically, a DVD playback device), which contains a main body 2401, a recording medium (such as a CD, an LD or a DVD) 2402, operation switches 2403, a display portion (a) 2404, a display portion (b) 2405 and the like.
  • the display portion (a) is mainly used for displaying image information.
  • the display portion (b) is mainly used for displaying character information.
  • the display device of the present invention can be used in the display portions (a) and (b) of the image playback device equipped with the recording medium. Note that the present invention can be applied to devices such as a CD playback device and a game machine as the image playback device equipped with the recording medium.
  • Fig. 8E shows a mobile computer, which contains a main body 2501, a camera portion 2502, an image receiving portion 2503, operation switches 2504, a display portion 2505 and the like.
  • the display device of the present invention can be used in the display portion 2505 of the mobile computer.
  • portions that do not display an image including the periphery of driving circuits where wiring lines are formed and a portion where the sealing member is formed, take up a large area to hinder the display devices from reducing their sizes.
  • the present invention is capable of forming wiring lines in the portion where the sealing member is formed instead of the periphery of the driving circuits.
  • the invention can provide a small-sized display device.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Optics & Photonics (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)
  • Liquid Crystal (AREA)

Claims (10)

  1. Anzeigevorrichtung, die umfasst:
    ein Substrat (701);
    eine Vielzahl von Pixeln (711), die auf dem Substrat (701) angeordnet sind;
    eine Treiberschaltung (702), die konfiguriert ist, ein Signal in die Vielzahl von Pixeln (711) einzugeben, und die auf dem Substrat (701) angeordnet ist;
    eine erste Verdrahtungsleitung (708), die konfiguriert ist, ein externes Signal in die Treiberschaltung (702) einzugeben, und die auf dem Substrat (701) angeordnet ist;
    ein Abdeckungselement (705) mit einer Lichtabschirmeigenschaft; und
    ein Dichtungselement (704), das auf dem Substrat angeordnet ist und das ein ultraviolett-härtendes Material umfasst, wobei das Dichtungselement (704) die Vielzahl von Pixeln (711) und die Treiberschaltung (702) umgibt, so dass die Vielzahl von Pixeln (711) und die Treiberschaltung (702), die auf dem Substrat (701) angeordnet sind, von dem Dichtungselement (704) und dem Abdeckungselement (705) hermetisch verschlossen sind, wobei das Abdeckungselement (705) auf dem Dichtungselement (704) angeordnet ist,
    wobei die Anzeigevorrichtung dadurch gekennzeichnet ist, dass:
    die erste Verdrahtungsleitung (708) auf dem Substrat (701) derart angeordnet ist, dass sie entlang zumindest einer Seite des Dichtungselements (704) zwischen dem Dichtungselement (704) und dem Substrat (701) läuft,
    wobei das Substrat (701) so konfiguriert ist, dass das Dichtungselement (704) mit Ultraviolettstrahlen durch das Substrat (701) bestrahlt werden kann,
    wobei die erste Verdrahtungsleitung (708) eine Vielzahl von weiteren Verdrahtungsleitungen (A1, ..., A6) umfasst, die zueinander parallel verbunden sind,
    wobei die Breite L jeder der weiteren Verdrahtungsleitungen (A1, ..., A6), die zueinander parallel verbunden sind, im Bereich von 100 µm bis 200 µm liegt, und
    wobei ein Zwischenraum S zwischen benachbarten Verdrahtungsleitungen der Vielzahl von weiteren Verdrahtungsleitungen (A1, ..., A6), die zueinander parallel verbunden sind, im Bereich von 50 µm bis 150 µm liegt.
  2. Anzeigevorrichtung nach Anspruch 1, wobei das Verhältnis von L zu S zwischen 0,7 und 1,5 liegt.
  3. Anzeigevorrichtung nach Anspruch 1, wobei das Dichtungselement (704) in Kontakt mit einer anorganischen Schicht (720) steht, die auf dem Substrat (701) angeordnet ist.
  4. Anzeigevorrichtung nach Anspruch 1, wobei die erste Verdrahtungsleitung (708) aus dem gleichen Material ausgebildet ist, das Sourceverdrahtungsleitungen und Drainverdrahtungsleitungen von Dünnschichttransistoren (712; 713) für die Vielzahl von Pixeln (711) und für die Treiberschaltung (702) ausbildet.
  5. Anzeigevorrichtung nach Anspruch 1, die ferner ein Flüssigkristallmaterial umfasst, wobei die Vielzahl von Pixeln (711), die Treiberschaltung (702) und das Flüssigkristallmaterial von dem Dichtungselement (704) und dem Abdeckungselement (705) hermetisch verschlossen sind.
  6. Videokamera, die eine Anzeigevorrichtung nach Anspruch 1 umfasst.
  7. Bildwiedergabegerät, das eine Anzeigevorrichtung nach Anspruch 1 umfasst.
  8. Head-Mounted-Display, das eine Anzeigevorrichtung nach Anspruch 1 umfasst.
  9. Mobiltelefon, das eine Anzeigevorrichtung nach Anspruch 1 umfasst.
  10. Tragbares Informationsendgerät, das eine Anzeigevorrichtung nach Anspruch 1 umfasst.
EP10182874.7A 2000-07-25 2001-07-25 Dichtungs- und Verdrahtungsanordnung für ein Anzeigesystem des Aktivmatrix-Typs Expired - Lifetime EP2275860B1 (de)

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EP01118047A EP1176457B1 (de) 2000-07-25 2001-07-25 Dichtungs- und Verdrahtungsanordnung für ein elektrolumineszentes Anzeigesystem des Aktivmatrix-Typs

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Families Citing this family (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4789369B2 (ja) * 2001-08-08 2011-10-12 株式会社半導体エネルギー研究所 表示装置及び電子機器
US7038377B2 (en) * 2002-01-16 2006-05-02 Seiko Epson Corporation Display device with a narrow frame
JP4720069B2 (ja) * 2002-04-18 2011-07-13 セイコーエプソン株式会社 電気光学装置及び電子機器
JP3778176B2 (ja) * 2002-05-28 2006-05-24 セイコーエプソン株式会社 発光装置および電子機器
JP3901127B2 (ja) * 2002-06-07 2007-04-04 セイコーエプソン株式会社 電気光学装置及び電子機器
CN100418221C (zh) * 2002-06-07 2008-09-10 精工爱普生株式会社 电光装置和电子仪器
SG142140A1 (en) 2003-06-27 2008-05-28 Semiconductor Energy Lab Display device and method of manufacturing thereof
CN1816836B (zh) * 2003-07-08 2011-09-07 株式会社半导体能源研究所 显示装置及其驱动方法
KR100544123B1 (ko) 2003-07-29 2006-01-23 삼성에스디아이 주식회사 평판표시장치
JP4741177B2 (ja) * 2003-08-29 2011-08-03 株式会社半導体エネルギー研究所 表示装置の作製方法
US7928654B2 (en) * 2003-08-29 2011-04-19 Semiconductor Energy Laboratory Co., Ltd. Display device and method for manufacturing the same
US7538488B2 (en) * 2004-02-14 2009-05-26 Samsung Mobile Display Co., Ltd. Flat panel display
KR100615212B1 (ko) * 2004-03-08 2006-08-25 삼성에스디아이 주식회사 평판 표시 장치
KR100581903B1 (ko) 2004-03-09 2006-05-22 삼성에스디아이 주식회사 전계 발광 디스플레이 장치
US7619258B2 (en) * 2004-03-16 2009-11-17 Semiconductor Energy Laboratory Co., Ltd. Display device
JP2005301161A (ja) * 2004-04-15 2005-10-27 Nec Corp 表示装置
KR100681022B1 (ko) * 2004-06-16 2007-02-09 엘지전자 주식회사 유기 전계발광표시소자 및 그 제조방법
CN1819300B (zh) * 2004-09-17 2010-06-16 株式会社半导体能源研究所 发光器件
KR20060104093A (ko) * 2005-03-29 2006-10-09 삼성전자주식회사 액정 표시 장치 및 그 제조 방법
KR101149936B1 (ko) * 2005-04-26 2012-05-30 엘지디스플레이 주식회사 유기전계발광패널
US7710739B2 (en) 2005-04-28 2010-05-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and display device
KR100671638B1 (ko) 2006-01-26 2007-01-19 삼성에스디아이 주식회사 유기 전계 발광 표시장치
KR101366980B1 (ko) * 2007-06-01 2014-02-24 엘지디스플레이 주식회사 유기전계발광소자
KR20080114263A (ko) * 2007-06-27 2008-12-31 엘지디스플레이 주식회사 유기전계발광소자
KR100839430B1 (ko) * 2007-09-14 2008-06-19 삼성에스디아이 주식회사 유기 발광 표시 장치 및 그 제조방법
JP2009175198A (ja) 2008-01-21 2009-08-06 Sony Corp Ｅｌ表示パネル及び電子機器
US8325311B2 (en) * 2008-07-07 2012-12-04 Lg Display Co., Ltd. Liquid crystal display device and method of fabricating the same
KR100995071B1 (ko) 2008-09-12 2010-11-18 삼성모바일디스플레이주식회사 유기 발광 표시 장치
CN101907795B (zh) * 2009-06-02 2013-08-07 群创光电股份有限公司 图像显示系统及其制造方法
JP5409315B2 (ja) * 2009-12-11 2014-02-05 キヤノン株式会社 表示装置
CN101789493B (zh) * 2009-12-25 2012-11-07 昆山维信诺显示技术有限公司 一种有机电致发光器件
KR101174882B1 (ko) 2010-06-15 2012-08-17 주식회사 엔씰텍 평판 표시 장치, 평판 표시 장치용 원장 기판, 평판 표시 장치 제조 방법 및 평판 표시 장치용 원장 기판 제조 방법
KR20120032250A (ko) * 2010-09-28 2012-04-05 삼성모바일디스플레이주식회사 평판 표시 장치 및 그 제조 방법
KR101810052B1 (ko) * 2010-10-27 2017-12-19 삼성디스플레이 주식회사 평판 표시 장치 및 평판 표시 장치 제조 방법
KR20120044021A (ko) * 2010-10-27 2012-05-07 삼성모바일디스플레이주식회사 평판 표시 장치 및 평판 표시 장치 제조 방법
ES2575544T3 (es) 2010-12-24 2016-06-29 Medichem, S.A. Procedimientos para la preparación de 5-cloro-2-metil-2,3,3a,12b-tetrahidro-1H-dibenzo[2,3:6,7]oxepino[4,5-c]pirrol
KR101957998B1 (ko) 2012-06-20 2019-07-03 삼성디스플레이 주식회사 표시 패널 및 이의 제조 방법
JP2014059246A (ja) * 2012-09-19 2014-04-03 Toshiba Corp 放射線検出器およびその製造方法
KR101896377B1 (ko) * 2012-10-12 2018-09-07 엘지디스플레이 주식회사 베젤이 최소화된 액정표시소자
KR102160829B1 (ko) * 2012-11-02 2020-09-28 가부시키가이샤 한도오따이 에네루기 켄큐쇼 밀봉체 및 밀봉체의 제작 방법
KR101993331B1 (ko) * 2013-01-03 2019-06-27 삼성디스플레이 주식회사 유기발광표시장치 및 그 제조방법
KR20180133942A (ko) 2013-03-07 2018-12-17 가부시키가이샤 한도오따이 에네루기 켄큐쇼 표시 장치 및 전자 기기
CN103217845B (zh) * 2013-04-22 2015-07-15 京东方科技集团股份有限公司 下基板及其制造方法、液晶显示面板和液晶显示器
KR102079253B1 (ko) * 2013-06-26 2020-02-20 삼성디스플레이 주식회사 박막트랜지스터 기판, 이를 구비하는 유기 발광 장치, 박막트랜지스터 기판 제조방법 및 유기 발광 장치 제조방법
KR102118676B1 (ko) 2014-02-05 2020-06-04 삼성디스플레이 주식회사 유기발광 디스플레이 장치
CN103777385A (zh) * 2014-02-12 2014-05-07 苏州众显电子科技有限公司 一种fpc与lcd基板连接结构
WO2015174013A1 (ja) * 2014-05-12 2015-11-19 パナソニックＩｐマネジメント株式会社 有機ｅｌ素子及び照明装置
CN104297957B (zh) * 2014-10-16 2017-02-15 昆山龙腾光电有限公司 Tft阵列基板、显示面板及显示装置
CN104465704B (zh) * 2014-12-03 2019-08-23 京东方科技集团股份有限公司 显示面板及其封装方法、显示装置
KR102399574B1 (ko) 2015-04-03 2022-05-19 삼성디스플레이 주식회사 유기 발광 표시 장치
CN104900677A (zh) * 2015-05-14 2015-09-09 信利半导体有限公司 有机电致发光器件、显示装置及照明装置
KR102439308B1 (ko) * 2015-10-06 2022-09-02 삼성디스플레이 주식회사 표시장치
CN207303104U (zh) * 2017-10-31 2018-05-01 昆山国显光电有限公司 显示面板
CN116669498A (zh) * 2018-04-20 2023-08-29 堺显示器制品株式会社 有机el装置及其制造方法
CN109243305B (zh) * 2018-09-17 2021-10-12 京东方科技集团股份有限公司 显示面板、显示装置和显示面板的制造方法
KR20200077250A (ko) * 2018-12-20 2020-06-30 엘지디스플레이 주식회사 표시 장치 및 그 제조 장치
CN109856865A (zh) * 2019-04-03 2019-06-07 深圳市华星光电半导体显示技术有限公司 阵列基板及显示面板
CN116664566B (zh) * 2023-07-28 2023-09-26 成都数智创新精益科技有限公司 一种oled面板丝印质量控制方法及系统及装置及介质

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2002A (en) * 1841-03-12 Tor and planter for plowing
US2001A (en) * 1841-03-12 Sawmill
US5076667A (en) * 1990-01-29 1991-12-31 David Sarnoff Research Center, Inc. High speed signal and power supply bussing for liquid crystal displays
US5148301A (en) * 1990-02-27 1992-09-15 Casio Computer Co., Ltd. Liquid crystal display device having a driving circuit inside the seal boundary
JP2901028B2 (ja) * 1991-12-03 1999-06-02 シャープ株式会社 誘電性表示素子およびその製造方法
JPH05249478A (ja) * 1991-12-25 1993-09-28 Toshiba Corp 液晶表示装置
JP2893433B2 (ja) * 1992-11-10 1999-05-24 カシオ計算機株式会社 液晶表示装置
US5684555A (en) * 1994-12-19 1997-11-04 Kabushiki Kaisha Toshiba Liquid crystal display panel
US6011607A (en) 1995-02-15 2000-01-04 Semiconductor Energy Laboratory Co., Active matrix display with sealing material
JP3299869B2 (ja) * 1995-09-27 2002-07-08 シャープ株式会社 液晶表示装置とその製造方法
JPH0990419A (ja) * 1995-09-27 1997-04-04 Toshiba Corp 液晶表示装置
JP3336900B2 (ja) * 1997-03-12 2002-10-21 セイコーエプソン株式会社 液晶表示パネルおよびそれを用いた投写型表示装置
KR100516533B1 (ko) * 1997-03-26 2005-12-16 세이코 엡슨 가부시키가이샤 액정장치,전기광학장치및그것을사용한투사형표시장치
JP3856901B2 (ja) * 1997-04-15 2006-12-13 株式会社半導体エネルギー研究所 表示装置
JPH1124588A (ja) 1997-06-30 1999-01-29 Kyocera Corp 表示装置
JP3541625B2 (ja) * 1997-07-02 2004-07-14 セイコーエプソン株式会社 表示装置及びアクティブマトリクス基板
JPH1152394A (ja) 1997-07-29 1999-02-26 Nec Kagoshima Ltd 液晶表示装置及びその製造方法
JP3907804B2 (ja) * 1997-10-06 2007-04-18 株式会社半導体エネルギー研究所 液晶表示装置
EP0950917B1 (de) 1997-10-31 2003-12-03 Seiko Epson Corporation Elektrooptische vorrichtung und elektronisches gerät
JPH11279558A (ja) * 1998-01-27 1999-10-12 Hitachi Maxell Ltd ポリマー分散型液晶組成物及び該組成物を有する液晶表示素子
JPH11271803A (ja) * 1998-03-18 1999-10-08 Seiko Epson Corp 液晶装置およびその製造方法並びに電子機器
JPH11271804A (ja) * 1998-03-20 1999-10-08 Toshiba Corp 液晶表示装置
US6111357A (en) * 1998-07-09 2000-08-29 Eastman Kodak Company Organic electroluminescent display panel having a cover with radiation-cured perimeter seal
JP2000173766A (ja) * 1998-09-30 2000-06-23 Sanyo Electric Co Ltd 表示装置
KR101634970B1 (ko) * 2007-05-18 2016-06-30 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 반도체 장치 제조 방법
JP5446982B2 (ja) * 2009-05-01 2014-03-19 株式会社リコー 画像表示パネル及び画像表示装置

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TW519606B (en) 2003-02-01
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