EP2269193A1 - Transistor antifusible programmable et procédé pour sa programmation - Google Patents

Transistor antifusible programmable et procédé pour sa programmation

Info

Publication number
EP2269193A1
EP2269193A1 EP09733487A EP09733487A EP2269193A1 EP 2269193 A1 EP2269193 A1 EP 2269193A1 EP 09733487 A EP09733487 A EP 09733487A EP 09733487 A EP09733487 A EP 09733487A EP 2269193 A1 EP2269193 A1 EP 2269193A1
Authority
EP
European Patent Office
Prior art keywords
source
drain
voltage
terminal
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP09733487A
Other languages
German (de)
English (en)
Inventor
Martin Groepl
Holger Hoeltke
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Silicon Line GmbH
Original Assignee
Silicon Line GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silicon Line GmbH filed Critical Silicon Line GmbH
Publication of EP2269193A1 publication Critical patent/EP2269193A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a programmable antifuse transistor, in particular an n-channel MOS transistor, according to the preamble of claim 1.
  • the present invention further relates to an antifuse circuit arrangement, in particular a one-time electrically programmable non-volatile memory cell according to the preamble of claim 7.
  • an antifuse circuit arrangement can, in particular as surface-efficient, designed for non-volatile or nonvolatile storage of bits, once electrically be formed programmable permanent memory cell.
  • the present invention further relates to a method for programming at least one such antifuse transistor according to the preamble of claim 10.
  • metal oxide transistors Metal Oxide Semiconductor (Field Effect Transistors) or MOS (FETs)
  • FETs Field Effect Transistors
  • a metal-oxide transistor can serve as an electrically programmable fuse which does not interrupt an electrically conductive connection during programming, but produces it (so-called anti-fuse technology).
  • an n-channel MOS transistor has four terminals, namely, gate, source (n-doped), substrate (p-doped), and drain (n-doped). Accordingly, it should be noted that a parasitic npn
  • Bipolar transistor from the regions (or regions) source (emitter) - substrate (base) - drain (collector) is formed.
  • the substrate ie base voltage
  • the source ie emitter voltage during programming
  • charge carriers enter the substrate region (base) via the pn junction between substrate and source; by applying a positive voltage to the drain at the drain, a current flows, which is caused by the introduced charge carriers in the substrate region.
  • the substrate potential is raised so far relative to the source potential that a pn diode (with a forward voltage of approximately 0.6 volt) located between the substrate and the source rises due to polarity in the forward direction - lent current flow
  • EP 1 777 708 A1 discloses a non-transient 3,5-transistor Speyer cell with gate oxide breakthrough
  • the object of the present invention is to further develop an antifuse transistor of the type mentioned above, an antifuse circuit arrangement of the type mentioned at the outset and a method of the type mentioned above that active circuit (ste ⁇ l) e (n) must not be located at a significant distance to the antifuse, in this way, the space requirement should be minimized, without requiring additional process steps in this case by an antifuse transistor with the specified in claim 1
  • n-channel MOS transistor is basically preferred, because in comparison with a p-channel MOS transistor, it has a higher conductivity (the charge carrier mobility of an n-channel MOS transistor).
  • Channel MOS transistor is higher than the charge carrier mobility of a p channel MOS transistor
  • the magnitude of the potential difference between the source terminal and the substrate terminal is at most about 0.5 volts, more preferably at most about 0.3 volts.
  • the amount of the potential difference between the source terminal and the substrate terminal is particularly preferably chosen to be smaller than the forward voltage of silicon pn junctions or of silicon pn diodes in order to avoid a latch-up of adjacent circuits.
  • the source terminal and the substrate terminal during programming at substantially the same potential, in particular collectively on a reference or reference potential, for example, at ground potential, zero potential or ground potential (ground or GND), recorded; for example by metallic connection (so-called short circuit).
  • a reference or reference potential for example, at ground potential, zero potential or ground potential (ground or GND), recorded; for example by metallic connection (so-called short circuit).
  • the amount of potential difference between the drain of the antifuse transistor and the source of the antifuse transistor during programming is greater, for
  • the largest possible drain-source voltage amount is achieved with a minimum amount of electric field strength between gate and conductive
  • the drain terminal is brought to a much higher potential than the reference or reference potential during programming, for example to approximately +4 volts.
  • a positive gate-source voltage which during programming is about half the size or slightly more than about half the size of the drain-source voltage, in the order of magnitude between about 0.4 times and about 0, 7 times the amount of the drain-source voltage is (for example, about +2 volts)
  • this current flow With a suitable choice of drain-source and gate-source voltage, becomes so great that local thermal heating of the semiconductor material between source and drain occurs. If this local thermal heating is so great that the semiconductor material melts between the source and the drain, this melting process produces a permanent conducting channel between the source and drain which is approximately 10,000 times greater in conductivity than in the unprogrammed state.
  • the antifuse transistor according to the present invention, the antifuse circuit arrangement according to the present invention and the method according to the present invention are characterized in particular by a high integration density with other active circuit parts, since there is no need for increased safety distance between antifuse and active circuit.
  • the substrate potential is conventionally raised, for example in the prior art method according to US Pat. No. 7,272,067 B1, according to the invention the substrate remains at a fixed reference or reference potential, for example at ground potential (ground or GND).
  • the substrate potential is not (or only slightly) raised, so that active circuit (steep) e (n) is not in clear distance from the antifuse. Rather, the transistor according to the invention is overloaded as it were defined for a short time; For example, a 1.2 volt transistor can be operated for a short time with a maximum voltage of about 2 volts between the gate and the source-drain channel.
  • both the drain-gate voltage may be about +2 volts and the gate-source voltage may be about +2 volts, resulting in a drain-source voltage of about +4 volts.
  • the present invention relates to the use of at least one antifuse transistor, in particular of at least one n-channel MOS transistor, according to the type set out above and / or a method according to the kind set forth above in at least one antifuse circuit arrangement, in particular at least one area-efficient, one-time electrically programmable non-volatile memory cell according to the above-described kind for non-volatile or nonvolatile storage of bits, for example in at least one C [complementary] M [etal] 0 [xide] S [emiconductor] -l [ ntegrated] C [ircuit] -Analogscrien.
  • FIG. 1 is a schematic cross-sectional view of an embodiment of an antifuse transistor programmable according to the method of the present invention according to the present invention
  • Fig. 2A is a schematic representation of a pre-stage of a first embodiment of an anti-fuse circuit according to the present invention having the antifuse transistor of Fig. 1;
  • Fig. 2B is a schematic representation of the first embodiment of the anti-fuse circuit of Fig. 2A in the form of an area-efficient permanent memory cell once electrically programmable according to the method of the present invention, having the antifuse transistor of Fig. 1;
  • FIG. 2C shows a schematic illustration of a second exemplary embodiment of an antifuse circuit arrangement in the form of an area-efficient permanent memory cell which is once electrically programmable according to the method according to the present invention and has the antifuse transistor from FIG. 1. Similar or similar embodiments, elements or features are identical in FIG. 1 to FIG. 2C
  • FIG. 1 there is shown a schematic cross-sectional view of an embodiment of a programmable antifuse n-channel MOS transistor 100 in accordance with the present invention, operating in accordance with the method of the present invention and having its conductivity in the programmed state greater by a factor of 10,000 as in the unprogrammed state.
  • drain D with connection ( drain contact or drain terminal) 16 and
  • the magnitude of the potential difference between the source terminal 14 and the substrate terminal 18 is selected smaller than the forward voltage of silicon-pn junctions 22 located in the immediate vicinity, for example, at a distance of approximately one micron.
  • the amount of the potential difference between the source terminal 14 and substrate terminal 18 is at most about 0.5 volts, more preferably at most about 0.3 volts;
  • the drain terminal 16 and the source terminal 14 are at different potential during programming, in particular during the reflow, wherein the amount of this potential difference between the drain terminal 16 and source 14 by more than twice the maximum allowable nominal (continuous) operating voltage n-channel MOS transistor 100; In the exemplary embodiment of FIG. 1, the drain terminal 16 is at a higher potential than the reference or reference potential GND.
  • Hatched in FIG. 1 is the one, among other things, limited by the silicon pn junctions 22 region 20 of the p-substrate 10, which is modified by the programming, that is, by the melting insofar as this area is now n-diffused ,
  • a voltage source 24 for providing the suitable for the firing or melting voltage V B (exemplary order of magnitude: about 4.2 volts to about five volts) is disposed between the drain terminal 16 and the source terminal 14 (see Fig. 1). Also between the drain terminal 16 and the source 14, in series with the Brenn- or
  • Melting voltage source 24 is a current-limiting element in the form of a current source 26 for the fuel or melt stream I 8 available.
  • an element 28 defining the voltage at the gate G is arranged between the gate terminal 12 and the source terminal 14 (see FIG.
  • FIG. 2A pre-stage
  • FIG. 2B in which a first exemplary embodiment of an anti-fuse circuit 200 having antifuse transistor 100 according to FIG. 1 is shown schematically
  • element 28 defining the voltage at gate G is shown , which is exemplified in Fig. 1 in a simplified representation as Sparv ⁇ ungsttle 28 for a defined bias to the gate G, configured in the first embodiment for the antifuse circuit 200 in the form of a voltage divider arrangement 28a, 28b.
  • the current-limiting element 26 is associated with the drain terminal 16 and the side facing away from the gate G side of the first resistor 28a of the voltage divider.
  • Both resistors 28a, 28b of the voltage divider arrangement are designed with high resistance, for example of the order of a few hundred kilohms.
  • FIG. 2C which schematically illustrates a second exemplary embodiment of antifuse circuit 200 'having antifuse transistor 100 according to FIG. 1, element 28 defining the voltage at gate G is shown in FIG simplified representation is exemplified as a voltage source 28 for a defined bias to the gate G, configured in the second embodiment for the antifuse circuitry 200 'in the form of a voltage regulator element 28'.
  • the drain connection 16 is brought to a significantly higher potential, for example, during programming than at the reference or reference potential GND to about +4 volts (see Fig. 2A).
  • the order of magnitude in the range of between about 0.4 times and about 0.7 times the amount of the drain-source voltage during programming, that is about half or a little more than about half is as large as the drain-source voltage and thus in the embodiments according to FIGS. 2A to 2C, for example, about +2 volts, there is the formation of a conductive charge carrier channel between the source S and drain D and thus to the flow of charge carriers between source S and drain D.
  • the semiconductor material 20 is thermally heated between source S and drain D and locally melts to form a permanently conductive channel between source S and drain D.
  • Such anti-fuse circuitry 200, 200 ' may be the basis for a more complex memory system, such as may be used in a memory device for nonvolatile or nonvolatile storage of bits;
  • a memory device may comprise an array of area-efficient, once electrically programmable, non-volatile memory cells based on the antifuses 100; the anti-fuse circuitry (s) 200, 200 'is then integrated in this array.
  • control unit 300 (so-called programming controller, see Fig. 2B and Fig. 2C) is the
  • t first switching position of the switch 30
  • the switch 30 is closed, not only a conductive connection between the fuel or melt current source 26 and the side facing away from the gate G side of the first resistor 28 a of the voltage divider is created, but parallel to the antifuse transistor 100 (already discussed above with reference to FIG 2A ) positive gate-source voltage is provided, so that the transistor 100 is placed in a conductive state
  • This gate-to-source voltage is about half the size (or slightly more than about half) of the drain-source voltage during programming, that is, in the range between about 0.4 times and about 0.7 times the Amount of the Dram source voltage and thus amounts to in the exemplary embodiments according to FIGS. 2A to 2C, for example, approximately +2 volts
  • the proviso is that a maximum drain-source voltage amount arises with a minimum amount of voltage between the gate G and the conducting channel, that is, with a minimal amount of electric field strength between the gate G and the conducting channel
  • the burning or melting current I 8 provided by the combustion or melt current source 26, for example of the order of approximately five milliamperes, can flow through this charge carrier flow I B the semicon- ductor 20 between source S and drain D is thermally heated and melts locally under durably conductive channeling between source S and drain D.
  • this current-limiting element 34 is designed as an ohmic resistor.
  • this current-limiting element 34 ' is designed as a current source
  • a decision element 36 is provided, which is not necessarily as an inverter (see
  • the antifuse transistor 100 is programmed, that is called “burned” or “damaged” or “destroyed”, then the antifuse transistor 100 is in a conductive, ie low-impedance state.
  • the voltage divider ratio RD S / (R S E + RD S) follows on to the drain terminal 16 to equipotential then thus lying center of the input terminal of the inverter 36 is a voltage well below V 8/2 well below half the supply voltage such a voltage significantly below V s / 2 represents the input of the inverter 36, a logical "0", which is at the output out of the inverter 36, through which the output terminal of the elekt ⁇ sch programmable non-volatile memory cell is given at the same time, a logical "1" is output
  • non-programmed that is “non-burned” (or “unfired”) or “undamaged” (or “undamaged”) or “non-destructed” (or “undelivered”) transistor 100, which may still be prior to programming in accordance with the present invention, for example Compared to the current-limiting element 34 significantly less conductive, that is much higher impedance, resulting in the input of the inverter 36, due to the voltage divider ratio RDS / (R S E + RDS).
  • a voltage above V 5/2 that is significantly above half the supply voltage results, for example, approximately the supply voltage V 3
  • V 3 Such a voltage of well above Vs / 2 represents the input of the inverter 36, a logic "1 ', which at the output out of the inverter 36, through which the output terminal of the electrically programmable permanent memory cell is simultaneously given, a logic "0" is output
  • the antifuse circuit 200 ' according to FIG. 2C
  • FIGS. 1 to 2C have the advantage over the prior art that the active circuit point does not have to be at a considerable distance from the antifuse.
  • active circuit points can be at a minimum distance to the antifuse transistor 100 are placed
  • the antifuse transistor 100 according to the present invention see FIG. 1
  • the antifuse circuitry 200 see FIG. 2B
  • 200 ' see FIG. 2C
  • the substrate potential is not (or only marginally) raised. Rather, the transistor 100 will, so to speak overloaded for a short time, for example, a 1.2 volt
  • Transistor 100 is briefly operated at a maximum gate voltage of about 2 volts.
  • control unit in particular programming controller 10 substrate (corresponding to base), in particular p-type substrate 12 connection of the gate G, in particular gate contact or gate terminal 14 connection of the source S, in particular source contact or source terminal 16 connection of the drain D, in particular drain contact or Drainterminal
  • connection of the substrate 10, in particular substrate contact or substrate terminal 20 semiconductor material, in particular fusible or molten semiconductor material 22 pn junction, in particular silicon pn junction
  • voltage source in particular fuel or melt voltage source, for providing the fuel or melt voltage V B.
  • current-limiting element in particular current source, for example, for fuel or fuse current I B 28 voltage at the gate G defining element, in particular voltage source for providing a
  • GND reference potential or reference potential in particular ground potential or ground potential or zero potential

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un transistor antifusible programmable et un procédé pour programmer ce transistor. Pour perfectionner un transistor antifusible programmable (100), en particulier un transistor MOS à canal n, ainsi qu'un procédé pour programmer au moins un tel transistor antifusible (100) présentant - au moins une grille (G) avec une borne de grille (12), - au moins une source (S) avec une borne de source (14), - au moins un drain (D) avec une borne de drain (16) et - au moins un substrat (10) avec une borne de substrat (18) de telle manière que des parties de circuit actives ne doivent pas se trouver à nette distance de l'antifusible pour réduire de cette façon le besoin de place sans que des étapes supplémentaires soient de ce fait nécessaire, l'invention propose que la grandeur de la différence de potentiel entre la borne de source (14) et la borne de substrat (18) soit au maximum d'environ 0,5 volt, en particulier au maximum d'environ 0,3 volt, - que la borne de drain (16) et la borne de source (14) se trouvent à un potentiel différent et - qu'en ajustant la tension drain-source et/ou la tension grille-source, un flux porteur de charge survienne grâce auquel le matériau semi-conducteur (20) entre source (S) et drain (D) est thermiquement chauffé et fond localement en formant au moins un canal continuellement conducteur entre source (S) et drain (D).
EP09733487A 2008-04-16 2009-04-16 Transistor antifusible programmable et procédé pour sa programmation Withdrawn EP2269193A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE102008001217 2008-04-16
DE102009001923 2009-03-26
PCT/EP2009/054483 WO2009127670A1 (fr) 2008-04-16 2009-04-16 Transistor antifusible programmable et procédé pour sa programmation

Publications (1)

Publication Number Publication Date
EP2269193A1 true EP2269193A1 (fr) 2011-01-05

Family

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EP09733487A Withdrawn EP2269193A1 (fr) 2008-04-16 2009-04-16 Transistor antifusible programmable et procédé pour sa programmation

Country Status (4)

Country Link
US (1) US8194431B2 (fr)
EP (1) EP2269193A1 (fr)
JP (1) JP5591792B2 (fr)
WO (1) WO2009127670A1 (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2172082B1 (fr) * 2007-06-19 2020-10-14 Silicon Line GmbH Circuiterie et procédé pour commander des composants électroluminescents
JP6076580B2 (ja) * 2007-06-19 2017-02-08 シリコン・ライン・ゲー・エム・ベー・ハー 発光部品を制御する回路装置
WO2009141449A2 (fr) * 2008-05-21 2009-11-26 Silicon Line Gmbh Circuiterie et procédé d'excitation de composants électroluminescents
EP2359502B1 (fr) 2008-10-09 2017-04-05 Silicon Line GmbH Circuit et procédé de transmission de signaux codés tmds
US8526244B2 (en) * 2011-07-21 2013-09-03 Elite Semiconductor Memory Technology Inc. Anti-fuse circuit
US8724364B2 (en) * 2011-09-14 2014-05-13 Semiconductor Components Industries, Llc Electronic device including a nonvolatile memory structure having an antifuse component and a process of using the same
WO2015122870A1 (fr) * 2014-02-11 2015-08-20 Intel Corporation Antifusible à bornes remplies
EP3183751A4 (fr) 2014-08-19 2018-03-28 Intel Corporation Anti-fusible mos à claquage accéléré par vide
US10212827B2 (en) * 2016-07-01 2019-02-19 Intel Corporation Apparatus for interconnecting circuitry
US11687766B2 (en) * 2018-06-19 2023-06-27 Qualcomm Incorporated Artificial neural networks with precision weight for artificial intelligence
JP7195921B2 (ja) * 2018-12-28 2022-12-26 キヤノン株式会社 記録素子基板、液体吐出ヘッド及び記録装置
US10825536B1 (en) * 2019-08-30 2020-11-03 Qualcomm Incorporated Programmable circuits for performing machine learning operations on edge devices

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5019878A (en) * 1989-03-31 1991-05-28 Texas Instruments Incorporated Programmable interconnect or cell using silicided MOS transistors
US5012384A (en) * 1990-02-20 1991-04-30 Advanced Micro Device, Inc. Load circuit for a differential driver
US5019769A (en) * 1990-09-14 1991-05-28 Finisar Corporation Semiconductor laser diode controller and laser diode biasing control method
JP2885933B2 (ja) * 1990-11-26 1999-04-26 シチズン時計株式会社 半導体不揮発性メモリとその書き込み方法
US5672994A (en) * 1995-12-21 1997-09-30 International Business Machines Corporation Antifuse circuit using standard MOSFET devices
JP3725235B2 (ja) 1996-03-29 2005-12-07 富士通株式会社 発光素子駆動回路及びこれを有する発光装置
US5834813A (en) * 1996-05-23 1998-11-10 Micron Technology, Inc. Field-effect transistor for one-time programmable nonvolatile memory element
GB2365788A (en) 2000-08-10 2002-02-27 Mark Technology Corp Q A signal transmitting/flashing adapter for a hand-held electronic game
JP2002246472A (ja) * 2001-02-19 2002-08-30 Kawasaki Microelectronics Kk 半導体装置
EP1233453A3 (fr) * 2001-02-19 2005-03-23 Kawasaki Microelectronics, Inc. Circuit intégré semi-conducteur comprenant un anti-fusible, procédé de fabrication, et procédé d'écriture de données dans le même
US6667661B1 (en) * 2001-05-04 2003-12-23 Euvis, Inc. Laser diode driver with high power efficiency
US6545928B1 (en) * 2001-09-25 2003-04-08 Micron Technology, Inc. Antifuse programming current limiter
US6686772B2 (en) * 2001-11-19 2004-02-03 Broadcom Corporation Voltage mode differential driver and method
JP2003332623A (ja) * 2002-05-07 2003-11-21 Rohm Co Ltd 発光素子駆動装置及び、発光素子を備えた電子機器
JP4177022B2 (ja) * 2002-05-07 2008-11-05 ローム株式会社 発光素子駆動装置、及び発光素子を備えた電子機器
US6650143B1 (en) * 2002-07-08 2003-11-18 Kilopass Technologies, Inc. Field programmable gate array based upon transistor gate oxide breakdown
US6812733B1 (en) * 2002-08-02 2004-11-02 Pmc-Sierra, Inc. High-efficiency mixed voltage/current mode output driver
US7545839B2 (en) * 2003-01-02 2009-06-09 Optiswitch Technology Corporation Apparatus and method for driving a pulsed laser diode
US6897543B1 (en) * 2003-08-22 2005-05-24 Altera Corporation Electrically-programmable integrated circuit antifuses
US7262584B2 (en) * 2004-02-19 2007-08-28 Analog Modules, Inc Efficient fast pulsed laser or light-emitting diode driver
US7133429B2 (en) * 2004-03-05 2006-11-07 Finisar Corporation Laser driver circuit with signal transition enhancement
DE102004032456B3 (de) 2004-06-30 2006-04-06 Siemens Ag Schaltungsanordnung zum Betreiben eines Leuchtzeichens
US7154923B2 (en) * 2004-08-24 2006-12-26 International Business Machines Corporation Method and apparatus for providing a modulation current
US6965722B1 (en) * 2004-10-29 2005-11-15 Finisar Corporation High efficiency active matching electro-optic transducer driver circuit operable with low supply voltages
KR100652391B1 (ko) * 2004-12-17 2006-12-01 삼성전자주식회사 저전압 차동 신호 드라이버
FR2889643A1 (fr) 2005-08-08 2007-02-09 Valeo Systemes Thermiques Ajustement de l'intensite lumineuse, notamment d'un tableau de commande pour vehicule automobile
US7280425B2 (en) * 2005-09-30 2007-10-09 Intel Corporation Dual gate oxide one time programmable (OTP) antifuse cell
US7173851B1 (en) 2005-10-18 2007-02-06 Kilopass Technology, Inc. 3.5 transistor non-volatile memory cell using gate breakdown phenomena
WO2007069104A1 (fr) 2005-12-12 2007-06-21 Koninklijke Philips Electronics N.V. Systeme et procede pour ouvrir des liens web dans une application de navigateur
DE102005062486B4 (de) 2005-12-27 2007-10-31 Insta Elektro Gmbh Elektrisches/elektronisches Installationsgerät
US7978741B2 (en) * 2006-06-14 2011-07-12 Sumitomo Electric Industries, Ltd. Optical transmitter with a shunt driving configuration and a load transistor operated in common gate mode
US8188682B2 (en) * 2006-07-07 2012-05-29 Maxim Integrated Products, Inc. High current fast rise and fall time LED driver
US7312513B1 (en) * 2006-07-10 2007-12-25 Wilcox William J Antifuse circuit with well bias transistor
US8324816B2 (en) 2006-10-18 2012-12-04 Koa Corporation LED driving circuit
US20080304527A1 (en) * 2007-06-07 2008-12-11 Miaobin Gao Controlling a bias current for an optical source

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2009127670A1 *

Also Published As

Publication number Publication date
US8194431B2 (en) 2012-06-05
JP2011520250A (ja) 2011-07-14
WO2009127670A1 (fr) 2009-10-22
US20110080765A1 (en) 2011-04-07
JP5591792B2 (ja) 2014-09-17

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