EP2073380B1 - Controllable supply voltage circuit for power amplifier - Google Patents

Controllable supply voltage circuit for power amplifier Download PDF

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Publication number
EP2073380B1
EP2073380B1 EP08171784.5A EP08171784A EP2073380B1 EP 2073380 B1 EP2073380 B1 EP 2073380B1 EP 08171784 A EP08171784 A EP 08171784A EP 2073380 B1 EP2073380 B1 EP 2073380B1
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EP
European Patent Office
Prior art keywords
signal
envelope
pass filter
low pass
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP08171784.5A
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German (de)
English (en)
French (fr)
Other versions
EP2073380A3 (en
EP2073380A2 (en
Inventor
Hiroyoshi c/o Fujitsu Limited Ishikawa
Nobukazu c/o Fujitsu Limited Fudaba
Hajime c/o Fujitsu Limited Hamada
Yuichi c/o Fujitsu Limited Utsunomiya
Kazuo c/o Fujitsu Limited Nagatani
Toru c/o FUJITSU LIMITED Maniwa
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Fujitsu Ltd
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Fujitsu Ltd
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Filing date
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Publication of EP2073380A2 publication Critical patent/EP2073380A2/en
Publication of EP2073380A3 publication Critical patent/EP2073380A3/en
Application granted granted Critical
Publication of EP2073380B1 publication Critical patent/EP2073380B1/en
Ceased legal-status Critical Current
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
    • H03F1/0216—Continuous control
    • H03F1/0222—Continuous control by using a signal derived from the input signal
    • H03F1/0227—Continuous control by using a signal derived from the input signal using supply converters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers

Definitions

  • the present invention relates to a power amplifying apparatus to be used in a transmission section of a mobile terminal device, a radio relay device or the like.
  • the power amplifying apparatus includes a technique which improves a power use efficiency of a transmission section.
  • an envelope tracking method As one of techniques which improves power use efficiency of a power amplifier to be used in a transmission section of a mobile terminal device, a radio relay device or the like, an envelope tracking method (ET) is known. This method is a technique which controls a drain voltage or a collector voltage according to an envelope fluctuation of a transmission signal so as to heighten the power use efficiency of the power amplifier.
  • FIG. 1 illustrates a constitutional example of a power amplifying apparatus using the envelope tracking method.
  • the power amplifying apparatus 70 includes an envelope arithmetic section 71, a power supply circuit 72 and a power amplifier 73.
  • the envelope arithmetic section 71 calculates envelope information included in a transmission signal, and supplies the envelope information to the power supply circuit 72.
  • the power supply circuit 72 is composed of a switching amplifier having high power conversion efficiency, for example.
  • the power supply circuit 72 amplifies an output from the envelope arithmetic section 71 so as to generate a drain voltage, and supplies the drain voltage to the power amplifier 73 so as to amplify the transmission signal.
  • the switching amplifier used in the power supply circuit 72 does not have a conversion speed which is sufficient for tracking a change in the envelope information of the transmission signal.
  • a voltage control speed adjusting section 74 composed of a low pass filter (LPF) is provided between the envelope arithmetic section 71 and the power supply circuit 72 as illustrated in FIG. 2 conventionally.
  • the voltage control speed adjusting section 74 limits a band of the envelope signal and makes a change in the signal gentle so as to supply the signal to the power supply circuit 72.
  • a carrier wave input section 75 illustrated in FIG. 2 is a circuit which multiplies a transmission signal by a carrier wave so as to up-convert it into a radio frequency band.
  • FIG. 3 is a waveform chart of a conventional circuit illustrated in FIG. 2 and a two-tone signal which changes greatly and cannot be tracked by the power supply circuit 72 as an example of a transmission signal.
  • "a" in FIG. 3 denotes an envelope signal (two-tone signal) to be output from the envelope arithmetic section 71.
  • the band of this envelope signal is limited by the voltage control speed adjusting section 74, and the signal is adjusted to an output signal b whose change is gentle.
  • the output signal b is amplified by the power supply circuit (switching amplifier) 72, since the speed is adjusted, the signal can sufficiently follow the amplifying process in the power supply circuit 72, and an output voltage c whose waveform is approximately matched with that of the output signal b can be obtained.
  • the output voltage c is supplied as a drain voltage to the power amplifier 73.
  • Japanese Patent Application Laid-Open No. 05-316012 discloses a technique which controls rising and falling of a waveform of a trapezoidal envelope signal included in a transmission signal so as to control a spread of a power spectrum of a transmission output signal to a predetermined width.
  • FIG. 4 is a diagram describing a constitution of the power supply circuit (switching amplifier) 72, and includes a modulator 77, a power switch 78 and an LC filter 79.
  • An envelope signal is first input into the modulator 77 so as to be pulse-modulated, and is amplified by the power switch 78. Further, the signal is smoothed by the LC filter 79 so as to be generated as a drain voltage of the power amplifier 73.
  • FIG. 5 is a diagram describing a signal waveform in the switching amplifier.
  • d denotes an input signal to be input into the modulator 77, and it is pulse-modulated by the modulator 77, so as to have a comb-shaped waveform as illustrated by e.
  • f denotes an output waveform smoothed by the LC filter 79.
  • US2007/0258602A1 discloses a method for optimizing efficiency of a power amplifier of a transmitter in which a detected envelope of an input signal of the power amplifier is filtered with a non-linear filter that substantially preserves a rise time of a peak in a waveform of the envelope but lengthens a temporal duration of the peak.
  • a filtered envelope is used as an input quantity for a control system that controls a supply voltage of the power amplifier.
  • FIG. 6 is a circuit diagram of the power amplifying apparatus according to the first embodiment.
  • the power amplifying apparatus 1 includes an envelope arithmetic section 2, a voltage control adjusting section 3, a power supply circuit 4, a power amplifier 5, a carrier wave input section 6, digital/analog converting circuits (hereinafter, D/A converting circuits) 7 and 8.
  • the power amplifying apparatus 1 is used in a transmission section of a mobile telephone or a transmission section of a radio relay station, for example, and a transmission signal includes audio information or the like.
  • the envelope arithmetic section 2 calculates an envelope component included in the transmission signal and outputs it to the voltage control adjusting section 3.
  • the voltage control adjusting section 3 includes low pass filters (LPF) 10 and 11, a rising/falling determination circuit 12, a selecting circuit 13, and a discontinuity removing circuit 14.
  • the low pass filter (LPF) 10 is for a high cut-off frequency (for high speed)
  • the low pass filter (LPF) 11 is for a low cut-off frequency (for low speed).
  • the rising/falling determination circuit 12 detects a trough or a crest of an envelope signal to be input, and when detecting a trough of the envelope signal, it determines that the envelope signal rises thereafter. On the other hand, when detecting a crest of the envelope signal, the rising/falling determination circuit 12 determines that the envelope signal falls thereafter.
  • the selecting circuit 13 selects an output from the low pass filter (LPF) 10 or 11 based on the determined signal from the rising/falling determination circuit 12, and outputs the selected output to the discontinuity removing circuit 14.
  • the discontinuity removing circuit 14 is a circuit which removes discontinuity generated at the time of switching signals, and is composed of a low pass filter (LPF), for example.
  • the carrier wave input section 6 is a circuit which supplies a carrier wave to a transmission signal.
  • the D/A converting circuit 7 converts a signal output from the voltage control adjusting section 3 into an analog signal, and the D/A converting circuit 8 converts a transmission signal into an analog signal.
  • the power supply circuit 4 may be a switching amplifier that is composed of a modulator, a power switch and an LC filter (not shown).
  • the power supply circuit 4 pulse-modulates the D/A-converted output signal from the voltage control adjusting section 3 and amplifies the modulated signal using the power switch. Thereafter, the power supply circuit 4 generates a drain voltage via the LC filter and supplies it to the power amplifier 5.
  • FIG. 7 is a waveform chart illustrating speed adjustment of the envelope signal in the voltage control adjusting section 3.
  • the envelope signal calculated by the envelope arithmetic section 2 is input into the low pass filters (LPF) 10 and 11, and the rising/falling determination circuit 12.
  • LPF low pass filters
  • the rising/falling determination circuit 12 detects a trough of the envelope signal (I in FIG. 7 ), it determines that the envelope signal rises thereafter, and outputs a determined signal for selecting the low pass filter (LPF) 11 to the selecting circuit 13.
  • a delay circuit 11a is set at an output of the low pass filter (LPF) 11, and an output from the low pass filter (LPF) 11 is delayed by predetermined time T so as to be output to the selecting circuit 13. Therefore, in this case, rising h of the envelope signal is adjusted to a low speed by the low pass filter (LPF) 11 and is adjusted to i in FIG. 7 so as to be output from the selecting circuit 13 to the discontinuity removing circuit 14.
  • the rising/falling determination circuit 12 detects a crest (II described in FIG. 7 ) of the envelope signal, it determines that the envelope signal falls thereafter, and outputs a determined signal for selecting the low pass filter (LPF) 10 to the selecting circuit 13.
  • the delay circuit 10a is set also at an output of the low pass filter (LPF) 10, and the output from the low pass filter (LPF) 10 is delayed by predetermined time T so as to be output to the selecting circuit 13.
  • the determined signal to be input into the signal circuit is also delayed by T so as to be changed. Therefore, the output from the selecting circuit 13 is switched into a signal of the low pass filter (LPF) 10 at timing of the crest of the envelope signal, so as to be supplied to the discontinuity removing circuit 14.
  • the discontinuity removing circuit 14 removes discontinuity of the adjusted envelope signal, and outputs a signal adjusted to the power supply circuit 4 via the D/A converting circuit 7.
  • the power supply circuit 4 pulse-modulates a signal to be input and amplifies it using the power switch so as to supply it to the LC filter.
  • FIG. 8 is a diagram showing a signal waveform at the time of passing through the LC filter of the power supply circuit 4.
  • the rising of the envelope signal is delayed as shown by k in FIG. 8 .
  • the signal to be supplied to the LC filter has the signal waveform adjusted as illustrated in FIG. 7 . That is to say, in this embodiment, the rising of the signal to be input is early, and as illustrated by i in FIG. 7 , the signal rises early.
  • its output waveform is j as shown in FIG. 7 .
  • the output signal from the voltage control adjusting section 3 is amplified by the switching amplifier, and a voltage having a voltage waveform j is supplied to a drain of the power amplifier 5.
  • This drain voltage is a voltage whose falling tracks the envelope signal, and thus useless power consumption is eliminated and the power use efficiency can be improved.
  • the envelope signal which passes through the low-speed low pass filter is selected.
  • the envelope signal which passes the high-speed low pass filter is selected.
  • the rising of the envelope signal is adjusted to a low speed, and the falling of the envelope signal is adjusted to a high speed, so that the voltage amplified by the power supply circuit 4 as a switching amplifier is supplied as a drain voltage to the power amplifier 5.
  • the power supply circuit 4, the rising/falling determination circuit 12 and the selecting circuit 13 in the first embodiment correspond to voltage supply means, determination means and selecting means of the disclosed power amplifying apparatus, respectively.
  • a second embodiment of the disclosed power amplifying apparatus is described below.
  • FIG. 11 is a circuit diagram of the power amplifying apparatus 30 according to the second embodiment.
  • the power amplifying apparatus 30 includes the envelope arithmetic section 2, a voltage control adjusting section 31, the power supply circuit 4, the power amplifier 5, the carrier wave input section 6 and the like.
  • the power amplifying apparatus 30 of the second embodiment has the voltage control adjusting section 31 whose constitution is different from that of the apparatus shown in FIG. 6 , and the other circuits are similar to those in FIG. 6 . Therefore, the constitution of the voltage control adjusting section 31 is described, and description about the remaining circuit configuration is omitted.
  • the voltage control adjusting section 31 includes a rising/falling determination circuit 32, a short interval maximum value holding circuit 33, a long interval maximum value holding circuit 34, and a selecting circuit 35.
  • the rising/falling determination circuit 32 has the same constitution as that of the rising/falling determination circuit 12 described with reference to FIG. 6 , and detects a trough and a crest of the envelope signal. When detecting a trough of the envelope signal, the rising/falling determination circuit 32 determines that the envelope signal rises thereafter, and when detecting a crest of the envelope signal, it determines that the envelope signal falls thereafter, and outputs a corresponding selection signal to the selecting circuit 35.
  • the short interval maximum value holding circuit 33 and the long interval maximum value holding circuit 34 basically have the same circuit configuration, but the numbers of latch circuits and the numbers of sampling clocks to be used are different.
  • the circuit configuration of the long interval maximum value holding circuit 34 is described with reference to FIG. 12 .
  • the long interval maximum value holding circuit 34 includes latch circuits 36a to 36d, a maximum value acquiring circuit 37, a 1/5 frequency dividing circuit 38, and a maximum value holding circuit 39.
  • a sampling clock is input into clock input terminals (CLK) of the latch circuits 36a to 36d and the 1/5 frequency dividing circuit 38, and envelope signals to be input into data terminals (D) are synchronized with the sampling clocks so as to be transmitted sequentially from output terminals (Q) to right adjacent latch circuits.
  • the maximum value acquiring circuit 37 acquires maximum data in data latched by the latch circuits 36a to 36d, and outputs it to the maximum value holding circuit 39.
  • the maximum value holding circuit 39 inputs the data of the maximum value acquired by the maximum value acquiring circuit 37 through a D terminal, and makes it synchronous with a clock signal output from the 1/5 frequency dividing circuit 38 so as to output the data of the maximum value from a Q terminal to the selecting circuit 35.
  • FIG. 13 is a waveform chart illustrating speed adjustments of the envelope signal in the voltage control adjusting section 31.
  • the envelope signal calculated by the envelope arithmetic circuit 2 is input into the rising/falling determination circuit 32, and is input into the short interval maximum value holding circuit 33 and the long interval maximum value holding circuit 34.
  • the rising/falling determination circuit 32 When the rising/falling determination circuit 32 detects a trough (I shown in FIG. 13 ) of the envelope signal, it determines that the envelope signal rises thereafter, and outputs a determined signal for selecting the long interval maximum value holding circuit 34 to the selecting circuit 35.
  • a delay circuit 34a is set at an output of the long interval maximum value holding circuit 34, and the output from the long interval maximum value holding circuit 34 is delayed by predetermined time T so as to be output to the selecting circuit 35.
  • the long interval maximum value holding circuit 34 acquires data of maximum value among outputs of five sampling clocks. Therefore, the long interval maximum value holding circuit 34 is used on the rising of the envelope signal, so that the rising interval of the envelope signal can be adjusted to a low speed.
  • the rising/falling determination circuit 32 detects a crest (II shown in FIG. 13 ) of the envelope signal, it determines that the envelope signal falls thereafter, and outputs a determined signal for selecting the short interval maximum value holding circuit 33 to the selecting circuit 35.
  • a delay circuit 33a is set also at an output of the short interval maximum value holding circuit 33, and the output from the short interval maximum value holding circuit 33 is delayed by predetermined time T so as to be output to the selecting circuit 35.
  • data of the maximum value among the outputs of two or three sampling clocks namely, data of maximum value in a narrow sampling interval is obtained as illustrated in FIG. 13 . Therefore, when the short interval maximum value holding circuit 33 is used on the falling of the envelope signal, the falling interval of the envelope signal can be adjusted to a high speed.
  • the envelope signal whose speed is adjusted in such a manner is output to the power supply circuit 4 which is a switching amplifier via the D/A converting circuit 7.
  • the adjusted signal is pulse-modulated, it is amplified by a power switch so as to be supplied to a LC filter.
  • the amplified signal becomes an optimum drain voltage according to an operation property at the time of passing through the LC filter, so as to be supplied to the power amplifier 5. That is to say, the falling of the drain voltage is a voltage tracking the envelope signal accurately, and eliminates useless power in the power amplifier 5 so as to be capable of improving the power use efficiency.
  • the short interval maximum value holding circuit is used instead of a high-speed low pass filter
  • the long interval maximum value holding circuit is used instead of a low-speed low pass filter.
  • the power supply circuit 4, the rising/falling determination circuit 32 and the selecting circuit 35 in the second embodiment correspond to the voltage supply means, the determination means and the selecting means of the disclosed power amplifying apparatus, respectively.
  • the circuit in FIG. 12 is described above as the long interval maximum value holding circuit 34, and the short interval maximum value holding circuit 33 is described as a circuit which acquires maximum data among two or three sampling clocks (in this case, the short interval maximum value holding circuit 33 includes one or two latch circuit(s) and 1/2 or 1/3 frequency dividing circuit).
  • the circuit in FIG. 12 may be the short interval maximum value holding circuit 33, and the long interval maximum value holding circuit 34 may be a circuit which acquires maximum data among six or more sampling clocks (in this case, the long interval maximum value holding circuit 34 includes six or more latch circuits).
  • a third embodiment of the disclosed power amplifying apparatus is described below.
  • FIG. 14 is a circuit diagram of the power amplifying apparatus 40 according to the third embodiment, and it includes the envelope arithmetic section 2, a voltage control adjusting section 41, the power supply circuit 4 and the power amplifier 5.
  • the power amplifying apparatus 40 in the third embodiment has the voltage control adjusting section 41 whose constitution is different from that of the apparatus shown in FIG. 6 , and the other circuits are similar to those in FIG. 6 . Therefore, the constitution of the voltage control adjusting section 41 is described, and description about the remaining circuit configuration is omitted.
  • the voltage control adjusting section 41 includes low pass filters (LPF) 42 and 43, a selecting circuit 44, a discontinuity removing circuit 45, a tilt angle ⁇ calculating section 46 and a selection signal generating section 47. Similar to those shown in Fig. 6 , the low pass filter (LPF) 42 is a low pass filter for a high cut-off frequency (high-speed), and the low pass filter (LPF) 43 is a low pass filter for a low cut-off frequency (low speed).
  • LPF low pass filter
  • the tilt angle ⁇ calculating section 46 calculates a tilt angle ⁇ from a waveform shape of an envelope signal to be input. Concretely, as shown in FIG. 15 , the tilt angle ⁇ is calculated based on time on an abscissa axis (X axis) and a voltage value (amplitude value) on an ordinate axis (Y axis). For example, the tilt angle ⁇ calculating section 46 acquires time information from a time counting circuit, not shown, and measures a voltage (amplitude) from a trough to a peak value of the envelope signal to be input so as to calculate the tilt angle ⁇ .
  • the tilt angle ⁇ calculating section 46 outputs data about the measured tilt angle ⁇ to the selection signal generating section 47.
  • the selection signal generating section 47 compares the input data about the tilt angle ⁇ with data about a preset threshold. When the data about the tilt angle ⁇ is smaller than the data about the threshold, the selection signal generating section 47 determines that a change in the envelope signal is such that the power supply circuit 4 at a later stage can sufficiently track with using the high-speed low pass filter (LPF) 42, so outputs a selection signal for the LPF 42.
  • LPF high-speed low pass filter
  • the selection signal generating section 47 determines that the change in the envelope signal exceeds a level such that the power supply circuit 4 at the later stage can track with using the high-speed low pass filter (LPF) 42, so outputs a selection signal for the low-speed low pass filter (LPF) 43.
  • a drain voltage which is suitable for the tilt angle ⁇ of the envelope signal can be generated, and the drain voltage which efficiently tracks the envelope signal can drive the power amplifier 5.
  • the power supply circuit 4, the selecting circuit 44 and the tilt angle ⁇ calculating section 46 in the third embodiment correspond to the voltage supply means, the selecting means and the calculating means of the disclosed power amplifying apparatus, respectively.
  • the above description refers to the constitution that when the data about the tilt angle ⁇ is larger than the data about the threshold, the low-speed low pass filter (LPF) 43 is selected. Further, the constitution may be such that the rising/falling determination circuit is provided, and when the data about the tilt angle ⁇ is larger than the data about the threshold, the low pass filter (LPF) 42 or 43 may be selected according to a determined result of the rising/falling determination circuit.
  • a fourth embodiment 5 of the disclosed power amplifying apparatus is described below.
  • FIG. 16 is a circuit diagram illustrating a power amplifying apparatus 50 according to the fourth embodiment, and it includes the envelope arithmetic section 2, a voltage control adjusting section 51, the power supply circuit 4 and the power amplifier 5.
  • the power amplifying apparatus 50 in the fourth embodiment has the voltage control adjusting section 51 whose constitution is different from that of the apparatus shown in FIG. 6 , and the other circuits are similar to those in FIG. 6 . Therefore, the constitution of the voltage control adjusting section 51 is described, and description about the remaining circuit configurations is omitted.
  • the voltage control adjusting section 51 includes low-pass filters (LPF) 52 and 53, a rising/falling determination circuit 54, a selecting circuit 55, a discontinuity removing circuit 56, an envelope peak determination circuit 57, a low pass filter 58, a difference detecting circuit 59 and a selection signal generating section 60.
  • the low pass filter (LPF) 52 is a low pass filter for a high cut-off frequency (high speed)
  • the low pass filter (LPF) 53 is a low pass filter for a low cut-off frequency (low speed).
  • the rising/falling determination circuit 54 When the rising/falling determination circuit 54 detects a trough of the envelope signal, it determines that the envelope signal rises thereafter, and when detecting a crest of the envelope signal, it determines that the envelop signal falls thereafter.
  • the rising/falling determination circuit 54 outputs a corresponding determined signal to the selection signal generating section 60.
  • the envelope peak determination circuit 57 determines a peak of the envelope signal, and outputs a determined result to the selection signal generating section 60.
  • the difference detecting circuit 59 compares the envelope signal with an output waveform from the low pass filter 58 and detects a difference so as to output it to the selection signal generating section 60.
  • the selection signal generating section 60 compares difference data output from the difference detecting circuit 59 with a preset threshold at timing that the peak determined signal is supplied from the envelope peak determination circuit 57. When the difference data is larger than the preset threshold, the selection signal generating section 60 outputs the determined signal output from the rising/falling determination circuit 54 as a selection signal to the selecting circuit 55.
  • a " shown in FIG. 16 is a waveform chart illustrating a circuit operation in the difference detecting circuit 59
  • a waveform n shown in FIG. 16 is a waveform of the envelope signal output from the envelope arithmetic section 2
  • a waveform p is a waveform output from the low pass filter 58.
  • the difference detecting circuit 59 detects a difference between the waveforms n and p at timing that the envelope waveform reaches a peak, and when the difference is larger than a preset threshold, it outputs the determined signal output from the rising/falling determination circuit 54 to the selecting circuit 55.
  • the selection signal generating section 60 outputs a selection signal for selecting the low pass filter (LPF) 52 to the selecting circuit 55.
  • the change in the envelope signal is gentle, and the low pass filter whose cut-off frequency is high (high speed) is used to adjust the envelope signal so as to output it to the power supply circuit 4.
  • the change in the envelope signal when the change in the envelope signal is sharp, the rising of the envelope signal is adjusted to low speed, and the falling is adjusted to high speed so that the power use efficiency is improved.
  • the change in the envelope signal is gentle, the envelope signal is adjusted to high speed so that the power use efficiency can be further improved.
  • the power supply circuit 4, the rising/falling determination circuit 54, the selecting circuit 55, the envelope peak determination circuit 57, the difference detecting circuit 59 and the selection signal generating section 60 in the fourth embodiment correspond to the voltage supply means, the determination means, the selecting means, the peak determination means, the difference detecting means and the selection signal generating means of the disclosed power amplifying apparatus, respectively.
  • the adjustment speed in the voltage control adjusting section is changed, and the power use efficiency of the power amplifier can be improved without deteriorating the adjustment speed on the falling of the envelope signal.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Amplifiers (AREA)
  • Transmitters (AREA)
EP08171784.5A 2007-12-20 2008-12-16 Controllable supply voltage circuit for power amplifier Ceased EP2073380B1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007329371A JP4905344B2 (ja) 2007-12-20 2007-12-20 電力増幅装置

Publications (3)

Publication Number Publication Date
EP2073380A2 EP2073380A2 (en) 2009-06-24
EP2073380A3 EP2073380A3 (en) 2014-06-11
EP2073380B1 true EP2073380B1 (en) 2015-10-21

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EP08171784.5A Ceased EP2073380B1 (en) 2007-12-20 2008-12-16 Controllable supply voltage circuit for power amplifier

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US (1) US8154341B2 (ja)
EP (1) EP2073380B1 (ja)
JP (1) JP4905344B2 (ja)
KR (1) KR101060403B1 (ja)
CN (1) CN101465621B (ja)

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US8154341B2 (en) 2012-04-10
CN101465621B (zh) 2012-05-16
JP4905344B2 (ja) 2012-03-28
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JP2009152904A (ja) 2009-07-09
KR20090067085A (ko) 2009-06-24

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