EP1891682A1 - Photodiode presentant un courant d'obscurite reduit et procede de fabrication - Google Patents

Photodiode presentant un courant d'obscurite reduit et procede de fabrication

Info

Publication number
EP1891682A1
EP1891682A1 EP06742752A EP06742752A EP1891682A1 EP 1891682 A1 EP1891682 A1 EP 1891682A1 EP 06742752 A EP06742752 A EP 06742752A EP 06742752 A EP06742752 A EP 06742752A EP 1891682 A1 EP1891682 A1 EP 1891682A1
Authority
EP
European Patent Office
Prior art keywords
region
doping
semiconductor layer
substrate
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06742752A
Other languages
German (de)
English (en)
Inventor
Jochen Kraft
Bernhard LÖFFLER
Gerald Meinhardt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ams AG
Original Assignee
Austriamicrosystems AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Austriamicrosystems AG filed Critical Austriamicrosystems AG
Publication of EP1891682A1 publication Critical patent/EP1891682A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H01L31/1812—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table including only AIVBIV alloys, e.g. SiGe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H01L31/103—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PN homojunction type
    • H01L31/1035—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PN homojunction type the devices comprising active layers formed only by AIIIBV compounds
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • photodiodes or phototransistors For the detection of light semiconductor devices can be used, for example photodiodes or phototransistors. These components have in common that they have a pn junction, around which forms a space charge zone, which can be increased by a correspondingly applied external voltage. Light absorbed by the semiconductor body generates pairs of charge carriers that can be separated in the intrinsic or external electric field and supplied to corresponding external contacts. The electric current thus collected at the external contacts represents a measure of the incident light.
  • a semiconductor circuit with a photodiode which has two horizontally extending semiconductor junctions.
  • biased diodes and transistors exhibit diode leakage currents that are present when the voltage is applied and also when the light is off. These leakage currents limit the sensitivity of the photodiodes and represent a source of noise that can not be separated exactly from the actual photocurrent.
  • Impurities have energy states whose position is located between the valence band and the conductivity band. Charge carriers can therefore be much confused with such impurities at a given temperature. get into the conductivity band more easily. If the defect is within the adjacent field or within the space charge zone, the charge carriers or charge carrier pairs thus produced are also supplied to the corresponding contacts and produce the aforementioned dark current. Impurities occur in particular at phase boundaries or on surfaces. By high-energy implantations impurities can also be generated within the semiconductor body.
  • a photodiode or a phototransistor of high quality may have only a minimum dark current. It is therefore desirable to reduce the number of impurities.
  • Another way to reduce the dark current is to use a larger bandgap semiconductor, which makes it difficult to cross charge carriers into the conduction band even in the dark.
  • the dark current generated by diffusion can be reduced, since the saturation current J s proportional to
  • the object of the present invention is therefore to specify a diode with reduced dark current and a method for the production.
  • a diode whose semiconductor junction is formed between a doping region of the first conductivity type disposed in the surface of a crystalline substrate and a first semiconductor layer deposited thereon with a doping of the second conductivity type.
  • the pn junction is further away from the phase boundary between the substrate and the first semiconductor layer at the edge of the doping region and therefore arranged deeper in the substrate than in the center above the doping region. This causes impurities on the surface of the substrate or at the edge of the doping region to be within a doped region with dopant of the second conductivity type region and thus outside of the space charge zone.
  • the crystalline substrate of the diode comprises at least on the surface of any semiconductor material.
  • the substrate may be a homogeneous wafer, but may also have one or more subsequently deposited on a base wafer, for example by epitaxy and with respect to composition or doping different semiconductor layers.
  • the first semiconductor layer is also deposited on the substrate by epitaxial deposition in a CVD method.
  • the first semiconductor layer is preferably very thin. It therefore requires a very highly doped region for the construction of the field, under which, however, an intrinsic layer region may still lie. The pi junction is therefore sharp and the depletion zone extends beyond the phase boundary both into the first semiconductor layer and into the first doping region.
  • the first semiconductor layer is formed sufficiently thin and has, for example, a maximum thickness of 100 nm. This guarantees that a large part of the space charge zone is formed within the semiconductor substrate, that only the first semiconductor layer is highly doped and therefore the substrate has only a low dopant concentration in the region of the space charge zone, which is advantageous for the use of the diode as a photodiode. Low dopant concentration reduces the number of potential recombination centers in the substrate that can contribute to photocurrent reduction.
  • the doping region is enclosed by an isolation region.
  • This isolation region extends into the substrate and is, for example, as field oxide or filled with insulation material and etched into the substrate Trench formed, in particular as so-called STI isolation (shallow trench isolation).
  • the isolation region may be formed around the first conductivity type impurity region. However, it is also possible to form the first doping region in a region closed by the isolation region.
  • an additional doping of the second conductivity type can be provided, by means of which the pn junction in this region is laid deeper into the substrate.
  • the interface with the isolation area which is heavily affected by defects and defects, is removed from the pn junction and thus also from the space charge zone, so that a main source for the emergence of dark flow is eliminated.
  • the doping of the second conductivity type is widened in this way into the substrate.
  • the diode can also be part of a transistor.
  • a second semiconductor layer with a doping of the first conductivity type which represents the emitter for the diode formed from substrate (collector) and first semiconductor layer (base) are arranged above the first semiconductor layer.
  • the second semiconductor layer is minimized in terms of its base area and, for example, only at the edge of the active diode surface (transistor surface) or only centrally arranged. As a result, excessive shading of the active device surface in the event of light is avoided.
  • the substrate may comprise monocrystalline silicon.
  • the first semiconductor layer is a silicon germanium. nium layer. Within this layer, a germanium concentration profile can be arranged, with the highest germanium concentration at the phase boundary to the substrate. This makes it possible to generate an additional field accelerating the charge carriers.
  • the first semiconductor layer is preferably formed over a large area and extends not only over the active diode region, but also beyond the isolation region. This makes it possible to use this portion extending beyond the active diode region for the electrical connection of this layer.
  • this connection region can be provided with a higher conductivity, for example by a higher doping of the second conductivity type.
  • the overlapping area between the first semiconductor layer and the first doping area may be defined by the limiting isolation area.
  • the window within this insulation layer can therefore be smaller but also larger than the area surrounded by the isolation area.
  • a method of fabricating a reduced dark current diode comprises the steps of: a) generating a first conductivity type doping region in the surface of a semiconductor material substrate; b) defining an active region in the surface of the substrate by forming an isolation region annularly surrounding the doping region; c) applying a doped semiconductor layer of the second conductivity type, d) introducing an additional doping of the second conductivity type into the substrate in the region, the phase boundary between the active region and the isolation region.
  • the part of the first semiconductor layer which is to form the lead can be doped more highly by implantation outside the active region and the required mask to be set so that during implantation said additional doping at the edge of the active region within the substrate becomes.
  • oblique implantation angles are between 80 ° and 45 °, with 90 ° representing a vertical implantation against the surface of the substrate.
  • the oblique implantation is performed in four steps, between which the substrate is rotated by 90 ° in each case.
  • the diode can be expanded to a transistor.
  • an insulation layer is produced over the first semiconductor layer, in which an emitter window is opened and there the first semiconductor layer is exposed.
  • An emitter layer is then deposited over the insulation layer and patterned by means of a mask in an etching step.
  • a resist mask can be used, which remain on the substrate and can serve as implantation mask in the subsequent implantation of dopant for higher doping of the connecting line within the first semiconductor layer.
  • a further possibility for producing additional doping utilizes a further process step known from CMOS technology, with which the electrical insulation of a plurality of semiconductor components arranged next to one another on a wafer can be improved.
  • This step which is also known as a field oxide implant or an anti-punch-through implant, involves a high-energy implantation of dopant from second conductivity type in the region below the isolation region, that is usually below the field oxide isolation, which encloses the active diode region, thus the doping region.
  • the implantation mask used is a FOX implant mask and designed here to produce the desired additional doping such that the dopant also reaches the edge of the active region during implantation and generates an additional doping or a counterdoping there.
  • FIGS. 1 to 4 show, by means of schematic cross sections, different process stages in the production of a diode according to the invention
  • FIG. 5 shows the implantation of the connecting line
  • FIG. 6 shows the production of the additional doping by means of the FOX implant mask.
  • FIG. 1 shows, in a schematic cross-section, a crystalline semiconductor substrate SU, in which a doped semiconductor region DG of the first conductivity type is arranged.
  • This doped region may extend over the entire surface of the substrate or, as shown in the figure, form only a narrow region on the surface of the substrate.
  • the doped region DG is enclosed in a ring shape by an insulation region IG, which is formed, for example, by field oxide by oxidation of the substrate surface.
  • the doped region may be generated before or after the formation of the isolated regions.
  • Not shown in the figure are means for contacting the doped region or for producing a connection. This can be done, for example, via a buried layer arranged below the doped region.
  • the connection to the surface of the substrate or to the surface of the finished component can then take place via a doped connection region extending to the surface (also not shown in the figure).
  • a thin insulating layer IS is deposited over the entire surface of the substrate and an amorphous poly-silicon layer PS is deposited over it.
  • a window is subsequently etched into the two layers and the surface of the doped region DG is exposed underneath. The window is dimensioned so that a part of the isolation area IG is also exposed.
  • FIG. 2 shows the arrangement on this process stage.
  • a semiconductor layer HS is applied over the whole area.
  • a semiconductor layer HS is applied over the whole area.
  • a semiconductor layer HS is applied over the whole area.
  • a silicon-germanium layer grown under epitaxial conditions. This forms monocrystalline in contact with the substrate surface, above the isolated regions or the amorphous polysilicon layer PS on the other hand polycrystalline.
  • the dashed line PG indicates the phase boundary of the monocrystalline region above the doped region DG.
  • the amorphous polysilicon layer PS is used in the epitaxial deposition to reduce the surface reflectivity to allow a homogeneous heating of the surface by means of radiant heating. It is also clear from FIG. 3 that the window etched in amorphous polysilicon layer PS and insulating layer IS has a larger surface area than the doped region DG exposed on the surface of the substrate. Only in this way is it possible to position the substrate stage outside of this defined by the exposed surface of the doped region active diode surface, as an additional substrate stage at the boundary of a field oxide isolation region would result in a too steep or high topological stage over which the homogeneous Deposition of further layers in sufficient layer thickness would be difficult.
  • FIG. 4 shows the component with additional doping GD already generated in the edge region of the doping region DG or at the interface of the doped region with the surrounding insulation region IG.
  • the doping of the first conductivity type in the doped region DG corresponds to an n-doping, so that both the semiconductor layer HS and additional doping GD have a p-doping. It is clear from FIG. 4 that the pn junction in the middle of the active region is formed between the semiconductor layer HS and the surface of the substrate in the doped region DG, but at the edge region at the interface between doped region DG and additional doping GD.
  • the exact shape of the additional doping is indicated only schematically in FIG. 4 and, depending on the manufacturing method used, can also be deeper, flatter or narrower.
  • FIG. 5A shows a simple possibility of generating the additional doping GD together with the top doping of the semiconductor layer HS for producing a low-resistance connection to the semiconductor layer outside the active region.
  • an implantation mask IM is generated above the active area, for example a photoresist mask.
  • an implantation IP with a dopant of the second conductivity type is now carried out. In this case, it is possible to select the dopant dose sufficiently high that, in a subsequent annealing step, diffusion of the dopant into the doping region DG takes place in order to generate the additional doping.
  • the dopant with such high implantation energy that it penetrates through the surface layers into the region of the additional doping to be produced.
  • a dopant with high penetration such as boron ions implanted.
  • the doping can be homogenized.
  • a temperature budget can be introduced, which it is sufficient to drive the doping into the desired range of additional doping.
  • FIG. 5B shows an implantation IP indicated by arrows with the same mask as in FIG. 5A, but at an oblique implantation angle. In this way, the implanted dopant can penetrate below the mask and also introduce the additional doping in the desired area.
  • FIG. 6 shows a further possibility for producing the additional doping.
  • the isolation regions IG After the definition of the active regions by means of the production of the isolation regions IG, their isolation effect is enhanced by introducing a doping of the second conductivity type below the isolation regions IG.
  • This anti-punch-through doping is performed with a high implantation energy through the insulation regions IG, which consist in particular of field oxide.
  • This implantation step can also be used to generate the additional doping in the boundary region between isolation region and doped region DG.
  • Insulation regions IG consisting especially of field oxide support the method, since a field oxide is thinner in the edge region than in the center and runs out into a bird's beak-like structure, which can be penetrated more easily during the implantation of dopant.
  • this implantation can also be carried out at an oblique implantation angle and / or subsequently homogenized and activated by an annealing step.
  • the additional doping GD at the edge region of the active diode interface can also be directly in a separate process with a separate Mask step done. If, for the production of the additive doping, process steps are used which are already used by default to produce a conventional diode, they can also be varied in other ways in such a way that additional doping is produced in the desired range. In particular, the masks used for implantation can be varied accordingly. A deeper implantation can also be achieved by forming a so-called scattering oxide, which is produced on the surface of semiconductor layers before the implementation of an implantation step, correspondingly thinner.
  • the component can be covered with insulation and passivation layers and can be covered by the insulation elements l mich reaching contacts are connected.
  • the doping region is preferably extended below the isolation regions or connected in a low-resistance manner by a prolonged buried layer within the doped region to a corresponding contact applied to the surface of the device.
  • Such a finished photodiode or a correspondingly formed phototransistor shows a substantially reduced dark current compared to a similar component without said additional doping.
  • the noise floor of the photodiode or the phototransistor is thus reduced and obtained a better signal-to-noise ratio. Incident light rays can therefore be detected with greater accuracy and higher sensitivity.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Light Receiving Elements (AREA)
  • Element Separation (AREA)

Abstract

L'invention concerne une photodiode comportant une jonction PN créée entre la zone de dopage (DG) pratiquée dans la surface d'un substrat à semiconducteurs cristallin et une couche à semiconducteurs (HS) déposée au-dessus de celle-ci. Un dopage supplémentaire (GD) est prévu dans la partie marginale de la zone dopée, la jonction PN s'étendant plus profondément dans le substrat (SU) avec ce dopage supplémentaire. La distance ainsi augmentée entre la jonction PN et des zones d'imperfection sur des frontières de phase permet de réduire le courant d'obscurité à l'intérieur de la photodiode.
EP06742752A 2005-06-14 2006-04-28 Photodiode presentant un courant d'obscurite reduit et procede de fabrication Withdrawn EP1891682A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102005027456A DE102005027456B4 (de) 2005-06-14 2005-06-14 Photodiode mit verringertem Dunkelstrom, Verfahren zur Herstellung und ihre Verwendung
PCT/EP2006/004027 WO2006133765A1 (fr) 2005-06-14 2006-04-28 Photodiode presentant un courant d'obscurite reduit et procede de fabrication

Publications (1)

Publication Number Publication Date
EP1891682A1 true EP1891682A1 (fr) 2008-02-27

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EP06742752A Withdrawn EP1891682A1 (fr) 2005-06-14 2006-04-28 Photodiode presentant un courant d'obscurite reduit et procede de fabrication

Country Status (4)

Country Link
US (1) US8134179B2 (fr)
EP (1) EP1891682A1 (fr)
DE (1) DE102005027456B4 (fr)
WO (1) WO2006133765A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2713409B1 (fr) 2012-09-27 2020-08-26 ams AG Photodiode avec zone de charge d'espace qui peut être réduite par une électrode de champ
EP3490000B1 (fr) 2017-11-24 2023-01-04 ams AG Dispositif semi-conducteur de photodétecteur infrarouge proche

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JPS6195580A (ja) 1984-10-17 1986-05-14 Hitachi Ltd 受光素子およびこの受光素子を内臓した光電子装置
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Also Published As

Publication number Publication date
US8134179B2 (en) 2012-03-13
DE102005027456A1 (de) 2006-12-28
US20100038678A1 (en) 2010-02-18
DE102005027456B4 (de) 2008-10-16
WO2006133765A1 (fr) 2006-12-21

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