Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J9/00—Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
  • H01J9/02—Manufacture of electrodes or electrode systems
  • H01J9/022—Manufacture of electrodes or electrode systems of cold cathodes
  • H01J9/025—Manufacture of electrodes or electrode systems of cold cathodes of field emission cathodes
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B82—NANOTECHNOLOGY
  • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
  • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B82—NANOTECHNOLOGY
  • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
  • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B82—NANOTECHNOLOGY
  • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
  • B82Y40/00—Manufacture or treatment of nanostructures
• • C—CHEMISTRY; METALLURGY
  • C01—INORGANIC CHEMISTRY
  • C01B—NON-METALLIC ELEMENTS; COMPOUNDS THEREOF; METALLOIDS OR COMPOUNDS THEREOF NOT COVERED BY SUBCLASS C01C
  • C01B32/00—Carbon; Compounds thereof
  • C01B32/15—Nano-sized carbon materials
  • C01B32/158—Carbon nanotubes
  • C01B32/16—Preparation
  • C01B32/162—Preparation characterised by catalysts
• • D—TEXTILES; PAPER
  • D01—NATURAL OR MAN-MADE THREADS OR FIBRES; SPINNING
  • D01F—CHEMICAL FEATURES IN THE MANUFACTURE OF ARTIFICIAL FILAMENTS, THREADS, FIBRES, BRISTLES OR RIBBONS; APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OF CARBON FILAMENTS
  • D01F9/00—Artificial filaments or the like of other substances; Manufacture thereof; Apparatus specially adapted for the manufacture of carbon filaments
  • D01F9/08—Artificial filaments or the like of other substances; Manufacture thereof; Apparatus specially adapted for the manufacture of carbon filaments of inorganic material
  • D01F9/12—Carbon filaments; Apparatus specially adapted for the manufacture thereof
  • D01F9/127—Carbon filaments; Apparatus specially adapted for the manufacture thereof by thermal decomposition of hydrocarbon gases or vapours or other carbon-containing compounds in the form of gas or vapour, e.g. carbon monoxide, alcohols
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J1/00—Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
  • H01J1/02—Main electrodes
  • H01J1/30—Cold cathodes, e.g. field-emissive cathode
  • H01J1/304—Field-emissive cathodes
  • H01J1/3048—Distributed particle emitters
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J31/00—Cathode ray tubes; Electron beam tubes
  • H01J31/08—Cathode ray tubes; Electron beam tubes having a screen on or from which an image or pattern is formed, picked up, converted, or stored
  • H01J31/10—Image or pattern display tubes, i.e. having electrical input and optical output; Flying-spot tubes for scanning purposes
  • H01J31/12—Image or pattern display tubes, i.e. having electrical input and optical output; Flying-spot tubes for scanning purposes with luminescent screen
  • H01J31/123—Flat display tubes
  • H01J31/125—Flat display tubes provided with control means permitting the electron beam to reach selected parts of the screen, e.g. digital selection
  • H01J31/127—Flat display tubes provided with control means permitting the electron beam to reach selected parts of the screen, e.g. digital selection using large area or array sources, i.e. essentially a source for each pixel group
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
  • H10K10/40—Organic transistors
  • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
  • H10K10/462—Insulated gate field-effect transistors [IGFETs]
  • H10K10/464—Lateral top-gate IGFETs comprising only a single gate
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
  • H10K10/40—Organic transistors
  • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
  • H10K10/462—Insulated gate field-effect transistors [IGFETs]
  • H10K10/481—Insulated gate field-effect transistors [IGFETs] characterised by the gate conductors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J2201/00—Electrodes common to discharge tubes
  • H01J2201/30—Cold cathodes
  • H01J2201/304—Field emission cathodes
  • H01J2201/30446—Field emission cathodes characterised by the emitter material
  • H01J2201/30453—Carbon types
  • H01J2201/30469—Carbon nanotubes (CNTs)
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J2201/00—Electrodes common to discharge tubes
  • H01J2201/30—Cold cathodes
  • H01J2201/319—Circuit elements associated with the emitters by direct integration
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
  • H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
  • H10K85/221—Carbon nanotubes

Definitions

• the invention relates to a method for manufacturing an emissive cathode comprising a cathode layer structured in columns, a grid layer structured in lines and emissive pads, the emitting pads being self - aligned with the lines of the gate layer. According to a particular embodiment, the emitting pads are also self-aligned with the columns of the cathode layer.
• Cathodic structures are mainly used in field emission excited cathodo-luminescence display devices and particularly in field emission flat screens.
• These field emission display devices comprise a cathode, which emits electrons, and an anode, opposite the cathode, covered with one or more luminescent layers.
• the anode and the cathode are separated by a space kept under vacuum.
• the cathode is either a source based on microtips, or a source based on a low threshold field emissive layer. If it is a low-threshold emissive layer, this layer may consist of nanostructures such as nanotubes, nanowires or nanofilaments; these nanostructures are made of electrically conductive material, such as carbon; they may also consist of multilayers (for example, multilayers of AlN or BN).
• the structure of the cathode may be of the diode or triode type. Triode structures have an additional electrode called a gate that controls the extraction of electrons. For flat screen application, a cathode having a triode structure is used because this particular structure makes it possible to separate the control voltage (gate voltage) from the anode voltage. Indeed, the control voltage must be low in order to minimize the cost of the addressing transistors ("drivers"), while the anode voltage must be as high as possible in order to improve the light output of the cathode and to minimize energy consumption. Triode type cathodes consist of rows and columns, the intersection of a line and a column defining a pixel. During operation of the cathode, the data to be displayed are fed to the columns, while the lines are sequentially scanned in order to address the entire screen, that is to say all the pixels of the screen.
• a triode-type cathode is described in Application FR 2,836,279, filed February 19, 2002, and is illustrated in Figures IA and IB.
• This cathode comprises the following elements: a first conductive level consisting of a structured cathode layer in the form of columns 7,
• a resistive layer 2 for example an amorphous silicon layer
• a layer of insulating material 6 placed between the resistive layer 2 and a second conducting level 10; a second conducting level consisting of a grid layer 8 structured in the form of lines 9, potential of this second level to control the extraction of electrons,
• a cavity 16 is made by etching the gate layer 8 and the layer of insulating material 6.
• a cavity 16 has a width of 10 to 15 microns and the grids are arranged with a pitch of 20 to 25 microns between the lines.
• FIG. 1A it can be seen that the lines 9 are engraved with cavities 16 at the intersection of the lines 9 and the columns 7, and that the lines are also etched outside these intersections to form thinner lines 11 .
• the columns 7 of the cathode layer have a particular perforated structure 13, forming sub-columns 4, on which the resistive layer 2 is deposited.
• the studs 14 must be positioned in the cavities between the sub-columns so that the electrical connection of the sub-columns 4 to the pads 14 is done through the resistive layer 2.
• the disadvantage of this method is that it requires two precise alignments, a first alignment of the cavities 16 with respect to the sub-columns 4, with an accuracy of the order of 1 to 2 ⁇ m (FIG. second alignment of the emitting pads 14, with respect to the grids 10, with an accuracy of at least 0.5 microns (Figure 2D).
• An off-centering of the cavities 16 with respect to the sub-columns 4 leads to a variation of the access resistance of the sub-columns to the emissive pads by the resistive layer. This variation remains second-order as long as the decentering does not exceed 2 ⁇ m.
• the object of the invention is to improve the known method so as to reduce the number of necessary alignments. This and other objects are achieved according to the invention by a method of producing a triode-type cathode structure comprising:
• deposition steps on a face of a substrate, of a cathode layer of electrically conductive material, of a resistive layer, of an electric insulating layer, of a grid layer of electrically conductive material , so as to form a stack, the gate layer forming the surface layer of the stack and being adjacent to the insulating layer,
• the cathode layer for structuring it into cathode conductors arranged in a form chosen from one of the line form and the column form,
• the gate layer for structuring it into gate conductors arranged in a form selected from the other between the line form and the column form,
• the method being characterized in that the etching steps of the structured gate layer in grid conductors and the electrical insulating layer are performed by: a) depositing a layer of resin on the grid layer structured in grid conductors, b) lithography and development of the resin layer to obtain openings in the resin layer arranged in a pattern intended to form emitting studs at the bottom of the cavities, c) etching of the grid layer structured in grid conductors, according to the pattern, d) etching of the layer of insulator under to the grid layer structured in grid conductors by widening the etching beyond the patterns of emissive pads to obtain a cavity width
• the structuring of the cathode layer, to structure it in cathode conductors, and the etching of said cathode layer structured in cathode conductors, to give it a perforated structure are carried out before the deposit of the resistive layer.
• the structuring of the cathode layer, to structure it in cathode conductors is carried out before the deposition of the insulating layer and, the insulator layer and the cathode layer structured in conductors of cathode being located between the grid layer structured in grid conductors and the resistive layer, step e) is completed by an etching of the cathode layer structured in cathode conductors, at the level of the areas exposed by the etching of the layer of insulation to reach the resistive layer, so as to provide a perforated structure to the cathode layer structured in cathode conductors.
• a diffusion barrier layer of the catalyst is deposited in the openings of the resin layer.
• the structuring of the cathode layer into cathode conductors or / and the structuring of the gate conductor layer is (are) carried out by etching through a mask obtained by photolithography.
• the structuring of the cathode layer to structure it into cathode conductors is completed by the etching of at least a portion of the thickness of the resistive layer at the areas exposed by the structuring from the cathode layer structured into cathode conductors.
• the resistive layer can thus be etched, for example, during the same lithography step as that used to etch the cathode layer into cathode conductors, which makes it possible to perfectly isolate the cathode conductors from each other and to avoid the leakage currents between the cathode leads during the operation of the screen.
• This embodiment is particularly interesting when it is desired to minimize the power consumption. It is specified that the resistive layer is etched between the columns, but not inside a column.
• the structuring of the cathode layer into cathode conductors and / or the structuring of the gate conductor layer is (are) carried out by depositing through a metal mask.
• step g) of removing the resin layer is carried out by "lift-off” or by dissolving the resin layer.
• the method of production further comprises a step of growing nanostructures of the nanotube, nanowire or nanofilament type on the catalyst layer to form the emitting pads.
• step d) of etching the insulating layer is an isotropic wet etching.
• Isotropic etching makes it possible to obtain a cavity centered in the insulator layer with respect to the pattern of the pads defined in the resin layer.
• the method according to the invention makes it possible to produce cathode structures that can be used in particular in flat-field emission displays and / or in backlighting ("backlight") for liquid crystal display LCDs (liquid crystal display LCDs). in English) .
• FIG. described is a top view of a cathode structure of triode type according to the prior art
• FIG. 1B is a sectional view of an enlarged portion of the cathode structure shown in FIG. 1A along the dashed lines;
• FIGS. 2A to 2F already described, illustrate a method of producing a triode type cathode structure according to the prior art
• FIGS. 3A to 3F illustrate a first embodiment of the method according to the invention
• FIGS. 4A to 4F illustrate a second embodiment of the method according to the invention.
• the originality of the production method according to the invention is based on the use of a single layer of resin for etching the grid layer, structured in grid conductors, through openings made in the resin layer, etching the insulating layer by extending the etching laterally under the grid layer to obtain cavities, etching the exposed grid layer under the resin layer and depositing a catalyst layer on the resistive layer at the bottom of the cavities, in the openings made in the resin layer.
• the embodiment method according to the invention allows, according to a first variant, to self-align the emitting pads with respect to the grid conductors, that is to say to position the emitting pads with respect to the grid conductors without having aligning the pads on the cavities formed in the gate layer, which eliminates one of the constraints of the prior art.
• the method also allows, according to a second variant, to self-align the emitting pads with respect to the gate conductors and with respect to the cathode conductors; the two alignment constraints of the prior art are thus removed.
• the different steps of the first variant are illustrated in FIGS. 3A to 3F.
• a layer of conductive material for example a molybdenum layer having a thickness of 0.2 ⁇ m.
• cleaning of the support substrate may optionally be carried out by known means of the basic laundry type.
• This conducting layer is then lithographed and etched so as to structure this layer in columns and sub-columns: a structured cathode layer 24 is then obtained (in FIG. 3A only two sub-columns are visible ).
• the columns are arranged in a pitch of 350 ⁇ m, with a space of 50 ⁇ m between the columns and the sub-columns have widths between 5 to 10 microns and are spaced from 10 to 15 microns.
• the sub-columns are etched to obtain perforated structures at locations that correspond to the superposition of the cathode conductors (columns) and the grid conductors (lines).
• the sub-columns are made for example parallel to the columns.
• etching of the cathode layer as it is a molybdenum layer, reactive ion etching (RIE) is etched with an SF 6 type gas,
• RIE reactive ion etching
• a resistive layer 22 is deposited (for example a phosphor doped amorphous silicon layer deposited by cathode sputtering and having a thickness of 1 ⁇ m).
• insulator 26 for example a 1 ⁇ m layer of silica deposited by chemical vapor deposition (CVD)
• a gate layer 30 for example a 0.2 ⁇ m thick layer of molybdenum deposited by electron gun evaporation
• the gate layer 30 is then lithographed and etched so as to form lines in a pitch of 350 ⁇ m and spaced by 50 ⁇ m, according to the same principle explained above for the etching of the columns in the cathode layer: a structured grid layer 300.
• a resin layer 27 of 1.2 ⁇ m thick is deposited on the structured grid layer 300 and this layer is lithographed.
• resin 27 in a pattern having the shape of the emitting pads 34 that it is desired to form on the resistive layer 22.
• the patterns may for example be rectangles 3 to 10 microns wide.
• the patterns of the pads must be centered with an accuracy of the order of 1 to 2 microns in the space of 10 to 15 microns which separates the column conductors 300.
• a lithography is carried out to obtain studs 34 of 4 , 5 x 4.5 ⁇ m on the side.
• Insolation of the resin layer 27 is carried out with proximity lithography equipment, then the resin is developed.
• the structured grid layer 300 is then etched according to the pattern.
• the structured grid layer 300 may be etched by wet etching or dry etching; in this example, the molybdenum layer is etched with RIE.
• the insulating layer 26 undergoes wet etching. This etching is done until the insulating layer is etched over a width L greater than the width of the patterns intended to form the emitting pads 34, but less than or equal to the distance separating two adjacent sub-columns 24 (FIG. 3C).
• the etching time of the insulating layer 26 determines the width L of the cavity 36 in the insulator.
• the nature of the insulation is chosen so that an isotropic etching is obtained chemically.
• the cavity 36 of width L is centered with respect to the pattern of the pads 34 defined in the resin layer 27.
• the silica insulating layer 26 is etched with the NH 4 F mixture, HF.
• a barrier layer 25 and a catalyst layer 29 are deposited through the resin mask, that is to say on the resin layer 27 and in the openings present in this resin layer 27 (FIG. 3E).
• the barrier layer 25, deposited between the resistive layer 22 and the catalyst layer 29, is not essential, but it makes it possible to better control the growth of the nanotubes (by avoiding, among other things, the diffusion of the catalyst) and / or improve the electrical contacts between the nanotubes and the resistive layer.
• Emissive pads 34 on the resistive layer 22 located at equal distances from the gate conductors of the structured gate layer 300 are thus obtained.
• a 80 nm thick TiN barrier layer is deposited by cathode sputtering.
• a triode-type cathode structure comprising a support substrate 21 on which a cathode layer 24 structured in columns and sub-columns is arranged, a resistive layer 22 covering this structured cathode layer 24, an insulating layer 26 having cavities 36 between two adjacent sub-columns, this insulating layer being covered with a structured grid layer 300, structured in lines, emitting pads 34 being located in the cavities 36 on the resistive layer 22.
• a resistive layer 22 is first deposited on the face of the support substrate 21, then a cathode layer is deposited and etched to structure it according to columns 40.
• the openwork structure columns formation of the sub-columns
• the openwork structure columns is obtained by etching through the openings made in the resin layer 27, once the insulating layer 26 has been etched.
• This second variant thus makes it possible to obtain a totally self-aligned method: the emitting pads 34 are centered both with respect to the lines of the structured grid layer 300 and by relative to the sub-columns of the structured cathode layer 400. This method makes it possible to eliminate the constraint related to the obligation to perform an alignment of the order of a micrometer.
• FIGS. 4A to 4F The steps of this variant of the embodiment method are illustrated in FIGS. 4A to 4F.
• a support substrate 21 of borosilicate glass 1.1 mm thick is used.
• the support substrate 21 may optionally be cleaned by known means of the basic laundry type.
• a resistive layer 22 is deposited in phosphor doped amorphous silicon 1 ⁇ m thick, for example by sputtering.
• a layer of electrically conductive material for forming the cathode layer for example a layer of 0.2 microns molybdenum by evaporation electron gun.
• the cathode layer is then lithographed and etched, for example by RIE etching, so as to form columns arranged in a pitch of 350 microns and spaced 50 microns, according to the same principle explained above (deposition of the resin, insolation and development of the resin, etching of the cathode layer, dissolution of the resin): a cathode layer structured as cathode conductors 40 (columns) is thus obtained.
• the columns are solid, that is to say without the perforated structure characteristic of the first variant: the perforated structure of the columns will be obtained later during the process.
• the etching of the resistive layer 22 is interesting when the problem of the electrical consumption is critical.
• an insulator layer 26 is then deposited on the cathode layer structured in cathode conductors 40 (for example a 1 ⁇ m silica layer deposited by CVD), then a layer of electrically conductive material to form the cathode layer.
• gate layer for example a molybdenum layer deposited by electron-gun evaporation and having a thickness of 0.2 ⁇ m.
• the gate layer is lithographed and etched to form gate conductors (lines) arranged at a pitch of 350 ⁇ m and spaced 50 ⁇ m according to the same principle explained for the etching of the cathode conductors (columns) in the cathode layer : thus, a structured grid layer 300 is obtained.
• a 1.2 ⁇ m thick resin layer 27 is deposited on the structured grid layer 300, and this resin layer 27 is lithographed and etched in a pattern designed to form emitting pads 34, for example studs. 4.5 x 4.5 ⁇ m side on the resistive layer.
• the layer of structured grid 300 is etched, by dry or wet etching, according to the pattern of the resin layer 27.
• the structured molybdenum grid layer 300 is etched by RIE.
• wet etching of the insulating layer 26 during an etching time which determines, as in the first variant, the width L of the cavity 36 ( Figure 4C).
• the sub-columns and the perforated structure of the cathode conductors are thus formed: a structured cathode layer 400 is obtained in columns and in sub-columns. These layers are in molybdenum and are etched with a "Cr Etch" type bath for 2 minutes, then the structure is rinsed with deionized water and dried.
• a catalyst layer, or a barrier layer 25 and a catalyst layer 29, is deposited through the resin mask, that is to say on the resin layer 27 and in the openings formed in this layer of resin. resin.
• a 80 nm thick TiN barrier layer is first deposited by sputtering through the resin mask, and then a layer of 10 nm nickel catalyst 29 by evaporation with an electron gun (FIG. 4E).
• emissive pads 34 are obtained on the resistive layer 22 located at equal distances from the grid layer structured in grid conductors 300.
• the resin layer 27 is removed, for example by dissolving the resin (FIG. 4F).
• This variant of the method has the advantage that the cavities 36 in the grid layer structured in grid conductors 300 and in the insulating layer 26, the formation of the perforated structure of the cathode conductors (formation of the structured layer 400 to from the cathode layer structured in cathode conductors 40), as well as the deposition of the emitting pads 34 through the resin mask are made with the same level of lithography, that is to say with the same mask obtained by lithography of the resin layer 27 to form the patterns of the emitting pads ( Figure 4C to 4E).
• the distance between the pads 34 and the grid conductors (lines) of the structured grid layer 300, on the one hand, and between the pads 34 and the sub-columns of the structured cathode layer 400, on the other hand, is determined by the etching time of the insulating layer 26.
• the emitting pads 34 are automatically centered with respect to the grid conductors (lines) and the sub-columns of the conductors cathode (columns). This eliminates the two alignment constraints of the prior art.

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  • 2006-05-29 US US11/915,222 patent/US7785164B2/en not_active Expired - Fee Related
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