EP1688993A3 - Procédé standardise de fixation de semi-conducteurs et appareil associé - Google Patents

Procédé standardise de fixation de semi-conducteurs et appareil associé Download PDF

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Publication number
EP1688993A3
EP1688993A3 EP06101077A EP06101077A EP1688993A3 EP 1688993 A3 EP1688993 A3 EP 1688993A3 EP 06101077 A EP06101077 A EP 06101077A EP 06101077 A EP06101077 A EP 06101077A EP 1688993 A3 EP1688993 A3 EP 1688993A3
Authority
EP
European Patent Office
Prior art keywords
die
standardized
array
employed
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06101077A
Other languages
German (de)
English (en)
Other versions
EP1688993A2 (fr
Inventor
Warren M. Farnworth
Alan G. Wood
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
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First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=24515660&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=EP1688993(A3) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of EP1688993A2 publication Critical patent/EP1688993A2/fr
Publication of EP1688993A3 publication Critical patent/EP1688993A3/fr
Withdrawn legal-status Critical Current

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    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)
EP06101077A 1996-04-02 1997-04-01 Procédé standardise de fixation de semi-conducteurs et appareil associé Withdrawn EP1688993A3 (fr)

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US08/627,680 US6169329B1 (en) 1996-04-02 1996-04-02 Semiconductor devices having interconnections using standardized bonding locations and methods of designing
EP97917805A EP0950260A1 (fr) 1996-04-02 1997-04-01 Procede standardise de fixation de semi-conducteurs et appareil associe

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EP (2) EP0950260A1 (fr)
AU (1) AU2604097A (fr)
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Families Citing this family (145)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1092857A (ja) * 1996-09-10 1998-04-10 Mitsubishi Electric Corp 半導体パッケージ
US6215184B1 (en) * 1998-02-19 2001-04-10 Texas Instruments Incorporated Optimized circuit design layout for high performance ball grid array packages
US6351040B1 (en) * 1998-01-22 2002-02-26 Micron Technology, Inc. Method and apparatus for implementing selected functionality on an integrated circuit device
US6329712B1 (en) * 1998-03-25 2001-12-11 Micron Technology, Inc. High density flip chip memory arrays
US5933713A (en) * 1998-04-06 1999-08-03 Micron Technology, Inc. Method of forming overmolded chip scale package and resulting product
US6143981A (en) 1998-06-24 2000-11-07 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
US6376352B1 (en) * 1998-11-05 2002-04-23 Texas Instruments Incorporated Stud-cone bump for probe tips used in known good die carriers
US6707159B1 (en) * 1999-02-18 2004-03-16 Rohm Co., Ltd. Semiconductor chip and production process therefor
US6407450B1 (en) * 1999-07-15 2002-06-18 Altera Corporation Semiconductor package with universal substrate for electrically interfacing with different sized chips that have different logic functions
US6285077B1 (en) * 1999-08-19 2001-09-04 Lsi Logic Corporation Multiple layer tape ball grid array package
US6249047B1 (en) * 1999-09-02 2001-06-19 Micron Technology, Inc. Ball array layout
KR20010037247A (ko) * 1999-10-15 2001-05-07 마이클 디. 오브라이언 반도체패키지
US6362525B1 (en) * 1999-11-09 2002-03-26 Cypress Semiconductor Corp. Circuit structure including a passive element formed within a grid array substrate and method for making the same
US6475828B1 (en) 1999-11-10 2002-11-05 Lsi Logic Corporation Method of using both a non-filled flux underfill and a filled flux underfill to manufacture a flip-chip
US6534861B1 (en) * 1999-11-15 2003-03-18 Substrate Technologies Incorporated Ball grid substrate for lead-on-chip semiconductor package
US6395097B1 (en) 1999-12-16 2002-05-28 Lsi Logic Corporation Method and apparatus for cleaning and removing flux from an electronic component package
KR100421774B1 (ko) * 1999-12-16 2004-03-10 앰코 테크놀로지 코리아 주식회사 반도체패키지 및 그 제조 방법
JP4629826B2 (ja) * 2000-02-22 2011-02-09 パナソニック株式会社 半導体集積回路装置
US7042068B2 (en) 2000-04-27 2006-05-09 Amkor Technology, Inc. Leadframe and semiconductor package made using the leadframe
US6465338B1 (en) 2000-07-10 2002-10-15 Lsi Logic Corporation Method of planarizing die solder balls by employing a die's weight
US6562641B1 (en) 2000-08-22 2003-05-13 Micron Technology, Inc. Apparatus and methods of semiconductor packages having circuit-bearing interconnect components
US6548757B1 (en) 2000-08-28 2003-04-15 Micron Technology, Inc. Microelectronic device assemblies having a shielded input and methods for manufacturing and operating such microelectronic device assemblies
US6627999B2 (en) 2000-08-31 2003-09-30 Micron Technology, Inc. Flip-chip with matched signal lines, ground plane and ground bumps adjacent signal bumps
US6462423B1 (en) 2000-08-31 2002-10-08 Micron Technology, Inc. Flip-chip with matched lines and ground plane
JP3822040B2 (ja) * 2000-08-31 2006-09-13 株式会社ルネサステクノロジ 電子装置及びその製造方法
US6407462B1 (en) * 2000-12-30 2002-06-18 Lsi Logic Corporation Irregular grid bond pad layout arrangement for a flip chip package
US6745273B1 (en) 2001-01-12 2004-06-01 Lsi Logic Corporation Automatic deadlock prevention via arbitration switching
US6504256B2 (en) * 2001-01-30 2003-01-07 Bae Systems Information And Electronic Systems Integration, Inc. Insitu radiation protection of integrated circuits
DE10108077B4 (de) * 2001-02-20 2005-09-08 Infineon Technologies Ag IC-Chip mit Anschlusskontaktflächen und ESD-Schutz
JP2002252304A (ja) 2001-02-23 2002-09-06 Toshiba Corp 半導体装置およびこれに用いられる支持基板
US8158508B2 (en) * 2001-03-05 2012-04-17 Megica Corporation Structure and manufacturing method of a chip scale package
US6818545B2 (en) 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US6545345B1 (en) 2001-03-20 2003-04-08 Amkor Technology, Inc. Mounting for a package containing a chip
KR100369393B1 (ko) * 2001-03-27 2003-02-05 앰코 테크놀로지 코리아 주식회사 리드프레임 및 이를 이용한 반도체패키지와 그 제조 방법
KR100393448B1 (ko) * 2001-03-27 2003-08-02 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
US6879492B2 (en) * 2001-03-28 2005-04-12 International Business Machines Corporation Hyperbga buildup laminate
US6680213B2 (en) 2001-04-02 2004-01-20 Micron Technology, Inc. Method and system for fabricating contacts on semiconductor components
US6472239B2 (en) * 2001-04-02 2002-10-29 Micron Technology, Inc. Method for fabricating semiconductor components
US6597059B1 (en) 2001-04-04 2003-07-22 Amkor Technology, Inc. Thermally enhanced chip scale lead on chip semiconductor package
US6479319B1 (en) 2001-04-20 2002-11-12 Lsi Logic Corporation Contact escape pattern
US6828884B2 (en) * 2001-05-09 2004-12-07 Science Applications International Corporation Phase change control devices and circuits for guiding electromagnetic waves employing phase change control devices
US6590292B1 (en) 2001-06-01 2003-07-08 Lsi Logic Corporation Thermal and mechanical attachment of a heatspreader to a flip-chip integrated circuit structure using underfill
TW531873B (en) * 2001-06-12 2003-05-11 Advanced Interconnect Tech Ltd Barrier cap for under bump metal
KR100415279B1 (ko) * 2001-06-26 2004-01-16 삼성전자주식회사 칩 적층 패키지 및 그 제조 방법
US6531932B1 (en) 2001-06-27 2003-03-11 Lsi Logic Corporation Microstrip package having optimized signal line impedance control
DE10139986A1 (de) * 2001-08-22 2002-11-14 Infineon Technologies Ag Elektronisches Bauteil mit wenigstens einem Halbleiterchip und Verfahren zu seiner Herstellung
US6882034B2 (en) * 2001-08-29 2005-04-19 Micron Technology, Inc. Routing element for use in multi-chip modules, multi-chip modules including the routing element, and methods
US6991970B2 (en) * 2001-08-30 2006-01-31 Micron Technology, Inc. Method and apparatus for circuit completion through the use of ball bonds or other connections during the formation of semiconductor device
US6472762B1 (en) 2001-08-31 2002-10-29 Lsi Logic Corporation Enhanced laminate flipchip package using a high CTE heatspreader
US6528735B1 (en) 2001-09-07 2003-03-04 International Business Machines Corporation Substrate design of a chip using a generic substrate design
US6847105B2 (en) 2001-09-21 2005-01-25 Micron Technology, Inc. Bumping technology in stacked die configurations
US6674174B2 (en) * 2001-11-13 2004-01-06 Skyworks Solutions, Inc. Controlled impedance transmission lines in a redistribution layer
US6671865B1 (en) 2001-11-27 2003-12-30 Lsi Logic Corporation High density input output
US6908784B1 (en) * 2002-03-06 2005-06-21 Micron Technology, Inc. Method for fabricating encapsulated semiconductor components
US7423336B2 (en) * 2002-04-08 2008-09-09 Micron Technology, Inc. Bond pad rerouting element, rerouted semiconductor devices including the rerouting element, and assemblies including the rerouted semiconductor devices
US6608366B1 (en) 2002-04-15 2003-08-19 Harry J. Fogelson Lead frame with plated end leads
TW550800B (en) * 2002-05-27 2003-09-01 Via Tech Inc Integrated circuit package without solder mask and method for the same
US7157790B2 (en) * 2002-07-31 2007-01-02 Microchip Technology Inc. Single die stitch bonding
US7326594B2 (en) * 2002-07-31 2008-02-05 Microchip Technology Incorporated Connecting a plurality of bond pads and/or inner leads with a single bond wire
US6800930B2 (en) 2002-07-31 2004-10-05 Micron Technology, Inc. Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies
US6965160B2 (en) * 2002-08-15 2005-11-15 Micron Technology, Inc. Semiconductor dice packages employing at least one redistribution layer
US6911624B2 (en) * 2002-08-23 2005-06-28 Micron Technology, Inc. Component installation, removal, and replacement apparatus and method
US6903442B2 (en) * 2002-08-29 2005-06-07 Micron Technology, Inc. Semiconductor component having backside pin contacts
US6818973B1 (en) 2002-09-09 2004-11-16 Amkor Technology, Inc. Exposed lead QFP package fabricated through the use of a partial saw process
US7723210B2 (en) 2002-11-08 2010-05-25 Amkor Technology, Inc. Direct-write wafer level chip scale package
US6905914B1 (en) 2002-11-08 2005-06-14 Amkor Technology, Inc. Wafer level package and fabrication method
US6798047B1 (en) 2002-12-26 2004-09-28 Amkor Technology, Inc. Pre-molded leadframe
US7388294B2 (en) * 2003-01-27 2008-06-17 Micron Technology, Inc. Semiconductor components having stacked dice
US6750545B1 (en) 2003-02-28 2004-06-15 Amkor Technology, Inc. Semiconductor package capable of die stacking
US6794740B1 (en) 2003-03-13 2004-09-21 Amkor Technology, Inc. Leadframe package for semiconductor devices
US6841883B1 (en) * 2003-03-31 2005-01-11 Micron Technology, Inc. Multi-dice chip scale semiconductor components and wafer level methods of fabrication
US6953994B2 (en) * 2003-10-02 2005-10-11 Interdigital Technology Corporation Wireless coupling of staked dies within system in package
US7078792B2 (en) * 2004-04-30 2006-07-18 Atmel Corporation Universal interconnect die
US7419852B2 (en) * 2004-08-27 2008-09-02 Micron Technology, Inc. Low temperature methods of forming back side redistribution layers in association with through wafer interconnects, semiconductor devices including same, and assemblies
US7635919B1 (en) * 2005-05-26 2009-12-22 Rockwell Collins, Inc. Low modulus stress buffer coating in microelectronic devices
US8039956B2 (en) * 2005-08-22 2011-10-18 Texas Instruments Incorporated High current semiconductor device system having low resistance and inductance
US7335536B2 (en) 2005-09-01 2008-02-26 Texas Instruments Incorporated Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices
US7485969B2 (en) * 2005-09-01 2009-02-03 Micron Technology, Inc. Stacked microelectronic devices and methods for manufacturing microelectronic devices
US7507603B1 (en) 2005-12-02 2009-03-24 Amkor Technology, Inc. Etch singulated semiconductor package
WO2007067982A2 (fr) * 2005-12-08 2007-06-14 Fairchild Semiconductor Corporation Mlp pour puce retournée avec encre conductrice
US7572681B1 (en) 2005-12-08 2009-08-11 Amkor Technology, Inc. Embedded electronic component package
TWI303870B (en) * 2005-12-30 2008-12-01 Advanced Semiconductor Eng Structure and mtehod for packaging a chip
SG135066A1 (en) 2006-02-20 2007-09-28 Micron Technology Inc Semiconductor device assemblies including face-to-face semiconductor dice, systems including such assemblies, and methods for fabricating such assemblies
US7902660B1 (en) 2006-05-24 2011-03-08 Amkor Technology, Inc. Substrate for semiconductor device and manufacturing method thereof
US7968998B1 (en) 2006-06-21 2011-06-28 Amkor Technology, Inc. Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package
US7687893B2 (en) 2006-12-27 2010-03-30 Amkor Technology, Inc. Semiconductor package having leadframe with exposed anchor pads
US7829990B1 (en) 2007-01-18 2010-11-09 Amkor Technology, Inc. Stackable semiconductor package including laminate interposer
US8922028B2 (en) * 2007-02-13 2014-12-30 Advanced Semiconductor Engineering, Inc. Semiconductor package
US7982297B1 (en) 2007-03-06 2011-07-19 Amkor Technology, Inc. Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same
US7977774B2 (en) 2007-07-10 2011-07-12 Amkor Technology, Inc. Fusion quad flat semiconductor package
US7687899B1 (en) 2007-08-07 2010-03-30 Amkor Technology, Inc. Dual laminate package structure with embedded elements
US8174110B2 (en) * 2007-09-04 2012-05-08 Epson Imaging Devices Corporation Semiconductor device having at least two terminals among the plurality of terminals electrically connected to each other while not being adjacent to one other and not being connected to internal circuit
US7777351B1 (en) 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
US8089159B1 (en) 2007-10-03 2012-01-03 Amkor Technology, Inc. Semiconductor package with increased I/O density and method of making the same
US7847386B1 (en) 2007-11-05 2010-12-07 Amkor Technology, Inc. Reduced size stacked semiconductor package and method of making the same
US7956453B1 (en) 2008-01-16 2011-06-07 Amkor Technology, Inc. Semiconductor package with patterning layer and method of making same
US7723852B1 (en) 2008-01-21 2010-05-25 Amkor Technology, Inc. Stacked semiconductor package and method of making same
TWI378285B (en) * 2008-03-28 2012-12-01 Au Optronics Corp Display device for disposing driving chip with different sizes
US8067821B1 (en) 2008-04-10 2011-11-29 Amkor Technology, Inc. Flat semiconductor package with half package molding
US7768135B1 (en) 2008-04-17 2010-08-03 Amkor Technology, Inc. Semiconductor package with fast power-up cycle and method of making same
US7808084B1 (en) 2008-05-06 2010-10-05 Amkor Technology, Inc. Semiconductor package with half-etched locking features
US8125064B1 (en) 2008-07-28 2012-02-28 Amkor Technology, Inc. Increased I/O semiconductor package and method of making same
US8184453B1 (en) 2008-07-31 2012-05-22 Amkor Technology, Inc. Increased capacity semiconductor package
US7847392B1 (en) 2008-09-30 2010-12-07 Amkor Technology, Inc. Semiconductor device including leadframe with increased I/O
US7989933B1 (en) 2008-10-06 2011-08-02 Amkor Technology, Inc. Increased I/O leadframe and semiconductor device including same
US8008758B1 (en) 2008-10-27 2011-08-30 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe
US8089145B1 (en) 2008-11-17 2012-01-03 Amkor Technology, Inc. Semiconductor device including increased capacity leadframe
US8072050B1 (en) 2008-11-18 2011-12-06 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including passive device
US7875963B1 (en) 2008-11-21 2011-01-25 Amkor Technology, Inc. Semiconductor device including leadframe having power bars and increased I/O
US7982298B1 (en) 2008-12-03 2011-07-19 Amkor Technology, Inc. Package in package semiconductor device
US8487420B1 (en) 2008-12-08 2013-07-16 Amkor Technology, Inc. Package in package semiconductor device with film over wire
US8680656B1 (en) 2009-01-05 2014-03-25 Amkor Technology, Inc. Leadframe structure for concentrated photovoltaic receiver package
US20170117214A1 (en) 2009-01-05 2017-04-27 Amkor Technology, Inc. Semiconductor device with through-mold via
US8058715B1 (en) 2009-01-09 2011-11-15 Amkor Technology, Inc. Package in package device for RF transceiver module
US8026589B1 (en) 2009-02-23 2011-09-27 Amkor Technology, Inc. Reduced profile stackable semiconductor package
US7960818B1 (en) 2009-03-04 2011-06-14 Amkor Technology, Inc. Conformal shield on punch QFN semiconductor package
US8575742B1 (en) 2009-04-06 2013-11-05 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including power bars
US8796561B1 (en) 2009-10-05 2014-08-05 Amkor Technology, Inc. Fan out build up substrate stackable package and method
US8937381B1 (en) 2009-12-03 2015-01-20 Amkor Technology, Inc. Thin stackable package and method
US9691734B1 (en) 2009-12-07 2017-06-27 Amkor Technology, Inc. Method of forming a plurality of electronic component packages
US8324511B1 (en) 2010-04-06 2012-12-04 Amkor Technology, Inc. Through via nub reveal method and structure
US8294276B1 (en) 2010-05-27 2012-10-23 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
US8440554B1 (en) 2010-08-02 2013-05-14 Amkor Technology, Inc. Through via connected backside embedded circuit features structure and method
US8487445B1 (en) 2010-10-05 2013-07-16 Amkor Technology, Inc. Semiconductor device having through electrodes protruding from dielectric layer
KR101796116B1 (ko) 2010-10-20 2017-11-10 삼성전자 주식회사 반도체 장치, 이를 포함하는 메모리 모듈, 메모리 시스템 및 그 동작방법
US8791501B1 (en) 2010-12-03 2014-07-29 Amkor Technology, Inc. Integrated passive device structure and method
US8390130B1 (en) 2011-01-06 2013-03-05 Amkor Technology, Inc. Through via recessed reveal structure and method
US8648450B1 (en) 2011-01-27 2014-02-11 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands
TWI557183B (zh) 2015-12-16 2016-11-11 財團法人工業技術研究院 矽氧烷組成物、以及包含其之光電裝置
US8552548B1 (en) 2011-11-29 2013-10-08 Amkor Technology, Inc. Conductive pad on protruding through electrode semiconductor device
US9704725B1 (en) 2012-03-06 2017-07-11 Amkor Technology, Inc. Semiconductor device with leadframe configured to facilitate reduced burr formation
US9048298B1 (en) 2012-03-29 2015-06-02 Amkor Technology, Inc. Backside warpage control structure and fabrication method
US9129943B1 (en) 2012-03-29 2015-09-08 Amkor Technology, Inc. Embedded component package and fabrication method
US8742599B2 (en) * 2012-08-30 2014-06-03 Freescale Semiconductor, Inc. Identification mechanism for semiconductor device die
KR101486790B1 (ko) 2013-05-02 2015-01-28 앰코 테크놀로지 코리아 주식회사 강성보강부를 갖는 마이크로 리드프레임
KR101563911B1 (ko) 2013-10-24 2015-10-28 앰코 테크놀로지 코리아 주식회사 반도체 패키지
US9373600B2 (en) * 2014-01-27 2016-06-21 Semiconductor Components Industries, Llc Package substrate structure for enhanced signal transmission and method
US9673122B2 (en) 2014-05-02 2017-06-06 Amkor Technology, Inc. Micro lead frame structure having reinforcing portions and method
US9780040B1 (en) * 2014-08-07 2017-10-03 Altera Corporation Integrated circuit package substrates having a common die dependent region and methods for designing the same
TWI620296B (zh) * 2015-08-14 2018-04-01 矽品精密工業股份有限公司 電子封裝件及其製法
US10109570B2 (en) * 2016-09-21 2018-10-23 Intel Corporation Radial solder ball pattern for attaching semiconductor and micromechanical chips
US10068866B2 (en) * 2016-09-29 2018-09-04 Intel Corporation Integrated circuit package having rectangular aspect ratio
US11373991B2 (en) 2020-02-06 2022-06-28 Lumileds Llc Methods of manufacturing light-emitting devices with metal inlays and bottom contacts
US11575074B2 (en) 2020-07-21 2023-02-07 Lumileds Llc Light-emitting device with metal inlay and top contacts
US12087716B2 (en) * 2021-12-21 2024-09-10 Micron Technology, Inc. Techniques for positioning bond pads of microelectronic devices and related microelectronic devices, methods, and systems

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59229850A (ja) * 1983-05-16 1984-12-24 Rohm Co Ltd 半導体装置
JPS61287133A (ja) * 1985-06-13 1986-12-17 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
EP0348972A2 (fr) * 1988-07-01 1990-01-03 Sharp Kabushiki Kaisha Dispositif semi-conducteur et procédé pour sa fabrication
JPH03165550A (ja) * 1989-11-24 1991-07-17 Hitachi Cable Ltd 高実装密度型半導体装置
EP0486829A2 (fr) * 1990-10-22 1992-05-27 Seiko Epson Corporation Dispositif semi-conducteur et système d'empaquetage pour dispositif semi-conducteur
US5216278A (en) * 1990-12-04 1993-06-01 Motorola, Inc. Semiconductor device having a pad array carrier package
EP0575051A1 (fr) * 1992-05-22 1993-12-22 National Semiconductor Corporation Modules à plusieurs puces empilées et procédé de fabrication
EP0660405A2 (fr) * 1993-12-22 1995-06-28 International Business Machines Corporation Boîtier de puce pour le montage en surface
US5454160A (en) * 1993-12-03 1995-10-03 Ncr Corporation Apparatus and method for stacking integrated circuit devices

Family Cites Families (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5785244A (en) 1980-11-18 1982-05-27 Fujitsu Ltd Semiconductor device
CA1229426A (fr) * 1984-04-19 1987-11-17 Yutaka Harada Dispositif supraconducteur
US4772936A (en) 1984-09-24 1988-09-20 United Technologies Corporation Pretestable double-sided tab design
US5082802A (en) * 1985-11-12 1992-01-21 Texas Instruments Incorporated Method of making a memory device by packaging two integrated circuit dies in one package
JPS6432150A (en) 1987-07-29 1989-02-02 Teijin Ltd Reflection color measuring instrument
JPS6461934A (en) 1987-09-02 1989-03-08 Nippon Denso Co Semiconductor device and manufacture thereof
US4862322A (en) * 1988-05-02 1989-08-29 Bickford Harry R Double electronic device structure having beam leads solderlessly bonded between contact locations on each device and projecting outwardly from therebetween
JP2610487B2 (ja) * 1988-06-10 1997-05-14 株式会社日立製作所 セラミック積層回路基板
US5138434A (en) 1991-01-22 1992-08-11 Micron Technology, Inc. Packaging for semiconductor logic devices
US5200362A (en) * 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
US5147815A (en) * 1990-05-14 1992-09-15 Motorola, Inc. Method for fabricating a multichip semiconductor device having two interdigitated leadframes
US5399903A (en) 1990-08-15 1995-03-21 Lsi Logic Corporation Semiconductor device having an universal die size inner lead layout
US5168345A (en) 1990-08-15 1992-12-01 Lsi Logic Corporation Semiconductor device having a universal die size inner lead layout
JP2876773B2 (ja) * 1990-10-22 1999-03-31 セイコーエプソン株式会社 プログラム命令語長可変型計算装置及びデータ処理装置
US5379191A (en) 1991-02-26 1995-01-03 Microelectronics And Computer Technology Corporation Compact adapter package providing peripheral to area translation for an integrated circuit chip
US5289346A (en) * 1991-02-26 1994-02-22 Microelectronics And Computer Technology Corporation Peripheral to area adapter with protective bumper for an integrated circuit chip
JP2966972B2 (ja) * 1991-07-05 1999-10-25 株式会社日立製作所 半導体チップキャリアとそれを実装したモジュール及びそれを組み込んだ電子機器
JPH0536857A (ja) 1991-07-30 1993-02-12 Toshiba Corp 半導体集積回路実装基板
JPH05129366A (ja) * 1991-11-08 1993-05-25 Fujitsu Ltd 集積回路用ｔａｂ実装構造
JP2894071B2 (ja) * 1992-03-09 1999-05-24 株式会社日立製作所 半導体装置
US5334857A (en) * 1992-04-06 1994-08-02 Motorola, Inc. Semiconductor device with test-only contacts and method for making the same
US5438224A (en) * 1992-04-23 1995-08-01 Motorola, Inc. Integrated circuit package having a face-to-face IC chip arrangement
JP3088877B2 (ja) * 1992-06-25 2000-09-18 日東電工株式会社 フィルムキャリアの製造方法および半導体装置
JP3267409B2 (ja) * 1992-11-24 2002-03-18 株式会社日立製作所 半導体集積回路装置
US5311057A (en) * 1992-11-27 1994-05-10 Motorola Inc. Lead-on-chip semiconductor device and method for making the same
US5365409A (en) 1993-02-20 1994-11-15 Vlsi Technology, Inc. Integrated circuit package design having an intermediate die-attach substrate bonded to a leadframe
US5291062A (en) * 1993-03-01 1994-03-01 Motorola, Inc. Area array semiconductor device having a lid with functional contacts
US5327008A (en) 1993-03-22 1994-07-05 Motorola Inc. Semiconductor device having universal low-stress die support and method for making the same
US5355283A (en) 1993-04-14 1994-10-11 Amkor Electronics, Inc. Ball grid array with via interconnection
US5495397A (en) 1993-04-27 1996-02-27 International Business Machines Corporation Three dimensional package and architecture for high performance computer
US5384487A (en) * 1993-05-05 1995-01-24 Lsi Logic Corporation Off-axis power branches for interior bond pad arrangements
US5490324A (en) * 1993-09-15 1996-02-13 Lsi Logic Corporation Method of making integrated circuit package having multiple bonding tiers
US5593927A (en) 1993-10-14 1997-01-14 Micron Technology, Inc. Method for packaging semiconductor dice
JP2531464B2 (ja) * 1993-12-10 1996-09-04 日本電気株式会社 半導体パッケ―ジ
JPH07169872A (ja) * 1993-12-13 1995-07-04 Fujitsu Ltd 半導体装置及びその製造方法
US5424492A (en) 1994-01-06 1995-06-13 Dell Usa, L.P. Optimal PCB routing methodology for high I/O density interconnect devices
US5506756A (en) 1994-01-25 1996-04-09 Intel Corporation Tape BGA package die-up/die down
JP2833996B2 (ja) * 1994-05-25 1998-12-09 日本電気株式会社 フレキシブルフィルム及びこれを有する半導体装置
US5497397A (en) * 1994-06-29 1996-03-05 General Electric Company Parallel dataword modulation scheme
US5741729A (en) 1994-07-11 1998-04-21 Sun Microsystems, Inc. Ball grid array package for an integrated circuit
JP3142723B2 (ja) 1994-09-21 2001-03-07 シャープ株式会社 半導体装置及びその製造方法
JP2792532B2 (ja) 1994-09-30 1998-09-03 日本電気株式会社 半導体装置の製造方法及び半導体ウエハー
JP2546192B2 (ja) * 1994-09-30 1996-10-23 日本電気株式会社 フィルムキャリア半導体装置
US5498767A (en) 1994-10-11 1996-03-12 Motorola, Inc. Method for positioning bond pads in a semiconductor die layout
US5715144A (en) * 1994-12-30 1998-02-03 International Business Machines Corporation Multi-layer, multi-chip pyramid and circuit board structure
TW373308B (en) * 1995-02-24 1999-11-01 Agere Systems Inc Thin packaging of multi-chip modules with enhanced thermal/power management
KR100218996B1 (ko) 1995-03-24 1999-09-01 모기 쥰이찌 반도체장치
WO1997037374A2 (fr) 1996-03-26 1997-10-09 Advanced Micro Devices, Inc. Procede economique d'encapsulation de plusieurs puces de circuit integre dans un boitier classique de semi-conducteur conçu pour une seule puce

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59229850A (ja) * 1983-05-16 1984-12-24 Rohm Co Ltd 半導体装置
JPS61287133A (ja) * 1985-06-13 1986-12-17 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
EP0348972A2 (fr) * 1988-07-01 1990-01-03 Sharp Kabushiki Kaisha Dispositif semi-conducteur et procédé pour sa fabrication
JPH03165550A (ja) * 1989-11-24 1991-07-17 Hitachi Cable Ltd 高実装密度型半導体装置
EP0486829A2 (fr) * 1990-10-22 1992-05-27 Seiko Epson Corporation Dispositif semi-conducteur et système d'empaquetage pour dispositif semi-conducteur
US5216278A (en) * 1990-12-04 1993-06-01 Motorola, Inc. Semiconductor device having a pad array carrier package
EP0575051A1 (fr) * 1992-05-22 1993-12-22 National Semiconductor Corporation Modules à plusieurs puces empilées et procédé de fabrication
US5454160A (en) * 1993-12-03 1995-10-03 Ncr Corporation Apparatus and method for stacking integrated circuit devices
EP0660405A2 (fr) * 1993-12-22 1995-06-28 International Business Machines Corporation Boîtier de puce pour le montage en surface

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"HIGH-PERFORMANCE PROCESSOR", 1 March 1989, IBM TECHNICAL DISCLOSURE BULLETIN, IBM CORP. NEW YORK, US, PAGE(S) 229-231, ISSN: 0018-8689, XP000120401 *
CICONE R A ET AL: "SILICON INTEGRATED HIGH PERFORMANCE PACKAGE", 1 December 1984, IBM TECHNICAL DISCLOSURE BULLETIN, IBM CORP. NEW YORK, US, PAGE(S) 4226, ISSN: 0018-8689, XP002010996 *

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US6169329B1 (en) 2001-01-02
EP0950260A1 (fr) 1999-10-20
AU2604097A (en) 1997-10-22
JP3766103B2 (ja) 2006-04-12
WO1997037383A1 (fr) 1997-10-09
US6048753A (en) 2000-04-11
EP1688993A2 (fr) 2006-08-09
EP0950260A4 (fr) 1999-10-20

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