WO2007067982A2 - Mlp pour puce retournée avec encre conductrice - Google Patents

Mlp pour puce retournée avec encre conductrice Download PDF

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Publication number
WO2007067982A2
WO2007067982A2 PCT/US2006/061799 US2006061799W WO2007067982A2 WO 2007067982 A2 WO2007067982 A2 WO 2007067982A2 US 2006061799 W US2006061799 W US 2006061799W WO 2007067982 A2 WO2007067982 A2 WO 2007067982A2
Authority
WO
WIPO (PCT)
Prior art keywords
leadframe
die
packaging
semiconductor device
tape
Prior art date
Application number
PCT/US2006/061799
Other languages
English (en)
Other versions
WO2007067982A3 (fr
Inventor
Seung-Young Choi
Ti-Ching Shian
Maria Cristina B. Estacio
Original Assignee
Fairchild Semiconductor Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/364,014 external-priority patent/US7638861B2/en
Application filed by Fairchild Semiconductor Corporation filed Critical Fairchild Semiconductor Corporation
Priority to CN2006800459980A priority Critical patent/CN101385134B/zh
Priority to KR1020117029367A priority patent/KR101363463B1/ko
Priority to KR1020087013404A priority patent/KR101135828B1/ko
Publication of WO2007067982A2 publication Critical patent/WO2007067982A2/fr
Publication of WO2007067982A3 publication Critical patent/WO2007067982A3/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49506—Lead-frames or other flat leads characterised by the die pad an insulative substrate being used as a diepad, e.g. ceramic, plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H01L2924/13034—Silicon Controlled Rectifier [SCR]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Definitions

  • This invention relates to a semiconductor device, and more particularly, to a semiconductor package for protecting a semiconductor chip and connecting the semiconductor chip with an external device.
  • bond wires are typically made of gold or aluminum with a diameter of about 25- ⁇ m and are quite fragile.
  • bond wires have a large minimum radius of curvature at bends in the wire to avoid damage.
  • the bond wires dictate the dimensions of the MLP, whereas the MLP may have a smaller profile without the bond wires.
  • care must be taken when over-molding the encapsulation layer as the wires may break under stress from the molding resin. The molding stress may also deform the bond wires, potentially causing short circuits.
  • One method for avoiding the issues with wire bonding is to affix stud bumps to the features on top of the semiconductor chip.
  • the chip is then flipped over onto a leadframe, which includes conductors that connect the bumps with the leads.
  • a drawback of such "flip chip” MLPs is that the leadframe must be specifically designed for the semiconductor chip applied to it. Particularly, the conductors and the leads must account for the number and the pattern of bumps on the chip.
  • a change in the chip design, such as a higher density of features, may require a new leadframe design. Further, if different semiconductor chips are packaged on the same line, the specific leadframe for each chip must be carefully coordinated with the chips,
  • the invention comprises, in one form thereof, a flip chip molded leadless package (MLP) with electrical paths printed in conducting ink.
  • MLP includes a taped leadframe with a plurality of leads and a non-conducting tape placed thereon. The electrical paths are printed on the tape to connect the features of the MLP.
  • the MLP includes a pre-moided leadframe with the electrical paths printed directly thereon.
  • the present invention also provides a method of fabricating the semiconductor package according to each embodiment.
  • the invention includes a packaged semiconductor device comprising a leadframe having a plurality of electrically conductive leads; a die positioned on the leadframe, the die having a plurality of stud bumps; a plurality of electrical paths between the plurality of stud bumps and the plurality of leads, wherein the electrical paths comprise electrically conductive ink; and an over-molded, nonconducting polymer.
  • the non-conducting polymer is, for example, an encapsulating molding compound.
  • the leadframe comprises a pre-moided frame wherein the leads are embedded in a non-conducting polymer and the electrical paths are printed directly on the pre-moided leadframe.
  • the pre-moided leadframe may be integral with a plurality of additional leadframes during assembly.
  • the packaged semiconductor device comprises a non-conductive tape situated on the leadframe, the tape including an. edge proximate to each of the leads.
  • the electrical paths may then be printed on the non-conductive tape, in this embodiment, the leadframe is provided on a leadframe tape having a plurality of leadframes. Each of the electrical paths connects one stud bump to one lead and the electrical paths follow distinct courses.
  • the invention further includes a method for packaging a semiconductor device.
  • the method comprises the steps of providing a leadframe having a plurality of electrically conductive leads and an integrated circuit die having a plurality of electrically conductive stud bumps in a pattern on one side of the die; printing a plurality of electrical paths between the leads and a plurality of termini using an electrically conductive ink, wherein the termini are arranged according to the pattern of stud bumps; situating the die on the leadframe such that each of the stud bumps lines up with a terminus thereby connecting the stud bumps to the leads via the electrical paths; and molding the die and the leadfhame in a non-conducting polymer.
  • the non-conducting polymer is, for example, an encapsulating molding compound or an epoxy.
  • a non-conductive tape is positioned on the leadfrar ⁇ e and the electrical paths are subsequently printed on the tape.
  • the non- conductive tape positioning step may comprise a tape stamping process, wherein a punching die removes the non-conductive tape fiom a sheet and adheres the non- conductive tape to the leadframe.
  • non-conductive tape positioning step comprises a laser cutting process, wherein a non-conductive sheet is placed over the leadframe, a laser cutting tool cuts the non-conductive tape from the sheet, and the remainder of the sheet is removed.
  • the leadframe is pre-molded with a nonconducting polymer and the electrical paths are printed on the pre-molded leadframe.
  • the electrical paths may be printed using a stencil printing technique.
  • the semiconductor devices and leadframes may be provided In an array having a plurality of devices and leadframes; the leadframes are integrally connected.
  • the method further comprises the step of separating the packages from the array.
  • the stud bumps may be provided in a stacked configuration to increase the height of the stud bumps.
  • the method may include the further step of applying an adhesive to the stud bumps prior to the die situating step.
  • An advantage of the present invention is that the MLP does not include bond wires. Further, the MLP may be used for a new die by simply changing the printing of the conductive paths - the MLP doesn't need to be redesigned and the
  • Fig. 1 is a cross-sectional view of a semiconductor package according to a first embodiment of the present invention
  • Fig. 2 is an exploded view of the semiconductor package of Fig, 1;
  • Fig. 3A is a plan view of the Ieadframe and the non-conducting tape portions of the semiconductor package of Fig, 1 ;
  • Fig. 3B is a cross-sectional view of the Ieadframe and lhe non-conducting tape portions of the semiconductor package of Fig. 1 ;
  • Fig. 4A is a plan view of the Ieadframe and tape of Fig- 3 A with the addled electrical paths;
  • Fig. 4B is a cross-seclional view of the Ieadframe and tape of Fig. 3B with the added electrical paths;
  • Fig. 5 A is a plan view of the leadframe and tape of Fig.4A with the added die;
  • Fig. 5B is a cross-sectional view of the Ieadframe and tape of Fig. 4 ⁇ with the added die;
  • Figs. 6A - 6C show the steps in a tape stamping process for applying the nonconducting tape to the leadframe
  • Figs. 7A— 7C show the steps in a tape laser cutting process for applying the non-conducting tape to the Ieadframe
  • Fig. 8 is a cross-sectional view of a semiconductor package according to a second embodiment of the present invention.
  • Fig. 9 is an exploded view of the semiconductor package of Fig. 8.
  • Fig. ⁇ OA is a plan view of the leadframe of the semiconductor package of Fig. 8;
  • Fig. 1 OB is a cross-sectional view of the leadframe of the semiconductor package of Fig. 8;
  • Fig. 1 IA is a plan view of the leadframe of Fig. 1OA with the added electrical paths;
  • Fig. 1 IB is a cross-seclional view of the leadframe of Fig. 1OB with the added electrical paths;
  • Fig. 12A is a plan view of the leacLframe of Fig. 11 A with the added die; and
  • Fig. 12B is a cross-sectionai view of the leadframe of Fig. 1 IB with the added die.
  • the packaged semiconductor device of the present invention includes a die 302, a ⁇ eadframe 104 with non-conducting tape 106, and an encapsuJation material 108.
  • the die 102 is a semiconductor device with a plurality of conductive stud bumps 110 that provide electrical contacts for features on the semiconductor device.
  • the stud bumps 110 are arranged in a pattern unique to the design of the semiconductor device, the pattern depending on the number and location of the integrated circuit features.
  • the stud bumps 110 may be formed on metal pads (not shown) of the semiconductor chip 102 in a method similar to wire bonding.
  • the metal pads are electrically connected to unit elements (not shown) formed therebel ⁇ w.
  • the bumps and metal pads provide input and output terminals for connecting the chip 102 to other chips.
  • the internal structure of the semiconductor chip 102 may vary, and accordingly does not limit the scope of the present invention.
  • the semiconductor chip 102 may Include discrete power semiconductor devices (diodes, transistors, thyristors, IGBTs), linear devices, integrated circuits, and memory devices or various types of logic circuits.
  • the number of stud bumps 110 may depend on the number of metal pads, which may vary according to the integration density of the semiconductor chip 102. For example, as the integration density of the semiconductor chip 102 increases, the number of metal pads increase, and accordingly, the number of bumps 110 may increase.
  • the bumps 110 may include a conductive material, such as. copper or gold.
  • the bumps 110 may have any shape as long as it protrudes from the bottom surface of the semiconductor chip 102.
  • the stud bumps 110 arc at least 5- ⁇ ni large and may be less than several hundreds of ⁇ ra so as to achieve stable flip chip bonding.
  • the diameter of each of the bumps 1 10 may range from 10- ⁇ m to 200- ⁇ m.
  • the stud bumps 110 may be provided tn a single configuration, as shown in the figures, or a stacked configuration. Stacking the stud bumps 110, wherein two or more studs are formed on a single metal pad, increases the space under the flip chip 102, which may relieve stress on the chip.
  • the Ieadframe 104 is a taped Ieadframe provided in an array, though only the leadfrar ⁇ e for a single MLP is shown in the figures.
  • the Ieadframe 104 of the present embodiment has a rectangular shape, as shown by the plan view of Fig. 3A; however, a Ieadframe having any shape is considered to be within the scope of the invention.
  • the Ieadframe 104 includes a non-conducting backing 112, a die support 114, a lead support 1 16, and a plurality of leads 1 IS (shown in Fig. 3A).
  • the leads 1 18 are conductive members that may serve as terminals that are connected to an external device.
  • the number of leads 118 included on the leadframe 104 may depend on the number required by the design of the die 102, or a standard number of leads 1 18 is provided and oniy the number of leads required by the die 102 are utilized.
  • a trench between the die support 1 14 and the lead support 136 is filled by the encapsulation material 108 to electrically isolate the supports.
  • the non-conducting tape 106 covers the die support 114 and a portion of the lead support 116.
  • a plurality of electrically conductive paths 120 comprising an electrically conductive ink connects each of the stud bumps 110 to one of the Seads 1 18.
  • Each of the paths 120 is printed on the non-conducting tape 106 and includes an enlarged portion or terminus 122 (best shown in Fig. 4A) at the interface between the stud bump 1 10 and Lhe path 120 thereby connecting each of the semiconductor device features with a lead 118.
  • the encapsulation material 108 is a layer of non-conducting polymer molded over the die 102 and the leadframe 104 to protect the MLP 100 from external environments.
  • the encapsulation material 108 is, for example, an epoxy or an encapsulating molding compound (EMC),
  • the MLP 100 is assembled by positioning the non-conducting tape 106 on the die support 114 and the lead support 116 such that the edge of the tape 106 is proximate to or covering a portion of each of the leads 1 18 as shown in Figs 3 A and 3B.
  • the tape 106 is adhered to the leadframe 104.
  • the conductive paths 120 and the termini 122 are printed onto the tape 106 and the leads 118 using any suitable printing technique, such as stencil printing.
  • the conductive paths 120 and the termini 122 are printed such that each of the termini 122 lines up with one of the stud bumps 1 ] 0 and such that the conductive paths 120 do not cross each other.
  • the die 102 is situated on the non-conducting tape 106 such that each of the stud bumps 110 contacts a terminus 122 as shown by Figs. 5 A and 5B.
  • An adhesive may be applied to the stud bumps 110 prior to situating the die 102 onto the nonconducting tape 106 to retain the die 102 in position until the encapsulation layer 108 is over-molded and cured, ⁇ n a particular embodiment, the adhesive is applied by dipping the stud bumps 1 30 into the adhesive; however care must be taken to prevent the adhesive from contacting the surface of the die 102.
  • the stud bumps 110 having a stacked configuration simplify this process by increasing the space between the surface of the die 102 and the tip of the stud bumps 110.
  • a non-conducting polymer is over-molded onto the die 102 and leadframe 104 and cured to form the encapsulation layer 108, resulting in the MLP 100 shown in Fig. 1.
  • the MLP 100 is removed from the array by sawing or another suitable cutting method, thereby exposing the leads 118.
  • the MLP 100 then proceeds to typical end-of-line processing such as final testing.
  • the non-conducting tape 106 may be applied to the leadframe 104 by a number of methods, such as, for example, by a stamping process.
  • a stamping process In the tape stamping process, a sheet of the non-conducting tape 106 is run over the array of leadframes.
  • the leadframes 104 are aligned with a plurality of punching dies 124 that, in a downward motion, punch out portions of the tape 106 and contact them with the leadframes 104, as shown in Figs. 5A- 5C.
  • An adhesive on the underside of the tape 106 adheres the tape 106 to the leadframes 104, resulting in the leadframe and tape assembly shown in Figs. 3 A and 3B.
  • the tape 106 is applied using a laser cutting process.
  • a sheet of the non-conducting tape 106 is applied to the array of leadframes and portions of the tape 106 are cut using a laser or other tool as shown for a single leadframe 104 in Figures 7A and 7B.
  • the unwanted tape is removed leaving the non-conducting tape 106 on the leadframe 104, as shown in Figure 7C.
  • the MLP includes a pre- moided ieadframe.
  • the MLP 200 comprises a die 202, a pre-molded leadfranie 204, and an encapsulation material 208.
  • the die 202 is a semiconductor device with a plurality of conductive stud bumps 210 that provide electrical contacts for features on the semiconductor device.
  • the non-conducting backing 212 and the leads 218 (shown in Fig. 1 OA) of the pre-molded leadframe 204 are molded with a non-conducting polymer such as an epoxy or an EMC to form a uniform surface onto which the conducting paths 220 may be printed. Thus, no non-conducting tape is needed for this embodiment.
  • the pre-molded leadframe 204 is provided in an array, though only the leadframe for a single MLP is shown in the figures.
  • the pre-molded leadframe 204 of the present embodiment has a rectangular shape, as shown by the plan view of Fig, 3A; however, a leadframe having any shape is considered to be within the scope of the invention.
  • the leads 218 are conductive members that may serve as terminals that are connected to an external device.
  • the number of leads 218 included o « the pre-mulded leadframe 204 may depend on the number required by the design of the die 202, or a standard number of leads 218 is provided and only the number of leads required by the die 202 are utilized.
  • a plurality of electrically conductive paths 220 comprising an electrically conductive ink connects each of the stud bumps 210 to one of the leads 218.
  • Each of the paths 220 is printed on the pre-molded leadframe 204 and includes an enlarged portion or terminus 222 (best shown in Fig, 1 IA) at the interface between the stud bump 210 and the path 220 thereby connecting each of the semiconductor device features with a lead 238.
  • the encapsulation material 208 is a layer of non-conducting polymer molded over the die 202 and the pre-molded leadframe 204 to protect the MLP 200 from external environments.
  • the encapsulation material 208 is, for example, an epoxy or an EMC.
  • the MLP 200 is assembled by molding the pre-molded leadfxame 204 such that the top surfaces of the leads 218 are exposed as shown in Figs 1OA and 1OB.
  • the conductive paths 220 and the termini 222 are printed onto the pre-molded leadframe 204 and the ieads 218 using any suitable printing technique, such as stencil printing.
  • the conductive paths 220 and the termini 222 are printed such that each of the termini 222 lines up with one of the stud bumps 210 and such that the conductive paths 220 do not cross each other.
  • the die 202 is situated on the pre-molded ieadf ⁇ ame 204 such that each of the stud bumps 210 contacts a terminus 222 as shown by Figs. 12A and 12B.
  • An adhesive may be applied to the stud bumps 210 prior to situating the die 202 onto the pre-molded leadframe 204 to retain the die 202 in position until the encapsulation layer 208 is over-molded and cured.
  • a non-conducting polymer is over-molded onto the die 202 and pre-molded leadframe 204 and cured to form the encapsulation layer 208, resulting in the MLP 200 shown in Fig. 8.
  • the MLP 200 is removed from the array by sawing or another suitable cutting method, thereby exposing the ieads 218.
  • the MLP 200 then proceeds to typical end-of-line processing such as final testing. "
  • MLP 100 molded leadless package

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

L’invention concerne un ensemble sans fil moulé (MLP) pour puce retournée avec des chemins électriques imprimés à l'encre conductrice. Le MLP comprend une grille de connexion scellée comportant une pluralité de fils et une bande non conductrice. Les chemins électriques sont imprimés sur la bande pour connecter les éléments du dispositif semi-conducteur aux fils et une couche d’encapsulation protège l’ensemble. Dans un second mode de réalisation, le MLP comprend une grille de connexion pré-moulée sur laquelle les chemins électriques sont directement imprimés. La présente invention concerne également un procédé de fabrication de l’ensemble semi-conducteur selon chaque mode de réalisation.
PCT/US2006/061799 2005-12-08 2006-12-08 Mlp pour puce retournée avec encre conductrice WO2007067982A2 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN2006800459980A CN101385134B (zh) 2005-12-08 2006-12-08 具有导电油墨的倒装芯片模制无引线封装
KR1020117029367A KR101363463B1 (ko) 2005-12-08 2006-12-08 도전성 잉크를 가진 플립 칩 ｍｌｐ
KR1020087013404A KR101135828B1 (ko) 2005-12-08 2006-12-08 도전성 잉크를 가진 플립 칩 ｍｌｐ

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US74843505P 2005-12-08 2005-12-08
US60/748,435 2005-12-08
US11/364,014 US7638861B2 (en) 2005-12-08 2006-02-28 Flip chip MLP with conductive ink
US11/364,014 2006-02-28

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CN101385134B (zh) 2011-04-06
KR101363463B1 (ko) 2014-02-14
KR20080075142A (ko) 2008-08-14
KR101135828B1 (ko) 2012-04-16
KR20110137405A (ko) 2011-12-22
WO2007067982A3 (fr) 2008-07-24
CN101385134A (zh) 2009-03-11

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