EP1614155A2 - Structure d'essai permettant de controler electriquement la profondeur de gravures de tranchees d'isolation dans une tranche soi et procedes de mise en oeuvre associes - Google Patents

Structure d'essai permettant de controler electriquement la profondeur de gravures de tranchees d'isolation dans une tranche soi et procedes de mise en oeuvre associes

Info

Publication number
EP1614155A2
EP1614155A2 EP04728158A EP04728158A EP1614155A2 EP 1614155 A2 EP1614155 A2 EP 1614155A2 EP 04728158 A EP04728158 A EP 04728158A EP 04728158 A EP04728158 A EP 04728158A EP 1614155 A2 EP1614155 A2 EP 1614155A2
Authority
EP
European Patent Office
Prior art keywords
trench
etching
island
islands
width
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP04728158A
Other languages
German (de)
English (en)
Inventor
Ralf Lerner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
X Fab Semiconductor Foundries GmbH
Original Assignee
X Fab Semiconductor Foundries GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE2003117748 external-priority patent/DE10317748B4/de
Application filed by X Fab Semiconductor Foundries GmbH filed Critical X Fab Semiconductor Foundries GmbH
Publication of EP1614155A2 publication Critical patent/EP1614155A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line

Definitions

  • the invention relates to a test structure (claim 1) or to methods for checking trench etching (trench etching) in SOI wafers (claim 2, 3 or 10).
  • trench isolation In order to integrate logic elements at the low voltage level and high voltage power elements in one and the same silicon circuit, it is necessary to isolate chip areas with significantly different potentials from one another.
  • One option is dielectric isolation using etched and refilled trenches (trench isolation).
  • a vertically acting insulation between component and substrate is realized by a buried (horizontal) insulating layer (usually a silicon dioxide, but also other insulating layers in essence). Lateral-acting insulation is achieved by etching a trench up to the buried insulating layer and then refilling the deep trench with insulating layers or with an insulating layer (insulating trench).
  • planarization step e.g. A suitable etching process or chemical mechanical polishing (CMP) will level the surface, cf. the illustration in FIG. 3 (prior art).
  • Too long etching in turn causes an etching attack on the lower side walls of the etched trenches due to backscattering of the etching ions and must be avoided if possible.
  • the etching time should not be made excessively long.
  • the aim of this is to increase the technological security when etching these trenches, to avoid rejects and to save costs.
  • the invention is intended to make it possible to easily check the depth of trenches achieved in an etching process on a test structure without having to measure the exact depth.
  • the task is solved with a test structure.
  • a series of contiguous islands is constructed so that each is surrounded by a trench after the etching.
  • the trench has different widths, varying in steps from island to island, including a width that occurs in the active circuit.
  • Part of the surrounding trench of each island forms a common piece with the trench of the neighboring island. This part (or this section) has a
  • the respective common section of the trenches of the respective (downward) neighboring island has the width dimension of the next narrower trench.
  • Section of the trenches of the respective (upwards) neighboring island has the width dimension of the next wider trench.
  • a mixture of different widths along the row of trenches can also be specified via the mask (can be prepared using a mask).
  • the etching rate depends to a certain extent on the width of the trenches to be etched.
  • the wider the trench the better the exchange of the etching species takes place and the greater the etching rate.
  • the wider trenches become already etched through (to the buried insulating layer), while the narrower trenches or narrow trenches have not yet been completely etched down to the buried oxide layer.
  • a sufficiently deep etching can be checked and checked by an electrical measurement between two neighboring islands across the common (between them) isolation trench.
  • the measurement of "electrical continuity" can extend to conductivity, resistance, or the resulting current at a fixed voltage or the resulting voltage at a fixed current. All are a technical type of electrical outlet.
  • the conductivity or resistance is measured successively between the individual islands, e.g. starting with the island of the narrowest trench and / or between each island and the surrounding area of the semiconductor wafer. This makes it possible to determine which of the isolation trenches have already been etched through (apart from the buried isolation layer) and which have not.
  • Such a test structure can be used to check that the etching is sufficiently deep (all trenches that are wider than the trench of the active circuit, which is designated as the reference trench) and also the reference trench itself is etched through on the insulating layer. The remaining trenches of the test structure, those with smaller widths than the reference trench, have not been etched through, i.e. they have not yet reached the buried insulating layer.
  • Figure 1a shows a test structure schematically in plan view.
  • Figure 1 b is a sectional view of the test structure of Figure 1 a, wherein isolation trenches have already been introduced after a certain etching time.
  • FIG. 2 illustrates the electrical measurement from island to island via an enlarged test trench, which has not yet been etched through and has an aspect ratio of z / y (width to depth).
  • Figure 3 is a trench in an active circuit on the SOI.
  • FIG. 1 shows a top view and a sectional view of a series of contiguous, square island areas A to E.
  • the borders of the island areas characterize the isolation trenches 16 to 20 which have different widths after the etching.
  • the trench widths a to e between the individual islands increase from island A to island E too. This also increases the etching rate according to the width of the trenches formed.
  • the etching rate as ⁇ y / ⁇ t is specified via the opening width z of a mask.
  • An insulating layer 1 is designed, for example, as silicon dioxide and carries the active semiconductor layer 2. This semiconductor can be silicon, for example.
  • a carrier substrate under the insulating layer 1 is indicated by dots.
  • the insulating layer is then a BOX layer (Buried Oxide).
  • Figure 3 is a symbolic reference.
  • the remaining disk area surrounding the trenches or the islands is designated by S.
  • the width of the trenches 16 to 21 is numbered a to e in the sectional illustration in FIG. 1b, e larger than a.
  • FIG. 3 A section of an already filled insulating trench in a carrier substrate, as a “handle wafer”, is shown in FIG. 3. This structure is known as such and is only intended here are therefore explained to illustrate an example of the reference trench or the width or the depth of the reference trench of the active circuit resulting therefrom during the etching.
  • the handle wafer has a carrier substrate 3, a buried insulating layer 1 as a box, which can be silicon dioxide, for example, and an active silicon layer 2.
  • the active layer is often also called “device wafer” or component wafer.
  • a trench structure 8 is used as an insulating trench (Trench) with two insulating layers 4 provided laterally on the left and right and an original width d for insulation
  • the left and right fields 6 and 7, which are both active silicon regions and can be at different potentials, are isolated, according to the high voltage of a power component
  • the vertical insulation takes over the box, the horizontal insulation takes over the two insulating layers 4. They are filled with a possibly conductive filling layer 5 and extend to the BOX layer.
  • the surface of the component is leveled by a removal process or polishing process, that is to say planarized.
  • the depth of the trench structure which has a width d and has not yet been provided with insulation layers 4 and filler layer 5, is lowered to the BOX, so that the horizontal insulation then interacts with the vertical insulation (the box layer 1) via the insulation layers 4 then introduced and together achieve horizontal-vertical isolation. Regions 6 and 7 are completely electrically isolated from one another. The insulation is measured by the dielectric strength (thickness and structure) of the insulating layers 4 and 1.
  • test structure according to FIG. 1a in plan view allows the isolation trench etching of, for example, the described trench structure 8 according to FIG. 3 to be checked. It is arranged at a different location on the SOI pane.
  • FIG. 1 a can define the mask openings, which then lead to etching depths which look after a predetermined etching time in the “device wafer” as the cross section according to FIG. 1 b shows. This is the preparation of the test structure created during the isolation trench etching ,
  • etching depths Two etching depths are to be described here, which can be recognized from the heights h16 and h2.
  • the thickness of the device disk h2 is in the trenches 19, 20 and 21 to Box layer 1 reduced. This etching depth is therefore h2.
  • the etching depth in the narrower trench 16, which surrounds the island A, is only small as h2-h16. There remains a bottom web h16 of the device disc, just as in the case of the trenches 17 and 18 of width b and c, which are each wider in stages.
  • the connected series of islands A to E are assigned to each other and each separated by a trench. They are related in the sense that they belong together functionally, but each island is of course separated from the other island by at least one ditch section.
  • a square trench surrounds one island and a section of this trench of one island and another section of the next trench of the next island are common.
  • the common section of the trench can have a width which either corresponds to the width of the wider trench or to the width of the narrower trench.
  • the width of the respective trench in FIG. 1a increases from left to right.
  • the common section between two neighboring islands is dimensioned here so that the wider trench separates the neighboring islands, so the trench width b separates the islands A and B, although island A only the trench width a in the remaining area as a separation from the rest Disk area S owns.
  • This disk area S thus surrounds the island A on three sides, the island B only on two sides. Both are at least partially surrounding each island with respect to the disk area S.
  • the widest trench width "e" is already achieved between the islands D and E, so that the right trench section with the reference number z (generally for the width of the trench) is no longer wider than the left trench section e between the islands D and E.
  • the width increases in stages from left to right from island to island.
  • a section of the trench surrounding each island has the described common piece with the trench that surrounds the neighboring island.
  • This respective piece has a width which corresponds to the width of the trench of the (right) neighboring island, viewed from left to right in FIG. 1a. Viewing and executing from right to left is also possible.
  • the trench between the islands D and E has the smaller width, namely the width "d", which has the trench that surrounds the island D.
  • the trench section between islands A and B is of width a, not of width b.
  • the trench width in the common trench section is therefore determined by one or the adjacent trench width.
  • One of the widths a to e corresponds at least essentially to a trench width of the active circuit, here in the example the trench width d of the (still unfilled, not laterally isolated) trench structure 8 from FIG. 3.
  • the trench thus obtained is the trench 19, which likewise has the width d , If it is etched down onto the oxide layer 1 in the etching process, this also corresponds to a correct etching depth in the active circuit between the islands 6, 7 to be isolated in the active “device wafer”.
  • the test structure according to FIG. 1a after the etching process according to FIG. 1b, is used. It is applied to the process disk and the electrical resistance can be measured between two neighboring islands in accordance with FIG. 2 in order to obtain an assessment of the sufficient or sufficient depth of the etched insulating trench with the size of the amounts (the measured values) get the active "device wafer".
  • Figure 2 illustrates two electrodes, which are symbolically placed on two island areas. These two islands are adjacent and separated by a ditch. It can be any ditch of Figure 1a and any pair of islands that are adjacent. The resistance between the two islands is measured via the electrodes. The electrical transmission as either current, resistance or conductance, or the transmission behavior with an impressed constant current and measured voltage between the electrodes gives measured values. These measured values are based on the remaining thickness of the “device wafer” under the already etched trench of the depth y.
  • Y is a function of time, y (t), the speed at which the depth of the trench is etched is a function of that Width z
  • the resulting measured values of the passage for example the resistance, show which trench has already been lowered down to the oxide layer would result in a very high resistance when measuring between islands C and D, while the measurement between islands A and B, that is to say via the remaining web under the trench 17, would result in a significantly lower resistance value in the electrical measurement.
  • the electrical measurement takes place successively, i.e. for all neighboring island pairs, not necessarily one after the other, only not simultaneously for all neighboring islands.
  • the measurement of one island to the substrate surface, which surrounds these islands at least on two or three sides can also be carried out.
  • the measurement can be carried out after an etching has been carried out, in order to obtain conclusions about the period of etching used and the result achieved, by electrical measurement of the test structure.
  • the etching can also be interrupted in sections to enable a measurement and to check the progress of the etching. Both lead to the fact that the isolation trench etching has been checked and that it has been ensured that the etching through has been achieved, but that the time required has not been too long.
  • a subsequent measurement of trench depths in the active area is also achieved via the test structure.
  • all contiguous island areas A to E are delimited from the outside to the disk area S, which corresponds at least to the width e of the widest trench.
  • each island is electrically separated from the remaining disk area S at an early stage, so that only the common sections between the respective islands, that is to say the widths a to e, are available for the control measurement.
  • a frame-like delimitation of the individual islands from the pane area is achieved at an early stage by rapidly etching down the widest trench, and then successively etching down the other, gradually narrowing trench sections between the individual islands.
  • the tests for the relevant trench depth are carried out non-destructively, only by electrical measurement and after the trench structure has been formed, no further mechanical work steps are necessary which interfere with the pane and the manufacturing process of the pane.
  • the accuracy of the resistance measurement is also not important, since the dimension of the trench and the remaining web are not to be measured, but only require an interpretation that could correspond to a threshold value.
  • a very high and characteristic resistance which stands for an isolation trench etched through to the oxide layer, is to be distinguished from a low resistance, which results with remaining webs. It's quick and easy to determine.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Automation & Control Theory (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

L'objectif de l'invention est de créer un procédé permettant de détecter à quel moment la couche isolante enfouie est atteinte lors de la gravure de tranchées d'isolation, ce procédé devant être sûr et facile à mettre en oeuvre. Par ailleurs, la sécurité technologique lors de la gravure des tranchées doit être accrue, les rebuts doivent être évités et les coûts réduits. Cet objectif est atteint grâce à une structure d'essai servant à contrôler la gravure de tranchées d'isolation dans une tranche de silicium sur isolant (SOI). Cette structure d'essai présente à l'issue de la gravure de tranchées d'isolation une série d'îlots contigus, chaque îlot étant entouré par une tranchée présentant d'un îlot à l'autre (A, B ; B, C) une largeur différente, notamment une largeur de tranchée constituant une tranchée d'isolation dans un circuit actif. Une partie de la tranchée (a, b) entourant chaque îlot (A, B) est commune à la tranchée de l'îlot voisin. Cette partie commune possède au niveau des îlots intérieurs la largeur de la tranchée voisine de dimension immédiatement supérieure ou immédiatement inférieure dans la série.
EP04728158A 2003-04-17 2004-04-19 Structure d'essai permettant de controler electriquement la profondeur de gravures de tranchees d'isolation dans une tranche soi et procedes de mise en oeuvre associes Withdrawn EP1614155A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE2003117748 DE10317748B4 (de) 2003-04-17 2003-04-17 Verfahren zur Überprüfung von Isoliergrabenätzungen in SOI-Scheiben mittels einer Teststruktur
PCT/DE2004/000815 WO2004095570A2 (fr) 2003-04-17 2004-04-19 Structure d'essai permettant de controler electriquement la profondeur de gravures de tranchees d'isolation dans une tranche soi et procedes de mise en oeuvre associes

Publications (1)

Publication Number Publication Date
EP1614155A2 true EP1614155A2 (fr) 2006-01-11

Family

ID=33311746

Family Applications (1)

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EP04728158A Withdrawn EP1614155A2 (fr) 2003-04-17 2004-04-19 Structure d'essai permettant de controler electriquement la profondeur de gravures de tranchees d'isolation dans une tranche soi et procedes de mise en oeuvre associes

Country Status (3)

Country Link
US (1) US7588948B2 (fr)
EP (1) EP1614155A2 (fr)
WO (1) WO2004095570A2 (fr)

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US7253650B2 (en) * 2004-05-25 2007-08-07 International Business Machines Corporation Increase productivity at wafer test using probe retest data analysis
US7301210B2 (en) * 2006-01-12 2007-11-27 International Business Machines Corporation Method and structure to process thick and thin fins and variable fin to fin spacing
JP5034662B2 (ja) * 2006-06-20 2012-09-26 ソニー株式会社 面発光型半導体レーザおよびその製造方法
DE102007063229B4 (de) * 2007-12-31 2013-01-24 Advanced Micro Devices, Inc. Verfahren und Teststruktur zur Überwachung von Prozesseigenschaften für die Herstellung eingebetteter Halbleiterlegierungen in Drain/Source-Gebieten
US8232115B2 (en) 2009-09-25 2012-07-31 International Business Machines Corporation Test structure for determination of TSV depth
CN104118845B (zh) * 2014-07-17 2016-02-03 华中科技大学 一种在soi硅片上制备微机械悬空结构的方法
RU175042U1 (ru) * 2017-06-20 2017-11-16 Закрытое акционерное общество "ГРУППА КРЕМНИЙ ЭЛ" Тестовый элемент для контроля качества анизотропного травления канавок
RU2686579C1 (ru) * 2018-08-16 2019-04-29 Федеральное государственное бюджетное учреждение науки Институт радиотехники и электроники им. В.А. Котельникова Российской академии наук Способ определения параметров плазменного травления пластин

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Also Published As

Publication number Publication date
US7588948B2 (en) 2009-09-15
WO2004095570A3 (fr) 2005-01-06
US20070054422A1 (en) 2007-03-08
WO2004095570A2 (fr) 2004-11-04

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