EP1614155A2

EP1614155A2 - Test structure for electrically verifying the depths of trench-etchings in an soi wafer, and associated working methods

Info

Publication number: EP1614155A2
Application number: EP04728158A
Authority: EP
Inventors: Ralf Lerner
Original assignee: X Fab Semiconductor Foundries GmbH
Current assignee: X Fab Semiconductor Foundries GmbH
Priority date: 2003-04-17
Filing date: 2004-04-19
Publication date: 2006-01-11
Also published as: US7588948B2; WO2004095570A2; US20070054422A1; WO2004095570A3

Abstract

The aim of the invention is to discover a simple to implement and reliable recognition of the moment at which insulating trenches reach the buried insulating layer during an etching operation. The technological reliability during the etching of these trenches should be increased, the production of refuse should be prevented, and costs should be reduced. To these ends, the invention provides a test structure for verifying an insulating trench etching in an SOI wafer. After an etching of insulating trenches, this test structure has a row of connected islands, whereby each island is surrounded by a trench. This trench has a different width from island to island (A, B; B, C) while including a trench width that appears in the form of an insulating trench in an active circuit. A section of the surrounding trench (a, b) of each island (A, B) forms a common piece with the trench of adjacent islands. The respective section has, in the inner islands, the width of the adjacent trench having the next larger or next smaller measure of width in the row.

Description

Test structure for the electrical checking of the depths of trench etchings in an SOI wafer and associated working methods

The invention relates to a test structure (claim 1) or to methods for checking trench etching (trench etching) in SOI wafers (claim 2, 3 or 10).

In order to integrate logic elements at the low voltage level and high voltage power elements in one and the same silicon circuit, it is necessary to isolate chip areas with significantly different potentials from one another. One option is dielectric isolation using etched and refilled trenches (trench isolation). A vertically acting insulation between component and substrate is realized by a buried (horizontal) insulating layer (usually a silicon dioxide, but also other insulating layers in essence). Lateral-acting insulation is achieved by etching a trench up to the buried insulating layer and then refilling the deep trench with insulating layers or with an insulating layer (insulating trench).

However, only a part of the etched trench can be filled with the insulating material. The remaining part is then filled up with a conductive filler layer, e.g. Polysilicon. Through a subsequent planarization, a so-called planarization step, e.g. A suitable etching process or chemical mechanical polishing (CMP) will level the surface, cf. the illustration in FIG. 3 (prior art).

Various problems exist in the prior art regarding the depth of the etched trenches. In order to achieve the electrical insulation in the lateral direction, ie from an insulating island to an adjacent insulated island, it is necessary to ensure that the insulating trench reaches through to the buried oxide. A conventional method in the prior art reaches its physical limits. Endpoint detection based on the etched composition of the etching plasma (oxygen ions are present in the etching plasma when the buried oxide layer is reached) fails if the proportion of the areas to be etched becomes small. Optical methods are becoming increasingly difficult when the aspect ratio, ie the ratio of width to depth, becomes too small, that is to say with narrow, deep trenches.

Too long etching in turn causes an etching attack on the lower side walls of the etched trenches due to backscattering of the etching ions and must be avoided if possible.

In addition, in order to achieve the highest possible system throughput when manufacturing SOI wafers with integrated logic elements and power elements, the etching time should not be made excessively long.

It is an object of the invention to provide an easy-to-use and safe method for recognizing the time at which the insulating trenches are etched through onto the buried insulating layer. The aim of this is to increase the technological security when etching these trenches, to avoid rejects and to save costs. Alternatively, the invention is intended to make it possible to easily check the depth of trenches achieved in an etching process on a test structure without having to measure the exact depth.

According to the invention, the task is solved with a test structure. A series of contiguous islands is constructed so that each is surrounded by a trench after the etching. The trench has different widths, varying in steps from island to island, including a width that occurs in the active circuit. Part of the surrounding trench of each island forms a common piece with the trench of the neighboring island. This part (or this section) has a | ϊβlf &? Fc width, namely that of the trench with the next wider or next narrower dimension in the row.

The respective common section of the trenches of the respective (downward) neighboring island has the width dimension of the next narrower trench. The common one

Section of the trenches of the respective (upwards) neighboring island has the width dimension of the next wider trench. A mixture of different widths along the row of trenches can also be specified via the mask (can be prepared using a mask).

Under most boundary conditions, the etching rate depends to a certain extent on the width of the trenches to be etched. The wider the trench, the better the exchange of the etching species takes place and the greater the etching rate. With a suitable process control or a suitable layout of the widths, the wider trenches become already etched through (to the buried insulating layer), while the narrower trenches or narrow trenches have not yet been completely etched down to the buried oxide layer.

A sufficiently deep etching can be checked and checked by an electrical measurement between two neighboring islands across the common (between them) isolation trench. The measurement of "electrical continuity" can extend to conductivity, resistance, or the resulting current at a fixed voltage or the resulting voltage at a fixed current. All are a technical type of electrical outlet.

If the depth of the etching process is still insufficient, i.e. then, if the insulating trench in question does not yet reach down to the buried insulating layer, a current flow or resistance which is orders of magnitude higher can be determined than with an already sufficient depth of the etched trench when the buried insulating layer is reached.

The conductivity or resistance is measured successively between the individual islands, e.g. starting with the island of the narrowest trench and / or between each island and the surrounding area of the semiconductor wafer. This makes it possible to determine which of the isolation trenches have already been etched through (apart from the buried isolation layer) and which have not.

Such a test structure can be used to check that the etching is sufficiently deep (all trenches that are wider than the trench of the active circuit, which is designated as the reference trench) and also the reference trench itself is etched through on the insulating layer. The remaining trenches of the test structure, those with smaller widths than the reference trench, have not been etched through, i.e. they have not yet reached the buried insulating layer.

In this way, unnecessarily long etching times are avoided. This would be the case if the trenches which are narrower than the reference trench are also etched through. The invention is explained and supplemented using an exemplary embodiment.

Figure 1a shows a test structure schematically in plan view.

Figure 1 b is a sectional view of the test structure of Figure 1 a, wherein isolation trenches have already been introduced after a certain etching time.

FIG. 2 illustrates the electrical measurement from island to island via an enlarged test trench, which has not yet been etched through and has an aspect ratio of z / y (width to depth).

Figure 3 is a trench in an active circuit on the SOI.

1 shows a top view and a sectional view of a series of contiguous, square island areas A to E. The borders of the island areas characterize the isolation trenches 16 to 20 which have different widths after the etching. The trench widths a to e between the individual islands increase from island A to island E too. This also increases the etching rate according to the width of the trenches formed. The etching rate as Δy / Δt is specified via the opening width z of a mask.

An insulating layer 1 is designed, for example, as silicon dioxide and carries the active semiconductor layer 2. This semiconductor can be silicon, for example. A carrier substrate under the insulating layer 1 is indicated by dots. The insulating layer is then a BOX layer (Buried Oxide). Figure 3 is a symbolic reference.

All islands A to E are surrounded by ditches. Each trench has a different width and the width of the trenches a to e, represented generally by z, grows from left to right in FIGS. 1a, 1b, z = a to e, where e> d, d> c, c> b , etc. (from right to left).

The remaining disk area surrounding the trenches or the islands is designated by S.

The width of the trenches 16 to 21 is numbered a to e in the sectional illustration in FIG. 1b, e larger than a.

A section of an already filled insulating trench in a carrier substrate, as a “handle wafer”, is shown in FIG. 3. This structure is known as such and is only intended here are therefore explained to illustrate an example of the reference trench or the width or the depth of the reference trench of the active circuit resulting therefrom during the etching.

The handle wafer has a carrier substrate 3, a buried insulating layer 1 as a box, which can be silicon dioxide, for example, and an active silicon layer 2. The active layer is often also called “device wafer” or component wafer. In this component wafer, a trench structure 8 is used as an insulating trench (Trench) with two insulating layers 4 provided laterally on the left and right and an original width d for insulation The left and right fields 6 and 7, which are both active silicon regions and can be at different potentials, are isolated, according to the high voltage of a power component The vertical insulation takes over the box, the horizontal insulation takes over the two insulating layers 4. They are filled with a possibly conductive filling layer 5 and extend to the BOX layer.

The surface of the component is leveled by a removal process or polishing process, that is to say planarized.

The depth of the trench structure, which has a width d and has not yet been provided with insulation layers 4 and filler layer 5, is lowered to the BOX, so that the horizontal insulation then interacts with the vertical insulation (the box layer 1) via the insulation layers 4 then introduced and together achieve horizontal-vertical isolation. Regions 6 and 7 are completely electrically isolated from one another. The insulation is measured by the dielectric strength (thickness and structure) of the insulating layers 4 and 1.

The test structure according to FIG. 1a in plan view allows the isolation trench etching of, for example, the described trench structure 8 according to FIG. 3 to be checked. It is arranged at a different location on the SOI pane.

In the not yet etched state, FIG. 1 a can define the mask openings, which then lead to etching depths which look after a predetermined etching time in the “device wafer” as the cross section according to FIG. 1 b shows. This is the preparation of the test structure created during the isolation trench etching ,

Two etching depths are to be described here, which can be recognized from the heights h16 and h2. The thickness of the device disk h2 is in the trenches 19, 20 and 21 to Box layer 1 reduced. This etching depth is therefore h2. The etching depth in the narrower trench 16, which surrounds the island A, is only small as h2-h16. There remains a bottom web h16 of the device disc, just as in the case of the trenches 17 and 18 of width b and c, which are each wider in stages.

The connected series of islands A to E are assigned to each other and each separated by a trench. They are related in the sense that they belong together functionally, but each island is of course separated from the other island by at least one ditch section. In the case of square islands, a square trench surrounds one island and a section of this trench of one island and another section of the next trench of the next island are common.

After each island is surrounded by a trench of different widths, the common section of the trench can have a width which either corresponds to the width of the wider trench or to the width of the narrower trench. The width of the respective trench in FIG. 1a increases from left to right. The common section between two neighboring islands is dimensioned here so that the wider trench separates the neighboring islands, so the trench width b separates the islands A and B, although island A only the trench width a in the remaining area as a separation from the rest Disk area S owns. This disk area S thus surrounds the island A on three sides, the island B only on two sides. Both are at least partially surrounding each island with respect to the disk area S.

It can be seen that the widest trench width "e" is already achieved between the islands D and E, so that the right trench section with the reference number z (generally for the width of the trench) is no longer wider than the left trench section e between the islands D and E.

The width increases in stages from left to right from island to island. A section of the trench surrounding each island has the described common piece with the trench that surrounds the neighboring island. This respective piece has a width which corresponds to the width of the trench of the (right) neighboring island, viewed from left to right in FIG. 1a. Viewing and executing from right to left is also possible. Then the trench between the islands D and E has the smaller width, namely the width "d", which has the trench that surrounds the island D. Then the trench section between islands A and B is of width a, not of width b. For the inner islands B to D, which are not at the end of the row (islands A and E), the trench width in the common trench section is therefore determined by one or the adjacent trench width.

One of the widths a to e corresponds at least essentially to a trench width of the active circuit, here in the example the trench width d of the (still unfilled, not laterally isolated) trench structure 8 from FIG. 3. The trench thus obtained is the trench 19, which likewise has the width d , If it is etched down onto the oxide layer 1 in the etching process, this also corresponds to a correct etching depth in the active circuit between the islands 6, 7 to be isolated in the active “device wafer”.

In a method for checking the trench etching, the test structure according to FIG. 1a, after the etching process according to FIG. 1b, is used. It is applied to the process disk and the electrical resistance can be measured between two neighboring islands in accordance with FIG. 2 in order to obtain an assessment of the sufficient or sufficient depth of the etched insulating trench with the size of the amounts (the measured values) get the active "device wafer".

Figure 2 illustrates two electrodes, which are symbolically placed on two island areas. These two islands are adjacent and separated by a ditch. It can be any ditch of Figure 1a and any pair of islands that are adjacent. The resistance between the two islands is measured via the electrodes. The electrical transmission as either current, resistance or conductance, or the transmission behavior with an impressed constant current and measured voltage between the electrodes gives measured values. These measured values are based on the remaining thickness of the “device wafer” under the already etched trench of the depth y. Y is a function of time, y (t), the speed at which the depth of the trench is etched is a function of that Width z The depth of the trench y is thus a function of x as y = y (z) The resulting measured values of the passage, for example the resistance, show which trench has already been lowered down to the oxide layer would result in a very high resistance when measuring between islands C and D, while the measurement between islands A and B, that is to say via the remaining web under the trench 17, would result in a significantly lower resistance value in the electrical measurement. The electrical measurement takes place successively, i.e. for all neighboring island pairs, not necessarily one after the other, only not simultaneously for all neighboring islands.

Instead of the measurement between two neighboring islands, the measurement of one island to the substrate surface, which surrounds these islands at least on two or three sides, can also be carried out.

The measurement can be carried out after an etching has been carried out, in order to obtain conclusions about the period of etching used and the result achieved, by electrical measurement of the test structure. However, the etching can also be interrupted in sections to enable a measurement and to check the progress of the etching. Both lead to the fact that the isolation trench etching has been checked and that it has been ensured that the etching through has been achieved, but that the time required has not been too long. A subsequent measurement of trench depths in the active area is also achieved via the test structure.

In an alternative test structure, which is not shown separately, all contiguous island areas A to E are delimited from the outside to the disk area S, which corresponds at least to the width e of the widest trench. This means that each island is electrically separated from the remaining disk area S at an early stage, so that only the common sections between the respective islands, that is to say the widths a to e, are available for the control measurement. In the course of the etching or the process section of the etching, a frame-like delimitation of the individual islands from the pane area is achieved at an early stage by rapidly etching down the widest trench, and then successively etching down the other, gradually narrowing trench sections between the individual islands.

The shown coordination (assignment) of the trench width of the trench 19, which essentially corresponds to the width of the trench structure 8 (without insulation layer 5 and filler layer 4) of FIG. 3, lies essentially in the central position of all trench widths of FIG. 1a.

The tests for the relevant trench depth are carried out non-destructively, only by electrical measurement and after the trench structure has been formed, no further mechanical work steps are necessary which interfere with the pane and the manufacturing process of the pane. With regard to the electrical measurement, the accuracy of the resistance measurement is also not important, since the dimension of the trench and the remaining web are not to be measured, but only require an interpretation that could correspond to a threshold value. A very high and characteristic resistance, which stands for an isolation trench etched through to the oxide layer, is to be distinguished from a low resistance, which results with remaining webs. It's quick and easy to determine.

Claims

Expectations:

1. Test structure for checking an isolation trench etching in an SOI pane, the test structure having a series of contiguous islands after the etching of isolation trenches, each island being surrounded by a trench, which trench from island to island (A, B; B , C) of (stepwise) increasing width, including a trench width, which occurs in an active circuit as an isolation trench; a portion of the surrounding trench (a, b) of each island (A, B) forming a common piece with the trench of the neighboring island; the respective section - with the exception of the island with the widest (e) or narrowest (a) insulating trench - has the width of the neighboring trench with the next largest or next smaller width dimension in the row.

2. Method for checking separation trench etching or isolation trench etching in SOI wafers, a test structure from a number of successive islands being introduced onto the wafer during an etching process or being prepared for an etching and after or in the course of the

Trench etching an electrical passage is measured several times; taking multiple electrical passage measurements; one of the measurements taking place between two neighboring islands (A, B), another taking place between other neighboring islands (B, C); and wherein the measurement values of the plurality of measurements for assessing the sufficient or sufficient depth of etched isolation trenches or

Separation trenches are used, which are located in particular outside the test structure on the pane in the area of an active circuit.

3. A method for checking trench etching (separating trench, isolation trench) in an SOI wafer, a test structure (A, B, C, D, E) being prepared on the wafer and introduced into it during trench etching and after or in the course of

5 trench etching, an electrical passage is measured successively in each case in each case between an island (A, B) and the pane region (S), which at least partially surrounds the island, and the size or amounts of the measurement results for assessing or recognizing the sufficient or sufficient depth of etched trenches 0 are used, which are located in particular outside the test structure, but were formed at the same time as the trench etching.

4. The method according to claim 2 or 3, wherein the test structure is that of claim 1. 5

5. The method of claim 2 or 3, wherein the electrical passage is a resistance or a conductance.

6. The method according to claim 2 or 3, wherein the passage is a current at constant o voltage or at constant current is a voltage measurement.

7. The method according to claim 2 or 3, wherein the measurements take place in the course of the etching, and the etching process is interrupted in order to carry out the measurement, in particular successively, on the islands. 5

8. The method according to claim 7, wherein the etching (the etching process) is continued if the trench with the width (d) corresponding to the current circuit has not yet been etched through to the insulating layer (1).

9. The method according to claim 7 or 8, wherein the etching is stopped when the trench is etched through with the width corresponding to the current circuit (d) to the insulating layer (1).

5

10. A method for checking isolation trench etching in SOI wafers, in which certain components or entire circuit units are insulated laterally dielectric from the environment by enclosing isolation trenches (8); by means of a test structure prepared on the individual pane after its completion in the process step "isolation trench etching", a check of the electrical resistances or the resistance between certain areas (A, B; B, C) of the test structure and / or between certain areas of the test structure and the surrounding crystal region (S) is carried out, the test structure being prepared on the wafer, which after the trench etching in the process step "isolation trench etching" leads to a number of associated islands, each of which is surrounded by a trench that is between two islands of different widths The isolating trench width occurring in the active circuit is arranged essentially in a central position of the row of islands and a partial length of the surrounding trench of each island, with the exception of the outermost islands, forms a common piece with the trench of an adjacent island, so that this T length in particular has the width of the adjacent trench with the next largest or next smaller width dimension in the row; - After completion of the "isolation trench etching" etching process, correct execution is carried out by repeatedly checking the electrical passage between two neighboring islands or one island and the surroundings (S) of the island outside the test structure; - The size of the measured value or the measured values obtained from the measurement can be used as a measure or a test for the desired, in particular predetermined depth of etched insulating trenches or separating trenches (8).

11. The method of claim 10, wherein the width of each trench around a respective island, in the course of the plurality of islands, increases in width, which increases in steps from island to island.

12. The method according to claim 10, wherein the width of an isolation trench (8) occurring in the active circuit is specified as the "relevant isolation trench width".

13. The method of claim 2, 3 or 10, wherein in a successive measurement of passages with an island is started, the surrounding trench width (d) corresponds to the relevant isolation trench (s) (8) of the circuit at least substantially.

14. The method according to claim 2 or 12, wherein the check is already finished after two measurements if there is between the relevant island pair

Test structure shows a transmission value that has jumped for total insulation (etching through to the insulating layer), but this test step that has changed suddenly has not yet emerged when testing the neighboring island pair with the smaller trench widths.

15. The method or test device according to one of the preceding claims, wherein at least three, preferably five or more island regions (A to E) lined up in a row are provided.

16. The method of claim 2 or 3 or 10, wherein no more measurements are made between the n islands than n-1, where n is the number of islands in the row of islands.

17. The method according to claim 2 or 3 or 10, wherein the maximum number of measurements from island to environment (S) is the number of islands in the row of islands.

18. The method according to claim 2 or 3, wherein after the etching, an evaluation of the measurement results takes place, in particular further etching steps of the following wafers are adapted accordingly in their permitted etching time to the result of the previous measurements.

19. The method according to claim 10, wherein the preparation is carried out by a mask specification.