EP1597770A1 - Bipolartransistor mit verbessertem basis-emitter- bergang und verfahren zur herstellung - Google Patents
Bipolartransistor mit verbessertem basis-emitter- bergang und verfahren zur herstellungInfo
- Publication number
- EP1597770A1 EP1597770A1 EP03785841A EP03785841A EP1597770A1 EP 1597770 A1 EP1597770 A1 EP 1597770A1 EP 03785841 A EP03785841 A EP 03785841A EP 03785841 A EP03785841 A EP 03785841A EP 1597770 A1 EP1597770 A1 EP 1597770A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- layer
- base
- emitter
- emitter layer
- bipolar transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
- 238000000034 method Methods 0.000 title claims description 28
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 20
- 239000010703 silicon Substances 0.000 claims abstract description 20
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 193
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 19
- 125000006850 spacer group Chemical group 0.000 claims description 17
- 238000002513 implantation Methods 0.000 claims description 13
- 230000007704 transition Effects 0.000 claims description 12
- 239000002019 doping agent Substances 0.000 claims description 9
- 229910052732 germanium Inorganic materials 0.000 claims description 9
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 239000011229 interlayer Substances 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims 1
- 238000005496 tempering Methods 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 11
- 239000000463 material Substances 0.000 description 16
- 230000007547 defect Effects 0.000 description 5
- 238000011065 in-situ storage Methods 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006735 deficit Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0804—Emitter regions of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
- H01L29/7371—Vertical transistors
- H01L29/7378—Vertical transistors comprising lattice mismatched active layers, e.g. SiGe strained layer transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
Definitions
- the invention relates to a bipolar transistor with a substrate in which a collector is formed, in which a base layer is provided above the collector, in which the base is formed monocrystalline and in which an emitter layer which is likewise monocrystalline is provided over the base.
- Bipolar transistors of this type are used as high-speed transistors. This is made possible by the high-quality monocrystalline structure of the base and emitter, both of which are epitaxially deposited. In this way, the transitions between the collector and the base, and especially between the base and the emitter, can be designed so that the interface problems that usually occur there are minimal. Furthermore, an epitaxial
- Base are formed thin, which reduces the base width and thus allows high switching speeds for the transistor.
- non-monocrystalline emitters for example made of polysilicon
- an implantation step or an in-situ doping during the deposition with subsequent annealing is usually required to drive the dopant into the single-crystal region.
- Disadvantages then arise from the high temperature input into the transistor layer system, which leads to a broadening of the intrinsic (active) base, to increased point defect diffusion and other similar defects.
- a broadened base profile is obtained, which limits the maximum achievable switching speed of the transistor, which is defined by the running time of the charge carriers, which they need to cross the base.
- a highly doped emitter-base junction with a high emitter-base capacitance and only a low breakdown voltage of the junction is also obtained.
- the polycrystalline structure of the emitter which can also be seen in a surface texture, affects the smoothness of the emitter-base transition solely due to the geometric design, with diffusion effects of the dopant used for the emitter being observed in particular at the grain boundaries.
- bipolar transistor with an epitaxial base and an epitaxial emitter layer.
- an insulation layer is created and structured in order to expose the intrinsic base. Only then is the emitter layer deposited epitaxially.
- the disadvantage of this method is that the time-consuming epitaxial step to be carried out in an epitaxial reactor has to be interrupted after the base layer has been produced. After the isolation layer has been produced and structured, the wafer must be introduced into the reactor again and the epitaxial conditions set. This requires additional time.
- the window in the insulation layer is opened, the intrinsic base is exposed unprotected to the etchant used, which can likewise damage the surface of the structure or the doping of the base.
- a silicon germanium alloy is epitaxially grown as the base layer. If a layer consisting of silicon is grown epitaxially directly above it, the silicon germanium alloy of the base layer can serve as an etch stop layer in the later structuring of the emitter layer.
- a disadvantage of this method is that the base layer has a high germanium content of approximately 20%, at least on the surface, in order to produce a high etching selectivity with respect to silicon. must. However, it has been shown that such a high germanium concentration at the base / emitter junction is disadvantageous for achieving a high switching speed. In addition, despite the high etching selectivity compared to silicon, the base layer can be damaged when the emitter layer is structured in the exposed surface areas of the base.
- the object of the present invention is therefore to provide a bipolar transistor with a high-quality emitter / base junction which avoids the disadvantages mentioned above.
- an epitaxially grown intermediate layer is arranged above the base and below the emitter layer and can be selectively etched against the emitter layer.
- the bipolar transistor according to the invention has the further advantage that the epitaxially grown layers for base and emitter as well as the intermediate layer in between follow one another directly, so that the epitaxial steps for their production can be carried out directly in succession in the same reactor without the substrates must be removed from the epitaxial reactor in between.
- the intermediate layer according to the invention also makes it possible to select the materials for the emitter layer and base independently of one another.
- the invention makes no restrictions or boundary conditions necessary for the material selection of the base layer and distinguishes it from known transistors. The only dependency arises in the selection of the intermediate layer, which must be dependent on the material of the emitter layer so that the emitter layer can be selectively etched against the intermediate layer.
- the invention also enables a precise definition of the emitter-base transition, since the exact arrangement and size of the emitter is determined by a direct structuring of the emitter layer.
- the transition is therefore defined with the same high accuracy as the structuring step.
- This is particularly advantageous over the indirect definition method of the emitter-base junction known from the prior art, in which the size of the active base, which corresponds to the area of the emitter-base junction, is defined via the window in an insulation layer becomes.
- additional interface effects are effective due to the additional layer, which can additionally disrupt the transition between emitter and base.
- the bipolar transistor according to the invention is delimited around the structured emitter layer by a spacer region which sits on the base layer and lies laterally on the emitter layer.
- the large-area base layer, within which the active base is formed, is more heavily doped than the (active) base in the regions which are not delimited by the emitter layer or the spacer region delimiting the emitter layer. That way this higher doped area of the base layer can be used as a base connection or extrinsic base, which is highly conductive due to the high doping and therefore allows a low-resistance connection of the active base.
- the spacer area also adjusts or ensures a distance between the extrinsic, highly doped base and the intrinsic (active), low-doped base.
- the known production of a spacer region delimiting a structure laterally takes place via anisotropic etching back of an auxiliary layer applied to cover the edge.
- the width of the spacer area which is determined parallel to the substrate plane, is determined by the thickness of the auxiliary layer covering this edge and applied to this area. With a suitable deposition process, the thickness of this auxiliary layer and thus the distance between the extrinsic and intrinsic base can be precisely adjusted.
- the intermediate layer is preferably relatively thin compared to the layer thickness of the base. It comprises an electrically conductive or at least semiconductive material without adversely affecting the emitter / base junction.
- a suitable material that fulfills all requirements for the intermediate layer according to the invention is silicon carbide. This is semiconducting, can be grown epitaxially and is sufficiently etch-selective compared to the materials normally used for the emitter layer, such as silicon or silicon germanium. Investigations have shown that a silicon carbide layer has no negative influence on the properties of the emitter-base junction.
- the emitter layer is produced in two stages or is formed as a double layer.
- a thin epitaxial layer is first grown and then reinforced by the deposition of a polycrystalline material.
- the doping of both partial layers for the emitter layer takes place in situ during the application process and is chosen to be approximately the same for both partial layers.
- the material for both partial layers is preferably also the same and preferably silicon.
- Such an emitter layer divided into two sub-layers has the advantage that it can be produced much faster and therefore more cost-effectively, since the epitaxy step is the more time-consuming and therefore cost-determining step
- Step is. Since the total layer thickness of the emitter layer is relatively high relative to the base, the portion of the epitaxially grown partial layer in the total layer thickness of the emitter layer is chosen to be as small as possible in order to shorten the epitaxy process. A polycrystalline sublayer is much easier and faster to apply. As in the first embodiment, this two-part emitter layer has the advantage that the emitter-base transition is of high quality and is not disturbed, for example, by any grain boundary effects. Since the polycrystalline layer can also be doped in situ during the application, no annealing steps are required here either, which could lead to undesired changes in doping profiles or to the formation or intensification of interface effects or defects.
- the transistor according to the invention is preferably designed as an npn bipolar transistor. This means that the base layer is p-doped. However, it is also possible to design the transistor as a pnp bipolar transistor.
- the individual layers of the transistor can consist almost independently of one another of different semiconductor materials, but preferably of a semiconductor material comprising silicon.
- This can be pure silicon or a semiconductor material that contains other semiconductors in different proportions.
- at least one of the emitter, collector and base layer consists of silicon, which contains up to approx. 30 (atomic)% germanium. Since germanium has a different band gap than silicon, the semiconducting properties can be set to a desired value via the content of the other semiconductor and in particular through the content of germanium.
- the silicon can also contain carbon in a proportion of up to 1%. It is also possible for one of the functional transistor layer regions, in particular the base, to consist of different layers which have different levels of germanium or carbon.
- Figure 1 shows two options, a collector in one
- FIG. 2 shows two different options for defining the base area with the aid of isolation areas.
- Figure 3 shows the arrangement after the production of the base layer.
- Figure 4 shows the arrangement after the production of the emitter layer.
- FIG. 5 shows the arrangement after structuring the emitter layer.
- FIG. 6 shows the arrangement during an oblique implantation process.
- Figure 7 shows the arrangement after the manufacture of the
- FIG. 8 shows a section of a finished bipolar transistor.
- FIG. 1 The bipolar transistor according to the invention is preferably constructed on a p-type silicon wafer used as substrate S.
- the collector K can, for example, be produced in the surface of the wafer by diffusing in a corresponding dopant of a first conductivity type (here an n-doping).
- FIG. 1b shows such a collector K produced by doping a substrate S.
- the collector K it is also possible for the collector K to have an additional epitaxial layer grown on a substrate S. For this purpose, this is at least monocrystalline, preferably semiconducting, and in particular a silicon wafer.
- the epitaxial layer has for the collector
- a lower dopant concentration of the first conductivity type (here n-doping), but can also be constructed in the opposite way to the doping of the underlying substrate S.
- a buried n + doping region (buried layer, not shown in the figure) can also be produced under the epitaxial layer for the collector K in FIG. 1a, for example by implantation in the substrate S prior to the epitaxial growth of the collector K. This buried Layer can be enlarged after the collector layer K has grown.
- the base region BG is defined with a minimum diameter which is approximately the same or only slightly larger than the minimum structure size that can be produced using the process used, in particular the lithography.
- the base region has a vertical base thickness of, for example, 150 to 400 ⁇ .
- a base layer BS is applied over the entire area under epitaxial conditions.
- the base layer BS grows monocrystalline over the base area BG, but over the insulation areas IG in polycrystalline modification.
- FIG. 3 shows the arrangement after the growth of the base layer in a schematic cross section.
- the base layer is made as thin as possible and has a thickness of approx. 100 ⁇ . In principle, however, higher base layer thicknesses of 300 to 500 ⁇ or more are also possible.
- the doping of the second conductivity type in the present case a p-doping, is incorporated in situ during the growth.
- the base layer is preferably grown using a low-temperature PE-CVD (Plasma Enhanced CVD) or using an LP-CVD (Low Pressure CVD) process.
- the base layer preferably consists of pure silicon. However, a silicon germanium alloy is also possible, and the germanium content can be up to 30%.
- the semiconducting properties can be set via the content and, for example, via a concentration profile via the base layer. It is advantageous, for example, to set a concentration gradient for germanium in silicon which is directly above the collector K has the highest concentration of, for example, 20 atomic% and drops to 0 down to the surface of the base layer.
- an intermediate layer is grown, whereby the same epitaxial conditions as when growing the base layer BS can be maintained.
- a preferred intermediate layer consists of silicon carbide.
- the intermediate layer is grown to a thickness which is substantially below that of the base layer, for example approximately 30 to 150 ⁇ .
- the intermediate layer is grown in the same reactor as the base layer without the wafer or the substrate having to be removed from the reactor.
- the emitter layer ES is grown in the same reactor.
- a relatively thick silicon layer is preferably grown, which is doped in situ with a dopant of the second conductivity type and is provided with an n + doping in the present exemplary embodiment.
- the thickness of the emitter layer ES is selected to be significantly higher than that of the base layer, in particular in order to provide a thickness reserve when a window is later opened for producing the emitter contacts.
- the growth is carried out at the lowest possible temperatures, for example at approximately 800 ° C. While the quality of the layers increases as the growth temperature decreases, the growth rate decreases in parallel.
- FIG. 4 shows the arrangement after the production of the emitter layer ES.
- a dashed line in the lower region of the emitter layer ES indicates that it can also consist of two sub-layers. While a first thinner sub-layer ES C is applied epitaxially, a comparatively thicker second sub-layer ES p is applied in a polycrystalline modification. The polycrystalline sub-layer ES p can also be grown in the same reactor, for which only the conditions on axle have to be changed.
- Figure 5 shows the arrangement after this step.
- the structuring determines the area of the emitter / base junction, which, as already mentioned, can correspond approximately to the size of the base region or a little less. Accordingly, the emitter layer is preferably arranged in the center of the base region.
- the low implantation energy creates a boron doping that is only close to the surface and moves the emitter-base transition inwards away from the etched outer edges of the emitter-base interface or the emitter-interlayer interface, where none are caused by the etching during structuring defects due to the emitter layer may exist.
- the surface areas of the base layer not covered by the emitter can be used to establish the base connection.
- a certain distance between the emitter-base transition and the more highly doped extrinsic base, that is to say the more highly doped surface area of the base layer BS, must be ensured.
- spacer regions SG surrounding the structured emitter are generated. By default, these are produced from an auxiliary layer of an electrically insulating material that is applied over the entire area, for example from a silicon oxide layer, by anisotropic etching.
- the spacer regions SG remain on the edges of all topographic steps, that is to say also on the edges of the emitter layer, provided that the steps are higher than the layer thickness of the auxiliary layer applied, in particular the oxide layer.
- the hard mask HM above the structured emitter layer serves to protect the emitter layer from attack by the etching plasma and is accordingly formed from a material that can be selectively etched against the auxiliary layer, for example silicon nitride.
- the thickness of the spacer regions SG measured parallel to the surface of the substrate essentially corresponds to the thickness of the original auxiliary layer and is selected such that it corresponds to the desired distance between extrinsic and active base.
- the basic implantation BI which is symbolized in FIG. 7 by corresponding arrows, takes place after the spacer regions have been produced.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
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Abstract
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10308870A DE10308870B4 (de) | 2003-02-28 | 2003-02-28 | Bipolartransistor mit verbessertem Basis-Emitter-Übergang und Verfahren zur Herstellung |
DE10308870 | 2003-02-28 | ||
PCT/EP2003/014339 WO2004077571A1 (de) | 2003-02-28 | 2003-12-16 | Bipolartransistor mit verbessertem basis-emitter-übergang und verfahren zur herstellung |
Publications (1)
Publication Number | Publication Date |
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EP1597770A1 true EP1597770A1 (de) | 2005-11-23 |
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ID=32863998
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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EP03785841A Ceased EP1597770A1 (de) | 2003-02-28 | 2003-12-16 | Bipolartransistor mit verbessertem basis-emitter- bergang und verfahren zur herstellung |
Country Status (6)
Country | Link |
---|---|
US (1) | US7319251B2 (de) |
EP (1) | EP1597770A1 (de) |
JP (1) | JP4414895B2 (de) |
AU (1) | AU2003294869A1 (de) |
DE (1) | DE10308870B4 (de) |
WO (1) | WO2004077571A1 (de) |
Families Citing this family (130)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102005021450B4 (de) * | 2005-05-10 | 2009-04-23 | Atmel Germany Gmbh | Integrierter Schaltkreis und Verfahren zur Herstellung eines integrierten Schaltkreises und dessen Verwendung |
US7439119B2 (en) * | 2006-02-24 | 2008-10-21 | Agere Systems Inc. | Thermally stable BiCMOS fabrication method and bipolar junction transistors formed according to the method |
DE102006011240A1 (de) * | 2006-03-10 | 2007-09-20 | Infineon Technologies Ag | Bipolartransistor und Verfahren zum Herstellen eines Bipolartransistors |
US9324576B2 (en) | 2010-05-27 | 2016-04-26 | Applied Materials, Inc. | Selective etch for silicon films |
US10283321B2 (en) | 2011-01-18 | 2019-05-07 | Applied Materials, Inc. | Semiconductor processing system and methods using capacitively coupled plasma |
US8999856B2 (en) | 2011-03-14 | 2015-04-07 | Applied Materials, Inc. | Methods for etch of sin films |
US9064815B2 (en) | 2011-03-14 | 2015-06-23 | Applied Materials, Inc. | Methods for etch of metal and metal-oxide films |
US8808563B2 (en) | 2011-10-07 | 2014-08-19 | Applied Materials, Inc. | Selective etch of silicon by way of metastable hydrogen termination |
US9267739B2 (en) | 2012-07-18 | 2016-02-23 | Applied Materials, Inc. | Pedestal with multi-zone temperature control and multiple purge capabilities |
US9373517B2 (en) | 2012-08-02 | 2016-06-21 | Applied Materials, Inc. | Semiconductor processing with DC assisted RF power for improved control |
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DE10308870B4 (de) | 2006-07-27 |
US20060060942A1 (en) | 2006-03-23 |
WO2004077571A1 (de) | 2004-09-10 |
JP2006514435A (ja) | 2006-04-27 |
JP4414895B2 (ja) | 2010-02-10 |
US7319251B2 (en) | 2008-01-15 |
AU2003294869A1 (en) | 2004-09-17 |
DE10308870A1 (de) | 2004-09-16 |
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