EP1589427B1 - System zur Steuerung des Hochfahrvorgangs - Google Patents

System zur Steuerung des Hochfahrvorgangs Download PDF

Info

Publication number
EP1589427B1
EP1589427B1 EP04256416A EP04256416A EP1589427B1 EP 1589427 B1 EP1589427 B1 EP 1589427B1 EP 04256416 A EP04256416 A EP 04256416A EP 04256416 A EP04256416 A EP 04256416A EP 1589427 B1 EP1589427 B1 EP 1589427B1
Authority
EP
European Patent Office
Prior art keywords
data
significant
protection code
sub
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP04256416A
Other languages
English (en)
French (fr)
Other versions
EP1589427A1 (de
Inventor
Masanori c/o Hitachi Ltd. Intl. Prop. Gp. Fujii
Yasuo c/o Hitachi Ltd. Intl. Prop. Gp. Inoue
Nobuyuki c/o Hitachi Ltd. Intl. Prop. Gp. Minowa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of EP1589427A1 publication Critical patent/EP1589427A1/de
Application granted granted Critical
Publication of EP1589427B1 publication Critical patent/EP1589427B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1417—Boot up procedures

Definitions

  • the present invention relates to a memory control system and to a technique for controlling booting of a processor.
  • Techniques for protection of data read by a processor include for example the techniques disclosed in Laid-open Japanese Patent Application No. 2001-109629, Laid-open Patent Application EP1324198 and Patent Application EP1369764.
  • Laid-open Japanese Patent Application No. 2001-109629 discloses the preparation of two boot programs that are used by a processor; if normal start-up is not achieved by reading one of these boot programs, the other boot program is read.
  • Laid-open Japanese Patent Application No. 2003-196097 discloses that, in addition to the instructions, the boot ROM stores the expected value of the checksum of the instructions, a DSP (digital signal processor) reads the instructions in the boot ROM and writes these into instruction memory and then performs a checksum, using the expected value of the checksum in the boot ROM, on the instructions that have thus been read into the instruction memory.
  • a DSP digital signal processor
  • Laid-open Japanese Patent Application No. 2004-13905 discloses a technique relating to code protection in the boot program.
  • boot memory memory such as ROM (hereinbelow referred to for convenience in description as "boot memory")
  • OS operating system
  • US5, 832, 005 discloses a method and means in a stored, program controlled machine to maintain an uninterrupted access and copying of simple parity-coded words of an initial program load (IPL) or other software from a read-only memory or a memory with limited rewrite capability in the presence of detectable errors, erasures or faults.
  • the method utilizes detected parity error in a word copied out from storage to modify the address register to seek the same word from a mirror address of an image copy of the IPL.
  • the image copy is stored at a second range of consecutive memory address nonintersecting and symmetric with the address range of the original IPL.
  • the IPL is then accessed in the second address range until either another parity error causes a switch back to the original IPL or the program terminates.
  • US6,571,347B discloses an intelligent computer initiation program recovery apparatus including a first memory containing a first computer initiation program wherein the first memory permits the stored first initiation program to be altered, a read-only-memory containing a second computer initiation program, and a circuit coupled to the first memory and the read-only-memory wherein the circuit calculates a value from the first program and compares the value against a predetermined value to enable the first memory when the value equals to the predetermined value and to enable the read-only-memory when the value differs from the predetermined value.
  • An aim of the present invention is therefore to ensure that, in the processing prior to starting up of the processor, spurious data codes are not read by the processor.
  • a boot control system comprises:
  • This boot control system may be incorporated in various types of electronic equipment comprising a processor.
  • the "start-up data” may consist for example of the boot program of the OS of the processor and constituent elements of the OS itself that are read in accordance with this boot program.
  • the "start-up protection code” may consist for example of parity or ECC (Error Correcting Code).
  • the validity check on at least one of said start-up protection code and said start-up data may be at least one of a check of validity of the start-up data using for example the start-up protection code and a check of validity of the start-up protection code, using the start-up data.
  • a storage control system further comprises a plurality of storage devices that store data; a cache memory for temporarily storing data that is exchanged between said storage devices and said external device; and a control device for controlling the exchange of data performed between said storage devices and said external device through said cache memory.
  • said data checking hardware comprises a subdividing circuit that subdivides the start-up data received from said processor into said start-up data most significant elements and said start-up data least significant elements, a protection code generating circuit that generates said start-up most significant protection code using said start-up data most significant elements and generates said start-up least significant protection code using said start-up data least significant elements, and a data storage circuit that stores said start-up data most significant elements and said start-up data least significant protection code in said first start-up sub-memory region and that stores said start-up data least significant elements and said start-up most significant protection code in said second start-up sub-memory region.
  • a processor chip according to another embodiment of the present invention comprises a processor core, and a boot control system according to the first aspect above.
  • Figure 1 shows the overall layout of a computer system comprising a storage control system according to an embodiment of the present invention.
  • This computer system 100 comprises a storage control system 3 and one or a plurality of host devices 1 connected with this storage control system 3.
  • a host device 1 may be for example a personal computer or workstation and constitutes a computer system comprising for example a CPU (central processing unit) and memory. Various functions may be implemented by running various types of program by the CPU of the host device 1.
  • the host device 1 is connected with the storage control system 3 through a communication network such as for example a LAN.
  • the storage control system 3 is for example a RAID (Redundant Array of Independent Inexpensive discs) system having one or more physical disc groups 9 comprising a plurality of disc storage devices arranged in an array.
  • the storage control system 3 comprises one or a plurality of channel control sections 13, a cache memory 15, a control memory 17, one or more physical disc groups 9, one or more disc control sections 19, a switching control section 21 and an SVP (Service Processor) 12.
  • the channel control sections 13 are connected with host devices 1.
  • the channel control sections 13 may be constituted by a hardware circuit, and possibly software, and effect data communication between this storage control system 3 and host devices 1 that are connected therewith.
  • the channel control sections 13 comprise a communication interface for performing communication with host devices 1 that are connected therewith and also comprise a processor for performing processing by interpreting various types of command received from the host devices 1.
  • the channel control sections 13 read data stored in the cache memory 15 and transmit this to the host devices 1 after referring to information registered in the control memory 17, and store data received from the host devices 1 and that is to be written, in the cache memory 15.
  • the cache memory 15 is a memory shared by the channel control sections 13 and the disc control sections 19.
  • the cache memory 15 temporarily stores data that is exchanged between the channel control sections 13 and the disc control sections 19.
  • the control memory 17 is also a memory that is shared by the channel control sections 13 and disc control sections 19.
  • data from the host devices 1 are written to logical volumes 11, to be described, and control information relating for example to transmission of data that is read therefrom from the logical volumes 11 to the host devices 1 is registered.
  • Each physical disc group 9 is constituted by arranging a plurality of disc storage devices in an array.
  • Various types of device such as for example hard disc devices, floppy disc devices, or semiconductor storage devices may be employed as the disc storage devices constituting the physical disc groups 9.
  • a plurality of logical volumes 11 constituting logical storage regions are set up on the physical storage region provided by the one or more physical disc groups 9.
  • the disc control sections 19 are provided for example for each of the physical disc groups 9 and control prescribed physical disc groups 9.
  • the disc control sections 19 may be constituted by hardware circuits, software or a combination of these.
  • the disc control sections 19 perform reading or writing of data in respect of a logical volume selected from the plurality of logical volumes 11 in accordance with control information recorded in the control memory 17.
  • the disc control sections 19 convert data access requests in respect of logical volumes 11 into data access requests to physical discs by converting logical addresses into physical addresses.
  • the switching control section 21 may be constituted as a high-speed bus such as for example a very high-speed cross bus switch that performs data transfer using a high-speed switching action.
  • the switching control section 21 is capable of mutual communication with the channel control sections 13, the disc control sections 19, control memory 17 and cache memory 15. Exchange of data or commands between these channel control sections 13, the disc control sections 19, control memory 17 and cache memory 15 is performed through the switching control section 21.
  • the SVP 12 is an information processing terminal (for example a notebook personal computer).
  • the SVP 12 is connected with a microprocessor, not shown, in each disc control section 13 and each disc control section 19, by means of a communication network (for example a LAN).
  • the SVP 12 displays information received from the microprocessor on its display screen.
  • This computer system 100 may be directly connected with the disc control sections 19 and physical disc groups 9 or may be indirectly connected by means of a network. Also, the physical disc groups 9 and disc control sections 19 may be integrally constructed. A single logical volume 11 may be respectively allocated to each channel control section 13 or a single logical volume 11 may be shared by a plurality of channel control sections 13.
  • one or more microprocessors may be provided in the channel control sections 13 and disc control sections 19.
  • the one or more microprocessors control the operation cf the channel control sections 13 or disc control sections 19 where these are provided.
  • a boot control system is provided that is so constructed that spurious data code cannot be read by the channel control sections 13 and disc control sections 19 prior to start-up of the incorporated MP. This boot control system is described below.
  • Figure 2 shows an example of the construction of a boot control system.
  • Figure 3 shows the data structures in the two boot memories 115 and 117 employed by the MP provided in this boot control system and in the local memory of this MP. It should be noted that, in the following description, the data that is exchanged between the boot memories 115, 117 and the MP 111 is termed the "MP data" inordertodifferentiate it from the data that is exchanged between the host device 1 and the storage control system 3.
  • the boot control system 120 includes a first boot memory 115, second boot memory 117, local memory 159, MP 111 and PLD (Programmable Logic Device) 121.
  • the first boot memory 115 and the second boot memory 117 are respectively for example 8-byte non-volatile memories (for example ROM or flash ROM).
  • the first boot memory 115 comprises a plurality of memory spaces, for example a first direct execution space 115B and a first file space 115F.
  • the second boot memory 117 comprises a plurality of memory spaces, for example a second direct execution space 117B and a second file space 117F.
  • the direct execution spaces 115B and 117B are memory spaces that store the required MP data (hereinbelow referred to as start-up MP data) that is read by the MP111 in order to start up the OS of the MP 111 (in other words, up to when the OS starts) .
  • start-up MP data the required MP data
  • PLs least significant protection data
  • start-up DLs start-up MP data least significant elements
  • PHs most significant protection data
  • the start-up DHs are MP data element on the most significant side of the start-up MP data and the start-up DLs are MP data element on the least significant side of the start-up MP data.
  • the data sizes of the start-up DHs and start-up DLs may be the same or different.
  • the start-up MP data (for example two-byte data) is subdivided into the start-up DHs (for example one-byte data) and the start-up DLs (for example one-byte data).
  • the start-up MP data is a constituent element of at least one of for example the boot program of the MP 111 or the OS that is read in accordance with this boot program.
  • the PHs are MP data including the start-up most significant protection code constituting protection code for the start-up DHs, the first address in the first boot memory 115 of the start-up DHs and, of the first address protection code constituting protection code for this first address, at least the start-up most significant protection code.
  • the PLs are MP data including the start-up least significant protection code constituting protection code for the start-up DLs, the second address in the second boot memory 117 of the start-up DLs and, of the second address protection code constituting protection code for this second address, at least the start-up least significant protection code.
  • the protection code may be for example parity or ECC (error correcting code).
  • the first direct execution space 115B stores a single PL in respect of a single start-up DH.
  • the second direct execution space 117B stores a single PH in respect of a single start-up DL.
  • the file spaces 115F and 117F are memory spaces in which the MP data employed by the OS (hereinbelow called MP data for the OS) is stored after start-up of the OS of the MP 111.
  • the MP data for the OS comprises for example two-byte data. In Figure 3, the most significant bytes of the start-up MP data and OS data are indicated by hatching and the least significant bytes are indicated by a reticulate pattern of dots.
  • the file spaces 115F and 117F may store the expected values of the checksum in respect of the various items of MP data for the OS.
  • At least one of the first direct execution space 115B and first file space 115F and/or at least one of the second direct execution space 117B and second file space 117F may be variable (for example the MP 111 may adjust the capacities of the respective spaces in accordance with a user request) .
  • the direct execution spaces 115B, 117B may be provided on a first sub-memory (for example DRAM) and the file spaces 115F, 117F may be provided on a second sub-memory, separate from the first sub-memory (for example SRAM).
  • first boot memory 115 and second boot memory 117 are described in separate memories; for example a first memory space corresponding to the first boot memory 115 and a second memory space corresponding to the second boot memory 117 could be provided on the same memory. Also, the first boot memory 115 and the second boot memory 117 could be provided for each MP, or could be shared by a plurality of MPs.
  • the local memory 159 is employed by the MP 111 for example as a work region of the MP 111 or a reception buffer region in which the data received from outside this boot control system 120 (for example from a host device 1 or a logical volume 11) is temporarily accumulated.
  • the start-up MP data and MP data for the OS that are read by the MP 111 from the first boot memory 115 and the second boot memory 117 are expanded into the local memory 159.
  • An example of the result of this expansion is shown in Figure 3. Specifically, into a first prescribed region 159A of the local memory 159, there are expanded the start-up DH and PL that are read from the first direct execution space 115B and the start-up DL and PH that are read from the second direct execution space 115F. Also, into a second prescribed region 159B of the local memory 159, there are expanded the MP data for the OS that is read from the first file space 115F and the MP data for the OS that is read from the second file space 117F.
  • the MP 111 shown in Figure 2 controls the operation of the channel control section 13 or the disc control section 19 in which this MP 111 is incorporated. If for example the MP 111 is incorporated in a channel control section 13, the MP 111 for example reads received data from a host device 1 into the cache memory 15 and the disc control section 19 reads data that has been written to the cache memory 15 and transmits this data to a host device 1. Also, if the MP 11 is incorporated in a disc control section 19, the MP 111 for example writes data that has been read from a logical volume 11 to the cache memory 15 and data written in the cache memory 15 is read by a channel control section 13 and stored in a logical volume 11.
  • the MP 111 when the MP data is read, the original address for reading registered beforehand in a register 123 of the MP 111 is output to a PLD 121 and, in accordance therewith, if a data pair is received from the boot memories 115, 117, this data pair is expanded into the first prescribed region 159A of the local memory 159. Also, the MP 111 outputs to the PLD 121 the start-up MP data and the original address for storage that displays the storage destination thereof. It should be noted that the "original address" is the address managed by the MP 111 and is different from the addresses of the boot memories 115 and 117.
  • the first address which is the address of the first boot memory 115 and the second address, which is the address of the second boot memory 117, are generated by the PLD 121 from the original address.
  • original addresses when the original address for reading and the address for storage are referred to generally, they will simply be termed "original addresses”.
  • the PLD 121 is for example a pure hardware circuit that is interposed on the communication route between the MP 111 and the first boot memory 115 and second boot memory 117.
  • the PLD 121 comprises an address buffer 101, address conversion circuit 102, read buffer 109, data check circuit 107, address protection code generating circuit 105, data buffer 103, sub-division protection generating circuit 119 i and coupling circuit 251.
  • the address buffer 101 is a buffer that temporarily accumulates original addresses that are input through the data input/output line 8 from the MP 111.
  • the address conversion circuit 102 acquires original addresses from the address buffer 101 and, using these original addresses, generates a first address (i.e. address in the first boot memory 115) and a second address i.e. address in the second boot memory 117).
  • the address conversion circuit 102 determines beforehand the rule whereby an original address that is received is used to generate a first address and a second address and outputs the first address and second address that are generated in accordance with this rule.
  • the first address that is output is input to the first boot memory 115 through a first address line 2A and the second address is input to the second boot memory 117 through a second address line 2B. Also, the first address and the second address are input to the address protection code generating circuit 105.
  • the first address includes for example a first sub-address for reading or writing the one-byte start-up DH and a second sub-address for reading or writing the one-byte PL.
  • the second address includes for example a third sub-address for reading or writing the one-byte start-up DL and a fourth sub-address for reading or writing the one-byte PH.
  • the MP data that is present at the first address of the first boot memory 115 is output to the PLD 121 through a first data line 4A.
  • the MP data that is present at the second address of the second boot memory 117 is output to the PLD 121 through a second data line 4B.
  • the MP data that was output respectively through the first data line 4A and the second data line 4B is temporarily stored in the read buffer 109.
  • the start-up DH and PL and the start-up DL and PH are read to the read buffer 109.
  • the start-up DH and start-up DL that are then read are constituent elements of the same MP data.
  • a pair comprising another start-up DL that does not constitute the same MPdata as the start-up DH is not read, but a start-up DL that constitutes the same MP data as this start-up DH is read. This is because the first address and the second address that are generated by the address conversion circuit 102 constitute the content that is thus read.
  • the data check circuit 107 performs a data check using the start-up DH and PL and the start-up DL and PH in the read buffer 109.
  • the data check circuit 107 performs a first check which is a check of the validity of at least one of the start-up DH and PH and a second check which is a check of the validity of at least one of the start-up DL and PL.
  • the data checking circuit 107 checks the validity of the start-up DH using the start-up most significant protection code contained in the PH and, in the second check, checks the validity of the start-up DL using the start-up least significant protection code contained in the PL.
  • the data checking circuit 107 If the data checking circuit 107 obtains a positive check result in both the first check and the second check, the data checking circuit 107 inputs the start-up DH and PL and the start-up DL and PH in the read buffer 109 to the MP 111 through a data input/output line 8. Contrariwise, if the data checking circuit 107 obtains a negative check result in at least one of the first check and the second check, it executes prescribed error processing so that neither the start-up DH and PL nor the start-up DL and PH are output to the MP 111.
  • the error processing may comprise for example that the data checking circuit 107 outputs the first address and the second address contained in the PH and PL to the first boot memory 115 and second boot memory 117, reads the same start-up DH and PL and start-up DL and PH to the read buffer 109 and again performs the first check and second check. Also, the error processing may comprise for example that the data checking circuit 107 resets the MP 111 by using a reset signal line 6. It should be noted that the data checking circuit 121 need not necessarily always perform the first and second checks but could for example perform error processing without performing the second check in cases where a negative check result is obtained by the first check.
  • the data buffer 103 is a buffer that temporarily accumulates start-up MP data that is input from the MP 111 through the data input/output line 8.
  • the sub-division protection generating circuit 119 subdivides the start-up MP data in the data buffer 103 into a start-up DH and start-up DL. Also, the start-up protection generating circuit 119 generates start-up most significant protection code based on the start-up DH obtained by the sub-division and generates start-up least significant protection code based on the start-up DL obtained by the sub-division. The sub-division protection generating circuit 119 generates and outputs the start-up DH, start-up DL, start-up most significant protection code and start-up least significant protection code.
  • the address protection code generating circuit 105 generates a first address protection code based on the first address from the address conversion circuit 102 and generates a second address protection code based on the second address.
  • the address protection code generating circuit 105 outputs the first address and second address from the address conversion circuit 102 with the first address protection code and second address protection code that have thus been generated.
  • a coupling circuit 251 generates a PH by coupling the first address protection code from the address protection code generating circuit 105, first address and start-up most significant protection code, and outputs this PH, a start-up DL selected from the start-up DHs and the start-up DLs from the sub-division protection generating circuit 119 to the second boot memory 117 through the second data line 4B. Inthisway, the start-up DL and PH are written in the location indicated by the second address that is input to the second boot memory 117 through the second address line 2B from the address conversion circuit 102.
  • the coupling circuit 251 generates a PL by coupling the second address protection code, from the address protection code generating circuit 105, the second address and the start-up least significant protection code and outputs this PL and a start-up DH selected from the start-up DHs and start-up DLs from the sub-division protection generating circuit 119 to the first boot memory 115 through the first data line 4A.
  • the start-up DH and PL are written in the location indicated by the first address that is input to the first boot memory 115 through the first address line 2A from the address conversion circuit 102.
  • Figure 4 shows the process flow performed when the MP 111 reads the start-up MP data.
  • the MP 111 When for example the power of the MP 111 is turned on, the MP 111 resets the value of the register 123 (step S1) and performs initialization of the register 123 (S2) . In this way, the original address for reading the start-up MP data is written to the register 123.
  • the MP 111 outputs the original address for reading (for example the original address for reading the boot program) that is written in the register 123 to the PLD 121 (S3).
  • the original address for reading that is output to the PLD 121 from the MP 111 is accumulated in the address buffer 101.
  • the address conversion circuit 102 generates a first and second address by using the original address for reading in the address buffer 101 and thereby specifies the first address in the first boot memory 115 and the second address in the second boot memory 117 (S4). In this way, the start-up DH and PL that are present in the first address of the first boot memory 115 are read and stored in the buffer 109 and the start-up DL and PH that are present in the second address of the second boot memory 117 are stored in the read buffer 109 (S5).
  • the data checking circuit 107 checks the validity (i.e. performs a first check) of the start-up DH by using the start-up most significant protection code included in the PH in the read buffer 109 and checks the validity (i.e. performs a second check) of the start-up DL using the start-up least significant protection code included in the PL (S6).
  • the data checking circuit 107 performs prescribed error processing to arrange that neither of the start-up DH and PL or start-up DL and PH are output to the MP 111 and resets (S8) the MP 111 using for example the reset signal line 6. In this way, the MP 111 is locked (S11).
  • the data checking circuit 107 If, in S7, the data checking circuit 107 obtained a positive check result in respect of both of the first check and the second check (Y in S7), the start-up DH and PL and the start-up DL and PH in the read buffer 109 are transferred to the MP 111 (S9). In other words, the data checking circuit 107 allows reading of the start-up DH and PL and the start-up DL and PH to the MP 111.
  • the processing of S6 to S9 is performed for all of the start-up DH and PL and start-up DL and PH in respect of the boot program (N in S10).
  • the MP 111 expands (S12) this start-up DH and PL and start-up DL and PH that have thus been read into the local memory 159.
  • the MP 111 If all of the start-up DH and PL and start-up DL and PH have been registered in the local memory 159 (Y in S13) in respect of the boot program i.e. if the boot program has been properly written to the local memory 159, the MP 111 outputs (S14) the original address for reading for reading the OS, in accordance with this boot program. In this way, the processing of S4 to S10 described above is performed.
  • the MP 111 is blocked (S15) in accordance with the reset signal from the PLD 121 but, otherwise, the OS of the MP 111 is started up (Y in S16 and S17, S18) by expansion of the OS in the local memory 159.
  • the OS of the MP 111 may perform a sum check in respect of the MP data for the OS.
  • a hardware check is performed on the MP data that is read by the MP 111 and after starting up of the MP 111 a software check can be performed by the OS on the MP data that is read by the MP 111.
  • Figure 5 shows the flow of the processing that is performed when writing the start-up MP data by the MP 111.
  • the MP 111 transmits (S51) the original address for storage of the group of start-up MP data constituting the boot program or OS, and also the group of these start-up MP data, to the PLD 121.
  • the group of start-up MP data that is transmitted from the MP 111 to the PLD 121 is accumulated on the data buffer 103.
  • the sub-division protection generating circuit 119 subdivides (S53) the respective groups of start-up MP data in the data buffer 103 into start-up DHs and start-up DLs. Also, the sub-division protection generating circuit 119 generates (S54) start-up most significant protection code based on the start-up DHs obtained by this sub-division process and generates start-up least significant protection code based on the start-up DLs obtained by the sub-division process. The sub-division protection generating circuit 119 generates and outputs (S55) the start-up DHs, start-up DLs, start-up most significant protection code and start-up least significant protection code.
  • the original address for storage that is transmitted from the MP 111 to the PLD 121 is accumulated in the address buffer 101.
  • the address conversion circuit 102 generates the first and second address based on the original address for storage in the address buffer 101 and designates the first address in the first boot memory 115 and designates the second address in the second boot memory 117 (S56). Also, the address conversion circuit 102 outputs the first address and the second address to the address protection code generating circuit 105.
  • the address protection code generating circuit 105 generates first address protection code based on the first address from the address conversion circuit 102 and generates second address protection code based on the second address (S57).
  • the address protection code generating circuit 105 outputs the first address protection code and the second address protection code that are thus generated and the first address and second address from the address conversion circuit 102 (S58).
  • the coupling circuit 251 generates a PL by coupling the second address protection code from the address protection code generating circuit 105 and the second address and start-up least significant protection code, and writes (S59) this PL together with the start-up DH selected from the start-up DHs and start-up DLs from the sub-division protection generating circuit 119 in the first boot memory 115 through the first data line 4A.
  • the coupling circuit 251 generates a PH by coupling the first address protection code from the address protection code generating circuit 105 and the first address and start-up most significant protection code, and writes (S60) this PH together with the start-up DL selected from the start-up DHs and start-up DLs from the sub-division protection generating circuit 119 in the second boot memory 117 through the second data line 4B.
  • a PLD 121 is interposed on the communication route between the MP 111 and the boot memories 115, 117 .
  • the boot memories 115 and 117 store start-up MP data and protection code thereof.
  • the PLD 121 performs, in hardware fashion, a check of the validity of the start-up MP data using the protection code thereof. If the result is that a negative check result is obtained, the PLD 121 does not output the start-up MP data to the MP 111 .
  • the start-up DHs and start-up DLs constituting the MP data are stored in separate boot memories 115, 117, the PH, including the protection code of the start-up DHs, is stored in the second boot memory 117 where the start-up DLs are stored and the PLs, including the protection codes of the start-up DLs, are stored in the first boot memory 119 where the start-up DHs are stored.
  • a given boot memory does not store the protection codes for given MP elements of the start-up MP data but rather the protection codes for the other MP data elements.
  • the memory spaces of the boot memories 115, 117 can be classified in accordance with the nature of the data stored therein.
  • the boot memories 115, 117 can be classified into direct execution spaces 115B, 117B in which start-up MP data is stored and file spaces 115F, 117F, in which OS data employed after start-up is stored.
  • the data that is read by the MP 111 can be checked by different methods depending on the type of space.
  • Figure 6 shows a channel control section according to a first modified example of the embodiment of the present invention.
  • the channel control section 13 comprises for example a microprocessor unit (hereinbelow called MPU) 201, a local memory 159, a host interface circuit (hereinbelow called host I/F) 204 connected with the host device 1 and a switch interface circuit (hereinbelow called switch I/F) 208 connected with a switching control section 21.
  • the MPU 201 comprises a processor core 203, a first boot memory 115 and second boot memory 117 that store for example start-up MP data read by the processor core 203, and a PLD 121 interposed on the communication route of the processor core 203 and boot memories 115, 117.
  • the MPU 201 comprises a DMA controller 207 that controls direct memory access, a memory controller 209 that controls access by the processor core 203 in respect of the local memory 159 and an I/F controller that controls communication of the processor core 203 and a device that is outside the MPU 201 through a PCI bus 206.
  • the processor core 203 starts up when it reads the OS from the boot memories 115, 117.
  • the boot memories 115, 117 may be SRAM or DRAM.
  • Figure 7 is a view given in explanation of a second modified example of the embodiment of the present invention.
  • a boot control system 123 is incorporated in the channel control sections 13 (or disc control sections 19) .
  • An SVP 12 is connected through a communication network such as a LAN with the MP 111 in the boot control system 123.
  • the SVP 12 monitors the various MPs on the channel control sections 13 on each disc control section 19 (for example, monitoring is performed by periodically sending signals to each MP and monitoring whether or not a prescribed response signal is returned). If the SVP 12 cannot detect an MP that ought to have started up (for example if no response signal has been returned from the MP that ought to have started up), for example as shown in Figure 7, a message to the effect that this MP has not started up and a message proposing re-installation of the program or OS are displayed on the display screen.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Stored Programmes (AREA)
  • Debugging And Monitoring (AREA)
  • Storage Device Security (AREA)

Claims (5)

  1. Bootsteuersystem (120), aufweisend:
    einen Prozessor (111),
    Hochfahrspeicherbereiche (115, 117) zum Speichern von zum Hochfahren des Prozessors benötigter Hochfahrdaten und eines einen Schutzcode für die Hochfahrdaten darstellenden Hochfahrschutzcodes, und
    Datenprüfhardware (121), dadurch gekennzeichnet, daß
    die Hochfahrdaten ein höchstwertiges Hochfahrdatenelement (DH), das das Element auf der höchstwertigen Seite der Hochfahrdaten darstellt, und ein niedrigstwertiges Hochfahrdatenelement (DL) umfassen, das das Element auf der niedrigstwertigen Seite der Hochfahrdaten darstellt,
    der Hochfahrschutzcode einen höchstwertigen Hochfahrschutzcode (PH), der den Schutzcode des höchstwertigen Elements (DH) der Hochfahrdaten darstellt, und einen niedrigstwertigen Hochfahrschutzcode (PL) enthält, der den Schutzcode des niedrigstwertigen Elements (DL) der Hochfahrdaten darstellt,
    der Hochfahrspeicherbereich einen ersten Hochfahrteilspeicherbereich (115B) und einen zweiten Hochfahrteilspeicherbereich (117B) umfaßt,
    der erste Hochfahrteilspeicherbereich (115B) das höchstwertige Hochfahrdatenelement (DH) und den niedrigstwertigen Hochfahrdatenschutzcode (PL) speichert,
    der zweite Hochfahrteilspeicherbereich (117B) das niedrigstwertige Hochfahrdatenelement (DL) und den höchstwertigen Hochfahrschutzcode (PH) speichert und
    die Datenprüfhardware (121) eingerichtet ist,
    den niedrigstwertigen Hochfahrschutzcode (PL) und das höchstwertige Hochfahrdatenelement (DH) aus dem ersten Hochfahrteilspeicherbereich (115B) zu lesen,
    den höchstwertigen Hochfahrschutzcode (PH) und das niedrigstwertige Hochfahrdatenelement (DL) aus dem zweiten Hochfahrteilspeicherbereich (117B) zu lesen,
    eine erste Teilprüfung auszuführen, die die Gültigkeit des höchstwertigen Hochfahrschutzcode (PH) und/oder des höchstwertigen Hochfahrdatenelements (DH) prüft, und eine zweite Teilprüfung auszuführen, die die Gültigkeit des niedrigstwertigen Hochfahrschutzcodes (PL) und des niedrigstwertigen Hochfahrdatenelements (DL) prüft, und
    den Prozessor (111) zurückzusetzen, wenn in der ersten Teilprüfung und/oder der zweiten Teilprüfung ein negatives Prüfungsergebnis erhalten wird, und das höchstwertige Hochfahrdatenelement (DH) und das niedrigstwertige Hochfahrdatenelement (DL) in den Prozessor einzugeben, wenn sowohl in der ersten Teilprüfung als auch in der zweiten Teilprüfung ein positives Prüfungsergebnis erhalten wird.
  2. System nach Anspruch 1, wobei
    die Datenprüfhardware (121) eingerichtet ist,
    die vom Prozessor (111) erhaltenen Hochfahrdaten in die höchstwertigen Hochfahrdatenelemente und die niedrigstwertigen Hochfahrdatenelemente zu unterteilen,
    den höchstwertigen Hochfahrschutzcode unter Verwendung der höchstwertigen Hochfahrdatenelemente zu erzeugen,
    den niedrigstwertigen Hochfahrschutzcode unter Verwendung der niedrigstwertigen Hochfahrdatenelemente zu erzeugen,
    die höchstwertigen Hochfahrdatenelemente und den niedrigstwertigen Hochfahrdatenschutzcode im ersten Hochfahrteilspeicherbereich (116B) zu speichern und
    die niedrigstwertigen Hochfahrdatenelemente und den höchstwertigen Hochfahrschutzcode im zweiten Hochfahrteilspeicherbereich (116B) zu speichern.
  3. Speichersteuersystem (100), das mit einer externen Vorrichtung (1) verbunden ist und folgendes umfaßt:
    mehrere Speichervorrichtungen (9) zum Speichern von Daten,
    einen Cache-Speicher (15) zum vorübergehenden Speichern von Daten, die zwischen den Speichervorrichtungen und der externen Vorrichtung ausgetauscht werden, und
    eine Steuervorrichtung (13, 19) zum Steuern des zwischen den Speichervorrichtungen und der externen Vorrichtung durch den Cache-Speicher vorgenommenen Datenaustauschs,
    wobei das Speichersteuersystem ein Bootsteuersystem (120) nach Anspruch 1 enthält.
  4. System (100) nach Anspruch 3, wobei die Datenprüfhardware (121) folgendes umfaßt:
    eine Unterteilungsschaltung (119) zum Unterteilen der vom Prozessor (111) erhaltenen Hochfahrdaten in die höchstwertigen Hochfahrdatenelemente und die niedrigstwertigen Hochfahrdatenelemente,
    eine Schutzcode-Erzeugungsschaltung (119) zur Erzeugung des höchstwertigen Hochfahrschutzcodes (PH) unter Verwendung der höchstwertigen Hochfahrdatenelemente (DH) und zur Erzeugung des niedrigstwertigen Hochfahrschutzcodes (PL) unter Verwendung der niedrigstwertigen Hochfahrdatenelemente (DL), und
    eine Datenspeicherschaltung (251) zum Speichern der höchstwertigen Hochfahrdatenelemente (DH) und des niedrigstwertigen Hochfahrdatenschutzcodes (PL) im ersten Hochfahrteilspeicherbereich (115B) und zum Speichern der niedrigstwertigen Hochfahrdatenelemente (DL) und des höchstwertigen Hochfahrschutzcodes (PH) im zweiten Hochfahrteilspeicherbereich (117B).
  5. Prozessorchip (201), aufweisend:
    einen Prozessorkern (203), und
    ein Bootsteuersystem (120) nach Anspruch 1.
EP04256416A 2004-04-19 2004-10-19 System zur Steuerung des Hochfahrvorgangs Expired - Lifetime EP1589427B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004122739A JP4544901B2 (ja) 2004-04-19 2004-04-19 記憶制御システム及びブート制御システム
JP2004122739 2004-04-19

Publications (2)

Publication Number Publication Date
EP1589427A1 EP1589427A1 (de) 2005-10-26
EP1589427B1 true EP1589427B1 (de) 2006-12-13

Family

ID=34930742

Family Applications (1)

Application Number Title Priority Date Filing Date
EP04256416A Expired - Lifetime EP1589427B1 (de) 2004-04-19 2004-10-19 System zur Steuerung des Hochfahrvorgangs

Country Status (4)

Country Link
US (2) US7287155B2 (de)
EP (1) EP1589427B1 (de)
JP (1) JP4544901B2 (de)
DE (1) DE602004003677T2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7623660B1 (en) 2004-07-20 2009-11-24 Xilinx, Inc. Method and system for pipelined decryption
US7689726B1 (en) * 2004-10-01 2010-03-30 Xilinx, Inc. Bootable integrated circuit device for readback encoding of configuration data
US7328335B1 (en) 2004-10-01 2008-02-05 Xilinx, Inc. Bootable programmable logic device for internal decoding of encoded configuration data
TWI355608B (en) * 2008-01-30 2012-01-01 Inventec Corp Computer system with dual basic input output syste
GB2471464A (en) * 2009-06-29 2011-01-05 Nokia Corp Procedure for generating a merged command list form the static lists to be used to start up or boot up the host device.
CN102087625A (zh) * 2009-12-04 2011-06-08 鸿富锦精密工业（深圳）有限公司 开机测试系统及测试方法
TWI450194B (zh) * 2011-11-10 2014-08-21 Inst Information Industry 作業系統處理方法以及系統、以及儲存其之電腦可讀取記錄媒體
KR102698994B1 (ko) * 2018-12-03 2024-08-27 에스케이하이닉스 주식회사 저장 장치 및 그 동작 방법
CN109634906B (zh) * 2018-12-12 2022-07-05 浪潮(北京)电子信息产业有限公司 一种ic通信系统和方法

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1002271B (it) * 1973-12-27 1976-05-20 Honeywell Inf Systems Perfezionamento ai dispositivi di controllo di parita nelle memorie a semiconduttori
JPS6371736A (ja) * 1986-09-12 1988-04-01 Fujitsu Ltd Ｒｏｍのパリテイビツト領域割当方式
US5388267A (en) * 1991-05-29 1995-02-07 Dell Usa, L.P. Method and apparatus for updating and restoring system BIOS functions while maintaining BIOS integrity
JPH05216776A (ja) * 1992-02-04 1993-08-27 Hitachi Ltd 自動車用コントロールユニット
JPH06243049A (ja) * 1993-02-15 1994-09-02 Fujitsu Ltd パリティ制御回路
US5797023A (en) 1994-10-17 1998-08-18 Digital Equipment Corporation Method and apparatus for fault tolerant BIOS addressing
KR100198382B1 (ko) * 1996-05-07 1999-06-15 윤종용 멀티-부팅 기능을 갖는 컴퓨터 장치
TW400469B (en) 1997-07-08 2000-08-01 Winbond Electronics Corp Device capable of fixing programs in embedded microprocessor
JPH1196012A (ja) * 1997-09-19 1999-04-09 Yokogawa Electric Corp 分散制御装置
US5832005A (en) 1997-12-11 1998-11-03 International Business Machines Corporation Fault-tolerant method and means for managing access to an initial program load stored in read-only memory or the like
JP2000148467A (ja) * 1998-11-05 2000-05-30 Sharp Corp 情報処理装置、情報処理装置の基本システムプログラム書換方法及び情報処理装置の基本システムプログラム書換プログラムを記録した記録媒体
US6571347B1 (en) 1999-05-24 2003-05-27 Winbond Electronics Corporation Apparatus and method for intelligent computer initiation program recovery
JP2001109629A (ja) 1999-10-05 2001-04-20 Toshiba Corp Ｃｐｕのブート制御装置及びブート制御方法
US6625730B1 (en) 2000-03-31 2003-09-23 Hewlett-Packard Development Company, L.P. System for validating a bios program and memory coupled therewith by using a boot block program having a validation routine
US6571310B1 (en) * 2000-04-20 2003-05-27 International Business Machines Corporation Method and apparatus for managing a heterogeneous data storage system
US6792556B1 (en) 2000-05-31 2004-09-14 Dell Products L.P. Boot record recovery
US6490668B2 (en) * 2000-12-15 2002-12-03 Hewlett-Packard Company System and method for dynamically moving checksums to different memory locations
TWI240864B (en) * 2001-06-13 2005-10-01 Hitachi Ltd Memory device
JP4434539B2 (ja) 2001-12-26 2010-03-17 富士通マイクロエレクトロニクス株式会社 プロセッサおよびそのブート方法
US6907522B2 (en) 2002-06-07 2005-06-14 Microsoft Corporation Use of hashing in a secure boot loader
JP2004021811A (ja) * 2002-06-19 2004-01-22 Hitachi Ltd 不揮発メモリを使用したディスク制御装置
US7017017B2 (en) * 2002-11-08 2006-03-21 Intel Corporation Memory controllers with interleaved mirrored memory modes
US7340638B2 (en) 2003-01-30 2008-03-04 Microsoft Corporation Operating system update and boot failure recovery
TWI243335B (en) 2003-09-04 2005-11-11 Htc Corp Booting method for performing warm boot or cold boot when CPU is down, and its computer system

Also Published As

Publication number Publication date
JP2005309580A (ja) 2005-11-04
US20050235138A1 (en) 2005-10-20
US20080046672A1 (en) 2008-02-21
US7644263B2 (en) 2010-01-05
US7287155B2 (en) 2007-10-23
DE602004003677T2 (de) 2007-10-04
EP1589427A1 (de) 2005-10-26
JP4544901B2 (ja) 2010-09-15
DE602004003677D1 (de) 2007-01-25

Similar Documents

Publication Publication Date Title
US7644263B2 (en) Storage control system and boot control system
JP4868216B2 (ja) ファームウェア更新回路およびファームウェア更新方法
US6505305B1 (en) Fail-over of multiple memory blocks in multiple memory modules in computer system
JP4110000B2 (ja) 記憶装置
JP2007058419A (ja) Ｐｌｄ上のメモリ内の情報に従って構築される論理回路を備えたストレージシステム
JPH10320135A (ja) 適応型電力障害リカバリシステム
JPH11272427A (ja) データ退避方法および外部記憶装置
US20040153738A1 (en) Redundancy management method for BIOS, data processing apparatus and storage system for using same
JPH07200191A (ja) ディスクアレイ装置
JP5103823B2 (ja) 情報処理装置および入出力要求制御方法
JP2007058873A (ja) 不揮発メモリを使用したディスク制御装置
JP2548475B2 (ja) アレイディスク装置のデータ復元量制御方法
JP2000293376A (ja) ブートプログラムの切替回路及び切替方法
US7430687B2 (en) Building-up of multi-processor of computer nodes
JP4066950B2 (ja) コンピュータシステムおよびその保守方法
JP2743756B2 (ja) 半導体ディスク装置
JP3311776B2 (ja) ディスクサブシステムにおけるデータ転送チェック方式
JP2904117B2 (ja) 装置記憶部の冗長化方法及び装置
JP2008217811A (ja) 不揮発メモリを使用したディスク制御装置
JP2853593B2 (ja) ダウンロード装置
JP2002140206A (ja) 待機冗長２重化制御装置及びそのアプリケーションプログラム開発装置
JPH08185354A (ja) メモリ管理装置
JPH05120153A (ja) 交代メモリ制御方式
KR20030068663A (ko) 이중화 보드간의 비휘발성 메모리 정보 동기화 장치 및 방법
JP2005128629A (ja) データベースの更新方式

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20041108

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL HR LT LV MK

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

RIN1 Information on inventor provided before grant (corrected)

Inventor name: MINOWA, NOBUYUKI, HITACHI LTD., INTEL. PROP. GROUP

Inventor name: FUJII, MASANORI, HITACHI, LTD., INTEL. PROP. GROUP

Inventor name: INOUE, YASUO, HITACHI, LTD., INTEL. PROP. GROUP

AKX Designation fees paid

Designated state(s): DE FR GB

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

RIN1 Information on inventor provided before grant (corrected)

Inventor name: FUJII, MASANORIC/O HITACHI LTD., INTL. PROP. GP.

Inventor name: MINOWA, NOBUYUKIC/O HITACHI LTD., INTL. PROP. GP.

Inventor name: INOUE, YASUOC/O HITACHI LTD., INTL. PROP. GP.

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REF Corresponds to:

Ref document number: 602004003677

Country of ref document: DE

Date of ref document: 20070125

Kind code of ref document: P

ET Fr: translation filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20070914

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20080918

Year of fee payment: 5

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

Effective date: 20100630

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20091102

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20141015

Year of fee payment: 11

Ref country code: DE

Payment date: 20141014

Year of fee payment: 11

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 602004003677

Country of ref document: DE

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20151019

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20160503

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20151019