EP1579456A1 - Cellule de memoire sram et procede pour compenser un courant de fuite circulant dans la cellule de memoire sram - Google Patents

Cellule de memoire sram et procede pour compenser un courant de fuite circulant dans la cellule de memoire sram

Info

Publication number
EP1579456A1
EP1579456A1 EP03811723A EP03811723A EP1579456A1 EP 1579456 A1 EP1579456 A1 EP 1579456A1 EP 03811723 A EP03811723 A EP 03811723A EP 03811723 A EP03811723 A EP 03811723A EP 1579456 A1 EP1579456 A1 EP 1579456A1
Authority
EP
European Patent Office
Prior art keywords
memory cell
semiconductor memory
leakage current
transistor
electrically connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03811723A
Other languages
German (de)
English (en)
Inventor
Thomas Nirschl
Yannick Martelloni
Bernhard Park Side The Ritz WICHT
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1579456A1 publication Critical patent/EP1579456A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only

Definitions

  • the invention relates to a semiconductor memory cell, in particular an SRAM memory cell, and a method for compensating for a leakage current flowing into the SRAM memory cell.
  • SRAM static memories
  • SRAMs are both manufactured as individual components and integrated on a chip in addition to other components.
  • the area share of SRAMs in microprocessors and in other highly complex logic circuits is up to 50%. Therefore, careful design of the SRAM and the peripheral circuits is of great importance in many applications.
  • An SRAM is a random access memory.
  • One speaks of a static memory since the electrically written information can be stored indefinitely as long as the supply voltage is not switched off.
  • a known SRAM memory cell (FIG. 1) has a static latch, a static latch being the simplest form of a bistable circuit and being constructed from two cross-coupled inverters.
  • the first inverter has an n-channel transistor M1 and a p-channel transistor M3.
  • the second inverter of the memory cell has an n-channel transistor M2 and a p-channel transistor M4.
  • the cross coupling of the inverters ensures that the output of one inverter controls the input of the other inverter.
  • the two CMOS inverters are electrically connected to complementary bit lines BL and BLQ via two NMOS selection transistors M5 and M6.
  • the use of complementary bit lines BL and BLQ increases the reliability and reduces the sensitivity to fluctuations in the component parameters.
  • the selection transistors M5 and M6 are each with their gate Connections electrically connected to a first word line WLl.
  • the selection transistor M5 is connected to a first storage node K1 of the memory cell and the selection transistor M6 is connected to a second storage node K2 of the memory cell.
  • the SRAM memory cell shown in FIG. 1 is referred to as a so-called 6T memory cell. Because of the "active load elements" M3 and M4, this cell type only requires relatively short times for reading or writing data.
  • Another embodiment of an SRAM memory cell, not shown, is the so-called ⁇ SRAM memory cell, in which the transistors M3 and M4 are replaced by passive load elements. The proposed concept can also be used for other types of memory cells.
  • the mode of operation of the memory cell with active load elements according to FIG. 1 is explained on the basis of the voltage profiles of signals flowing through the first word line WL1 and the bit line pair BL and BLQ shown in FIG. 2.
  • Signals impressed from the outside are represented in FIG. 2 by trapezoidal courses, while the generally weaker ones
  • a first logic state "1" is defined by a high potential on the left side of the memory cell in the memory node K1. It follows from this that the transistor M1 blocks. A write or read process is triggered by the transistors M5 and M6 being activated, controlled by the first word line WL1. A write operation is carried out by drivers pulling the signal on the bit line BL and on the complementary bit line BLQ to the logic levels “0” or “1”. In order to write a first logic state "1" into the memory cell, the complementary bit line BLQ must have a logic state "0" according to the definition assumed above.
  • the storage node (K1 or K2) of the storage cell that is to be brought to a low potential must be brought from the outside of the storage cell to a voltage lower than the switching threshold of the opposite inverter.
  • the other node should be above a voltage threshold.
  • bit lines BL and BLQ are first precharged to a precharge voltage.
  • the precharge voltage is selected in such a way that the cell is not unwantedly written according to the previously described mechanisms. If this is the case, one speaks of a non-destructive reading.
  • a current flows via transistors M5 and M3 as well as M6 and M2 depending on the precharge voltage.
  • the storage node K2 must be brought to a potential lower than the switching threshold of the opposite inverter. It follows that the resistance formed by transistor M6 must be approximately 3 times that of the transistor M2. The writing and reading of the logic state "0" into and out of the memory cell takes place accordingly.
  • bit line pair BL and BLQ are precharged to a high potential (alternatively, these bit lines can also be precharged to a low potential or to any reference voltage). If the word line is selected, the selection transistors connected to the memory cell are switched on. One of the memory nodes of the memory cell has a memory state "0" and the other memory node has a memory state "1". The storage node which has the low storage state "0” pulls the bit line connected to this storage node to a low potential (logic state "0").
  • a sense amplifier accelerates the reading and amplifies the drop in the signal on the bit line connected to the voltage node having the memory state "0" from the state with a high potential to the state with a low potential and at the same time maintains the high potential state on the second bit line ,
  • the sense amplifier only begins to work or read a state when a certain voltage difference between the two bit lines BL and BLQ occurs.
  • the current of the memory cell can also be amplified directly.
  • a write operation of a memory state into a memory cell can generally be carried out as follows.
  • One of the bit lines is precharged to a high potential and the other bit line of the bit line pair is precharged to a low potential. If the memory cell into which a memory state is to be written is selected via a word line, and the memory states in the two memory nodes of the memory cell correspond to the potential states on the bit lines with which the respective memory node of the memory cell is connected, the storage states in the two storage nodes remain unchanged. However, if the storage nodes have storage states that are different from the potentials of the bit lines to which one of the storage nodes is connected, the storage states in the storage nodes are changed.
  • the storage node that has a logical storage state "1" (high potential) is thereby pulled to a logical storage state "0" (low potential).
  • the state of the other storage node is set from a logical storage state "0" (low potential) to a logical storage state "1" (high potential).
  • a disadvantage of the known semiconductor memory cells, in particular the SRAM memory cells, is the problem that leakage currents flow into the memory cell, in particular if the memory cell of a memory cell array is connected to a plurality of memory cells in the non-selected state.
  • One way to keep the leakage current as low as possible is to select the threshold voltage of the transistors of the memory cell relatively high.
  • this in turn results in the disadvantage that the reading out or writing in of a memory state from or into the memory cell proceeds more slowly and the course of a storage process is significantly deteriorated.
  • a large number of memory cells Z 0 to Z N are usually connected to a bit line pair BL and BLQ. If the memory state of the memory cell Z 0 is now read out, a current i c flows into the cell in the exemplary embodiment shown. The current on the bit line BLQ therefore decreases and has the value I-ic. At the same time, leakage currents i L ⁇ to im flow from the bit line BL into the corresponding cells Z x to Z N , which are each in the non-selected state. This results in a total leakage current i L , whereby a current I-ii from the bit line BL ne current evaluation circuit SBS flows.
  • the current difference between the two bit lines BL and BLQ is determined by means of this current evaluation circuit SBS or this sense amplifier. These current evaluation circuits SBS use these current signals directly to determine the memory state in the memory cell to be read out. Voltage sense amplifiers, on the other hand, use the voltage difference between the two bit lines, which is generated between the two bit lines BL and BLQ when the selected memory cell is read out. Both the current evaluation circuit SBS and a voltage reading amplifier circuit evaluate a read memory state from a memory cell only when a certain voltage difference .DELTA.U or a certain current difference .DELTA.l occurs between the two bit lines. As shown in Fig. 4, the memory state of the read out
  • Memory cell Z 0 can only be evaluated by the current evaluation circuit SBS (FIG. 3) when a current difference> ⁇ l occurs between the bit lines BL and BLQ. If no leakage current i L ⁇ to i N would flow into the unselected memory cells Z 1 to Z N in FIG. 3, the current on the bit line BL would have a constant value I.
  • a 6T SRAM memory cell and a method for reading out this memory cell are known from US Pat. No. 6,181,608 B1 with which the leakage current problem is to be prevented.
  • the SRAM memory cell has selection transistors which have a lower threshold voltage than the transistors of the two inverters of the SRAM memory cell.
  • the integrated circuit in which the SRAM memory cells are arranged has a control circuit for checking the voltages of the word lines. This control circuit is connected to all word lines of the integrated circuit. The signals on the word lines are set by this control circuit in such a way that the leakage current which flows into the non-selected memory cells is to be minimized.
  • the gate connections of the selection transistors of the non-selected memory cells are not led to ground potential V S s, but these gate connections of the selection transistors are "understeered” by the control circuit applying a negative voltage in the range from a few to a few hundred millivolts to the word lines connected to the non-selected memory cells.
  • the disadvantage of this circuit arrangement is that a relatively complex and complex circuit structure for checking these word lines and their signals is necessary, and secondly the "understeering" of the word lines that are connected to the unselected memory cells is relatively difficult and can only be carried out very imprecisely.
  • the leakage currents that flow into the individual non-selected memory cells cannot be eliminated as a result and have a significant influence on reading out or writing into the memory cell.
  • the leakage current compensation circuit has two p-channel transistors, which are arranged symmetrically between the bit lines of the bit line pair, with each of these two p-channel transistors being used to detect the leakage current on the bit line with which the respective p-channel transistor is connected. Furthermore, this leakage current compensation circuit has two further p-channel transistors, which are also formed in a symmetrical arrangement between the bit lines of the bit line pair. By means of these two additional p-channel transistors, a current which is of the magnitude of the detected leakage current is applied to the respective bit line in order to compensate for the detected leakage current. This compensation takes place by means of the two additional p-channel transistors during a read / write operation of a memory cell of the memory cell array.
  • the four p-channel transistors are controlled such that the detected leakage current is stored in a capacitance of the leakage current compensation circuit and the stored leakage current flows to the bit line by means of an activation signal for activating the second p-channel transistors.
  • the leakage current is therefore first converted into a voltage and stored in a capacitance of the leakage current compensation circuit.
  • a compensation current is generated from this, which is applied to the corresponding bit line for compensation of the leakage current.
  • This circuit arrangement for leakage current compensation is very complex and very complex. Another disadvantage of this arrangement is the large capacity that is required to store the leakage current. Furthermore, this circuit arrangement only detects the total leakage current, that is to say the sum of all those leakage currents which flow into the non-selected memory cells of the memory cell array. With this compensation circuit, it is not possible to compensate for this leakage current separately in each individual memory cell into which a certain leakage current flows.
  • a semiconductor memory cell according to the invention is designed in particular as an SRAM memory cell and is electrically connected to at least one data line.
  • the semiconductor memory cell has at least one storage node.
  • the semiconductor memory cell comprises at least one selection transistor of a first line type, which is electrically connected to the first memory node of a first data line and a first word line.
  • An essential idea of the invention is that the semiconductor memory cell comprises means for compensating for a leakage current flowing into the semiconductor memory cell. These means for compensating the leakage current are designed such that a current corresponding to the leakage current flows into the semiconductor memory cell.
  • a simply constructed semiconductor memory cell can be constructed, with which the leakage current, which flows into the semiconductor memory cell in particular when the memory cell is not selected, can be compensated for quickly and with little effort. Regardless of how large this leakage current is, a current corresponding to the leakage current is always generated, which is also added to the semiconductor ter memory cell flows. Furthermore, the means according to the invention for compensating for the leakage current flowing into the semiconductor memory cell allow the leakage current in each individual semiconductor memory cell to be compensated separately or the size thereof and to be taken into account as an easy-to-determine variable during evaluation.
  • the means for compensating the leakage current are designed such that at least one additional electrical connection between these means of the semiconductor memory cell and one of the ones connected to the semiconductor memory cell Data lines are present. In this way it can be achieved that regardless of the storage states of the semiconductor memory cell stored in the respective storage nodes, a current of the same magnitude as the leakage current is injected. This is particularly advantageous for the compensation of a leakage current which flows into this semiconductor memory cell when the semiconductor memory cell is not selected.
  • the means for compensating the leakage current are electrically connected to at least one of the storage nodes of the semiconductor memory cell.
  • the means for compensating the leakage current are advantageously connected to the first data line and to ground potential.
  • the means for compensating for the leakage current flowing into the semiconductor memory cell have a first transistor of a first conductivity type, which is connected with its source connection the first data line and its gate connection is electrically connected to ground potential.
  • this first transistor is connected with its drain connection to the second storage node of the semiconductor memory cell and always has the closed or conductive state.
  • the leakage currents flowing into the non-selected memory cells of a memory cell array with a plurality of semiconductor memory cells are thereby compensated for in an efficient and effective manner, and the reading or writing of a memory state from or into a selected semiconductor memory cell of the memory cell array can be carried out quickly and reliably, since a read / write process in a selected semiconductor memory cell is no longer falsified or delayed by the leakage currents flowing into the non-selected semiconductor memory cell.
  • the leakage current of all the memory cells connected to the data lines is known, so that the leakage currents of the non-selected memory cells are subtracted from a reference current flowing through the data line, and a known constant value is thereby available. A memory state can therefore be read out or written into a selected memory cell in a simple and very precise manner.
  • the semiconductor memory cell has a second selection transistor of a first line type, which is electrically connected with its drain connection to the second storage node and with its source connection to a second data line. is bound. It can be provided that the second selection transistor is electrically connected with its gate connection to the first word line. It can also be provided that the second selection transistor is electrically connected with its gate connection to a second word line.
  • the first and the second data line are preferably designed as complementary bit lines, as a result of which the data can be transferred more reliably and at a higher speed than a single data line or bit line.
  • a further advantageous embodiment of the invention is characterized in that the means for compensating for the current flowing into the semiconductor memory cell, in particular the first leakage current flowing from the first data line into the first memory node when the semiconductor memory cell is not selected, and / or the second leakage current flowing from the second data line into the second storage node, are electrically connected to the first and second data lines and to the first and second storage nodes of the semiconductor memory cell. Regardless of which leakage current components flow from the two data lines into the semiconductor memory cell, compensation of these leakage current components can be achieved in a simple and reliable manner.
  • the means for compensating for the leakage current flowing into the semiconductor memory cell comprise the first transistor, which has a drain connection to the second storage node and a source connection to the first data line to produce a first additional electrical connection is electrically connected between the semiconductor memory cell, in particular the second storage node, and the first data line.
  • the semiconductor memory cell or the means for compensating for the leakage current further comprises a second transistor of the first conductivity type include. This second transistor has a drain connection with the first storage node, with its source connection with the second data line and with its gate connection with ground potential for generating a second additional electrical connection between the semiconductor memory cell and one with the memory cell already connected data line, electrically connected.
  • the leakage currents flowing through the data lines and the selection transistors into the storage nodes connected to them can be compensated for quickly and very precisely, since currents corresponding to the leakage currents flow from the respectively complementary data lines into the semiconductor memory cell through the first and the second additional electrical connection. Because of this symmetrical arrangement of the means for compensating for the leakage current or the leakage current components, an equally large current corresponding to the leakage current always flows into the memory cell on the data lines connected to the memory cell. This applies in particular to a differential embodiment of the semiconductor memory cell.
  • the semiconductor memory cell is designed as a 6T SRAM memory cell and has a first and a second inverter, each of these two inverters comprising a transistor of a first and a transistor of a second conductivity type and the two inverters between the first and the second Storage nodes are cross-coupled.
  • the two transistors of the first inverter are electrically connected to the first storage node and the two transistors of the second inverter are electrically connected to the second storage node of the semiconductor memory cell.
  • the semiconductor memory cell is designed as a 4T SRAM memory cell.
  • the memory cell concept according to the invention is not limited to SRAM memory cells, but is possible for all semiconductor memory cells that only have one selection transistor and two memory nodes exhibit. It is also possible that the memory cell concept according to the invention is applied to semiconductor memory cells with at least two selection transistors and a storage node.
  • a first additional electrical connection between the semiconductor memory cell and a data line already electrically connected to the semiconductor memory cell In a method according to the invention for compensating for a leakage current flowing into the semiconductor memory cell, in particular a leakage current flowing into the memory cell in the non-selected state of the semiconductor memory cell, a first additional electrical connection between the semiconductor memory cell and a data line already electrically connected to the semiconductor memory cell.
  • the first additional electrical connection between the semiconductor memory cell and the data line electrically connected to the semiconductor memory cell is advantageously produced by means of a transistor which is always operated in the closed or conductive state.
  • a first selection transistor of the semiconductor memory cell is preferably connected to a first data line and a first memory node of the semiconductor memory cell and the first transistor is electrically connected to the first data line and a second memory node of the semiconductor memory cell.
  • a second additional electrical connection is advantageously formed between the semiconductor memory cell and one of the data lines electrically connected to the semiconductor memory cell, the first additional electrical connection to a first and the second additional electrical connection to a second data line being produced.
  • the second additional electrical connection between the semiconductor memory cell and the second data line connected to the semiconductor memory cell is generated by means of a second transistor which is always operated in the closed state.
  • a second selection transistor of the semiconductor memory cell is preferably electrically connected to the second data line and a second memory node of the semiconductor memory cell and the second transistor is electrically connected to the second data line and a first memory node of the semiconductor memory cell.
  • leakage currents flowing from the first and / or second data line into the first or second storage node are compensated for by a current from the second or first data line corresponding to the leakage currents via the second or first additional electrical connection flows into the first and second storage nodes, respectively.
  • FIG. 2 shows a signal curve on a word line and two complementary bit lines of a known memory cell according to FIG. 1 during write / read processes of logic states in or out of the SRAM memory cell;
  • FIG. 3 shows an arrangement of a plurality of memory cells in a memory cell array known from the prior art
  • Fig. 4 shows a time delay in
  • Reading a memory state from a memory cell when leakage currents occur shows a first exemplary embodiment of a semiconductor memory cell according to the invention
  • FIG. 6 shows a second exemplary embodiment of a semiconductor memory cell according to the invention.
  • FIG. 7 shows a third exemplary embodiment of a semiconductor memory cell according to the invention.
  • the semiconductor memory cell (FIG. 5) is designed as an SRAM memory cell and has two cross-coupled inverters which are connected to supply voltage potential V DD and ground potential V SS .
  • the first inverter has an n-channel transistor M1 and a p-channel transistor M3.
  • the second inverter comprises an n-channel transistor M2 and a p-channel transistor M4.
  • a first storage node K1 is arranged between the two transistors M1 and M3 and a second storage node K2 of the SRAM memory cell is arranged between the transistors M2 and M4.
  • a selection transistor M5 is connected with its drain connection to the first storage node K1, with its source connection with a first bit line BL and with its gate connection with a first word line WL1. Furthermore, the SRAM memory cell has an n-channel transistor M7, which with its drain connection to the second storage node K2 and the source connection of the transistor M2
  • Source terminal is electrically connected to the first bit line BL, and its gate terminal connected to ground potential V ss.
  • This transistor M7 which is always in the closed state, is used to produce a first additional electrical connection between the first bit line BL and the second memory node K2 of the SRAM memory cell.
  • Memory cell (word line WL1 at low potential) blocks the selection transistor M5.
  • a known reference current I REF is applied to the bit line BL.
  • a larger or smaller leakage current flows into the semiconductor memory cell.
  • a logical state “0” is stored in the storage node K1 and a logical state “1” is stored in the storage node K2.
  • a large leakage current therefore flows from the bit line BL via the selection transistor M5 into the storage node Kl (large in comparison to the leakage current which would flow into the storage node if the logic state "1" was stored in the storage node Kl) and via the transistor Ml.
  • Storage states in the storage nodes K1 and K2 always generate a current corresponding to the leakage current, which flows into the non-selected state of the memory cell and thus virtually compensates for the leakage current by generating it in each cell and thus as a known variable in the further evaluation can be treated. Therefore, in this exemplary embodiment, the flow is compensated for as a compensation Leakage current of equal magnitude understood in the memory cell via the transistors M5 and M7.
  • the exemplary embodiment of the SRAM memory cell shown in FIG. 5 can be used for single-ended write and read processes. If one of these two SRAM memory cells is selected for a read / write operation in a memory cell array with at least two SRAM memory cells designed according to FIG. 5, its memory state can be read out via the first bit line BL or a memory state can be written.
  • the SRAM memory cell is constructed in accordance with the SRAM memory cell in FIG. 5 and additionally has a second selection transistor M6, which has a drain connection to the second storage node K2 and a source connection to a second one first bit line is complementary bit line BLQ and its gate connection is electrically connected to a second word line WL2.
  • This exemplary embodiment of the SRAM memory cell according to the invention has a 6T SRAM memory cell as the core cell.
  • This embodiment of the SRAM memory cell can be used for single-ended read operations and for differential write operations. Only the first word line WL1 is set to high potential for write operations, for
  • an n-channel transistor M8 is arranged, with its drain connection with the first storage node K1, with its source connection with the second Bit line BLQ and with its gate connection is electrically connected to ground potential V S s.
  • the bit line BL is electrically connected to both the first and the second storage node via the transistors M5 and M7, and the bit line BLQ is also connected to the two storage nodes K1 and K2 via the transistors M6 and M8.
  • the second selection transistor M6 is not electrically connected to a second word line WL2 but to the first word line WL1, to which the first selection transistor M5 is also connected.
  • the transistor M8 connected to the transistor Ml and the bit line BLQ is pulled to the potential of the node to which the transistors Ml and M8 are connected, which is changed by the leakage current Leakage current corresponding to current flowing into node K1 is generated and flows to ground from bit line BLQ via transistor M8 and transistor M1, so that essentially the same current flows from both bit lines BL and BLQ into the semiconductor memory cell from the bit line BLQ into the storage node K2, in which the logical State “1” is stored, this leakage current being negligible in comparison to the leakage current that is negligible in the storage node K 1 in which the logic state “0” is stored.
  • the invention can prevent the disruptive influence of the leakage current when evaluating memory states in memory cells, in particular SRAM memory cells, or performing read / write operations of memory states in or out of a semiconductor memory cell.
  • a leakage current that occurs is not suppressed or reduced by the invention, but rather a compensation current corresponding to the leakage current is generated, which flows into the semiconductor memory cell and corresponds in size to the leakage current.
  • the invention thus achieves separate compensation of the leakage current flowing into the respective semiconductor memory cell in each individual semiconductor memory cell of a memory cell array.
  • the leakage current is thus not suppressed, but a compensation current corresponding to the leakage current is generated, which flows into the semiconductor memory cell and generates a constant additional current in both storage nodes, that is to say on both sides of the memory cell (in the case of a differential embodiment), as a result of which What is achieved is that the absolute value of the current i c flowing into the selected memory cell is available in full size for the evaluation.
  • the current detected when evaluating a memory state via a bit line or via two complementary bit lines is not falsified or reduced by the leakage current of the non-selected memory cells.
  • the leakage current is compensated and is thus acted on as an additional known signal on the data lines in the case of differential evaluations or differently implemented circuit arrangements or is detected as a constant variable in the evaluation in the case of single-ended evaluations or single-ended circuit arrangements.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne une cellule de mémoire SRAM qui comprend au moins un point mémoire (K1, K2) et au moins un transistor de sélection (M5) qui est relié électriquement au point mémoire (K1, K2), à une première ligne de bit (BL) et à une première ligne de mot (WL1). La cellule de mémoire SRAM selon l'invention comprend également des moyens (M7, M8) servant à compenser un courant de fuite circulant dans la cellule de mémoire SRAM et réalisés de sorte qu'un courant correspondant au courant de fuite s'écoule dans la cellule de mémoire SRAM. Selon un mode de réalisation de l'invention, ces moyens sont réalisés sous forme de transistor (M7) qui est relié électriquement à la première ligne de bit (BL) et au deuxième point mémoire (K2), le premier point mémoire (K1) étant relié au transistor de sélection (M5).
EP03811723A 2002-11-26 2003-10-24 Cellule de memoire sram et procede pour compenser un courant de fuite circulant dans la cellule de memoire sram Withdrawn EP1579456A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10255102A DE10255102B3 (de) 2002-11-26 2002-11-26 SRAM-Speicherzelle mit Mitteln zur Erzielung eines vom Speicherzustand unabhängigen Leckstroms
DE10255102 2002-11-26
PCT/DE2003/003551 WO2004049348A1 (fr) 2002-11-26 2003-10-24 Cellule de memoire sram et procede pour compenser un courant de fuite circulant dans la cellule de memoire sram

Publications (1)

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EP1579456A1 true EP1579456A1 (fr) 2005-09-28

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EP03811723A Withdrawn EP1579456A1 (fr) 2002-11-26 2003-10-24 Cellule de memoire sram et procede pour compenser un courant de fuite circulant dans la cellule de memoire sram

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US (1) US7504695B2 (fr)
EP (1) EP1579456A1 (fr)
JP (1) JP2006507617A (fr)
CN (1) CN100557707C (fr)
DE (1) DE10255102B3 (fr)
WO (1) WO2004049348A1 (fr)

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JP2006507617A (ja) 2006-03-02
WO2004049348A1 (fr) 2004-06-10
CN100557707C (zh) 2009-11-04
US7504695B2 (en) 2009-03-17
CN1717747A (zh) 2006-01-04
DE10255102B3 (de) 2004-04-29
US20050281109A1 (en) 2005-12-22

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