EP1559131A2 - Dispositif a semiconducteurs - Google Patents

Dispositif a semiconducteurs

Info

Publication number
EP1559131A2
EP1559131A2 EP03779674A EP03779674A EP1559131A2 EP 1559131 A2 EP1559131 A2 EP 1559131A2 EP 03779674 A EP03779674 A EP 03779674A EP 03779674 A EP03779674 A EP 03779674A EP 1559131 A2 EP1559131 A2 EP 1559131A2
Authority
EP
European Patent Office
Prior art keywords
lines
semiconductor arrangement
type
arrangement according
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03779674A
Other languages
German (de)
English (en)
Inventor
Dirk Fuhrmann
Reidar Lindstedt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1559131A2 publication Critical patent/EP1559131A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections

Definitions

  • the invention relates to a semiconductor arrangement according to claim 1.
  • the basic structure of a DRAM device is in
  • a relatively wide logic area is formed along a central axis, which includes so-called address multiplexers, address generators, read and write amplifiers, etc.
  • connection contacts the so-called pads, are arranged in this area.
  • Word and bit lines are arranged in a rectangular grid on the chip.
  • additional logic areas are provided at right angles to this, which divides the chip into individual memory banks.
  • an area for detection amplifiers in addition to the individual word lines, an area for detection amplifiers, so-called “sense amplifiers”, is arranged at a uniform distance, ie after a predetermined number of word lines.
  • sense amplifiers With the steadily increasing number of memory cells and the simultaneously increasing number of cycles, it is becoming increasingly difficult to manage the access times to the individual memory cells. This means that the reading or writing of a memory cell which is arranged spatially close to the logic must be as reliable as that of a memory cell which is arranged far away from the logic.
  • the running times are very different, so that safe, ie error-free, management of the accesses can only be made possible with a high technical outlay at high clock rates and thus low access times.
  • the invention is therefore based on the object of providing a semiconductor arrangement which, with a high density of circuit elements, reliably ensures easy access to individual elements even at a high clock rate.
  • FIG. 1 shows an exemplary embodiment of a semiconductor arrangement with memory cells
  • FIG. 2 signal directions of the exemplary embodiment shown in FIG. 1,
  • FIG. 3 shows a development of the exemplary embodiment shown in FIG. 1,
  • FIG. 4 shows an exemplary arrangement of DRAM cells in the exemplary embodiment
  • FIG. 5 further exemplary line arrangements.
  • FIG. 1 shows an exemplary embodiment of a semiconductor chip 1 which is delimited by an edge 12 and preferably has a rectangular shape.
  • the semiconductor chip 1 shown is intended to be a DRAM memory.
  • Memory cells 2 are arranged around the central region 5, the arrangement being designed such that the memory cells are arranged along word lines 3 which are designed in the form of concentric rings. There are therefore a number of m word lines 3.
  • FIG. 1 it is provided that, after several word lines, an area 7 is additionally provided for detection amplifiers.
  • bit lines 4 Radially extending bit lines 4 are now shown starting from the central region 5. For the sake of clarity, only a few bit lines 4 are shown in a segment section in FIG. In fact, the bit lines 4 are arranged evenly distributed over the entire circular area. In the illustrated embodiment, the
  • Bit lines 4 arranged radially aligned with the center of the central area 5.
  • bit lines are not aligned towards a central point. This means that an imaginary extension of the bit lines to the center would not run to the center, but past it.
  • bit lines 4 and word lines 3 are shown symbolically arranged around a central area 5.
  • the invention is not restricted to straight bit line routing.
  • a single or multiple curved course can also be implemented. Accordingly, it is not necessary that the word lines have a circular shape.
  • an elliptical course is just like comparable arrangements in which the word lines around the central area are led around. This variant is also indicated in Figure 5.
  • the memory cells 2 arranged in the spaces between the word and bit lines are arranged at the intersection of word and bit lines. How the exact arrangement z. B. a DRAM cell is to be provided at a later time with reference to Figure 4a u. 4b explained by way of example.
  • outer additional surfaces 6a, 6b, 6c and 6d are provided in the four corners of the chip 1 shown in FIG. Without the connection surfaces being shown in detail, it is easy to see that there is sufficient space for them.
  • the additional areas 6a to 6d are only shown symbolically for the really required additional areas. The exact shape and extent depends on the actual space requirement.
  • logic circuit parts can be arranged in the outer additional surfaces 6a to 6d, but also circuit parts, such as voltage supplies, for example.
  • connection surfaces can also be formed in the central area 5.
  • each memory cell array is thus arranged at a minimal distance from logic circuits if they are formed in the inner region A and that all memory cells can be driven from the inner region A along a concentric circle with the same signal propagation time. This shows that the control of the entire memory cell array in this concentric arrangement is simplified in terms of the timing, the so-called “timing”.
  • FIG. 3 shows a further development of the exemplary embodiment shown in FIG. 1, the same circuit parts being provided with the same reference symbols. Therefore, in order to avoid repetition, a comprehensive description is omitted again.
  • FIG. 3 illustrates four additional inner surfaces 8a, 8b, 8c and 8d in FIG. 3, which extend from the logic region 5 to the chip edge 12.
  • the inner additional areas 8a to d are shown as rectangular areas and divide the chip, which need not necessarily be square as shown, into four segments, which can correspond to the usual division of memory cell banks.
  • the rectangular shape of the inner additional surfaces 8a to 8d is not absolutely necessary. Nor is it necessary that they are actually formed up to the physical edge 12 of the chip 1.
  • These inner additional surfaces 8a to 8d can be provided to provide space for additional logic circuits or connection surfaces. Furthermore, it is possible for individual additional areas to be omitted or for additional areas to be added.
  • FIG. 4a shows a section of the top view of a memory cell array on an enlarged scale. Starting from an area l x which is provided for detection amplifiers, bit lines 4 are shown, the exemplary explanation relating to bit lines j, 4j + 1 and 4j + 2. Word lines 3 are arranged concentrically to the area 7 X and run outwards, the explanations relating to the word lines 3i, 3i + 1 and 3i + 2.
  • an active region 13 for two selection transistors T1 and T2 is formed between two cell capacitors C1 and C2.
  • the respective transistor channel is formed under the word lines 3i + 1 and 3i + 2.
  • a bit line contact 9 connects the bit line 4j + 1 between the two selection transistors T1 and T2 with the active region 12.
  • This arrangement which comprises two memory cells, is shown again for comparison in FIG. 4b in cross section along the section line X-Y.
  • the capacitors Ci and C shown in the illustrated embodiment are so-called "deep trench (DT) storage capacitors".
  • the selection transistors can be designed using vertical or horizontal technology.
  • bit line contacts are thus opposite the neighboring one Bit lines arranged offset by a memory cell size enable a very high memory cell density.
  • the bit lines 4 run radially from the central region 5 to the outer region and the word lines 3 run on concentric circles, ring-shaped additional surfaces 7 being provided at predetermined intervals, which are used for the arrangement of the detection amplifiers and for example for the supply of the voltage supply. are provided.
  • An arrangement in which the bit lines are replaced by the word lines is not shown, but is fundamentally possible to the same extent. This would mean that the word lines run radially outwards and the bit lines on concentric circles, the areas required for the detection amplifiers or the voltage supply on segment areas then also being arranged radially outwards after a predetermined number of word lines.
  • the actual chip area is square. If there is additional space required outside, a rectangular chip area can also be realized.

Landscapes

  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un dispositif à semiconducteurs, comportant plusieurs champs d'éléments individuels (2) disposés sur une puce a semiconducteurs (1), le long de lignes (3) d'un premier type, et de lignes (4) d'un deuxième type. Les lignes du premier ou du deuxième type s'étendent d'une zone intérieure (A ; 5) vers une zone extérieure (B), et les lignes de l'autre type s'étendent autour de la zone intérieure (A ; 5).
EP03779674A 2002-11-08 2003-10-27 Dispositif a semiconducteurs Withdrawn EP1559131A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10252058 2002-11-08
DE10252058A DE10252058A1 (de) 2002-11-08 2002-11-08 Halbleiteranordnung
PCT/DE2003/003567 WO2004042800A2 (fr) 2002-11-08 2003-10-27 Dispositif a semiconducteurs

Publications (1)

Publication Number Publication Date
EP1559131A2 true EP1559131A2 (fr) 2005-08-03

Family

ID=32185374

Family Applications (1)

Application Number Title Priority Date Filing Date
EP03779674A Withdrawn EP1559131A2 (fr) 2002-11-08 2003-10-27 Dispositif a semiconducteurs

Country Status (6)

Country Link
US (1) US7136295B2 (fr)
EP (1) EP1559131A2 (fr)
CN (1) CN1711641A (fr)
AU (1) AU2003287853A1 (fr)
DE (1) DE10252058A1 (fr)
WO (1) WO2004042800A2 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004028076A1 (de) * 2004-06-09 2006-01-05 Infineon Technologies Ag Integrierter Halbleiterspeicher mit einem Speicherbereich und einem Zentralbereich

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6120349A (ja) * 1984-07-06 1986-01-29 Hitachi Ltd Ｌｓｉ集合体
US4731643A (en) * 1985-10-21 1988-03-15 International Business Machines Corporation Logic-circuit layout for large-scale integrated circuits
JPH01128458A (ja) 1987-11-13 1989-05-22 Fujitsu Ltd 半導体記憶装置
JPH02268439A (ja) * 1989-04-10 1990-11-02 Hitachi Ltd 半導体集積回路装置
JPH0474465A (ja) 1990-07-17 1992-03-09 Nec Corp 半導体記憶装置
JP3185271B2 (ja) * 1991-09-13 2001-07-09 日本電気株式会社 半導体集積回路
JPH08116036A (ja) * 1994-10-14 1996-05-07 Hitachi Ltd メモリチップ
US5880492A (en) * 1995-10-16 1999-03-09 Xilinx, Inc. Dedicated local line interconnect layout
KR100213249B1 (ko) * 1996-10-10 1999-08-02 윤종용 반도체 메모리셀의 레이아웃
JP3347020B2 (ja) * 1997-07-09 2002-11-20 株式会社ビー・エム 水処理方法およびその装置
US6154051A (en) * 1998-11-05 2000-11-28 Vantis Corporation Tileable and compact layout for super variable grain blocks within FPGA device
DE10257665B3 (de) * 2002-12-10 2004-07-01 Infineon Technologies Ag Halbleiterspeicher mit einer Anordnung von Speicherzellen

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2004042800A2 *

Also Published As

Publication number Publication date
AU2003287853A1 (en) 2004-06-07
DE10252058A1 (de) 2004-05-27
AU2003287853A8 (en) 2004-06-07
WO2004042800A3 (fr) 2004-08-05
US7136295B2 (en) 2006-11-14
US20050247959A1 (en) 2005-11-10
CN1711641A (zh) 2005-12-21
WO2004042800A2 (fr) 2004-05-21

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