EP1557032A1 - Capteur optoelectronique - Google Patents

Capteur optoelectronique

Info

Publication number
EP1557032A1
EP1557032A1 EP03753208A EP03753208A EP1557032A1 EP 1557032 A1 EP1557032 A1 EP 1557032A1 EP 03753208 A EP03753208 A EP 03753208A EP 03753208 A EP03753208 A EP 03753208A EP 1557032 A1 EP1557032 A1 EP 1557032A1
Authority
EP
European Patent Office
Prior art keywords
transistor
voltage
diode
photodiode
gate voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03753208A
Other languages
German (de)
English (en)
Inventor
Martin Wäny
Peter Mario Schwider
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Photonfocus AG
Original Assignee
Photonfocus AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Photonfocus AG filed Critical Photonfocus AG
Publication of EP1557032A1 publication Critical patent/EP1557032A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
    • H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
    • H04N3/14—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices
    • H04N3/15—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices for picture signal generation
    • H04N3/155—Control of the image-sensor operation, e.g. image processing within the image-sensor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H04N25/571—Control of the dynamic range involving a non-linear response
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H04N25/571—Control of the dynamic range involving a non-linear response
    • H04N25/573—Control of the dynamic range involving a non-linear response the logarithmic type
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Definitions

  • the present invention relates to an optoelectronic sensor comprising at least one photodiode which can be connected via a first transistor to a first potential.
  • CMOS complementary metal-oxide-semiconductor
  • This technology allows the realization of non-linear characteristics of the output signal with respect to the input signal, in contrast to CCD technology.
  • a non-linear characteristic makes it possible to process a higher contrast within an image with the same grayscale resolution, without saturation of the image occurring, as is possible with a linear characteristic curve.
  • pulsed light sources flash illumination
  • global shutter exposure control
  • the invention is therefore an object of the invention to provide an optoelectronic sensor with increased dynamic range and "global shutter" exposure control available. It is essentially a question of both limiting the sensitivity of the sensor at high light energies, and at the same time to allow an increase in sensitivity at low optical intensities.
  • the invention relates to an optoelectronic sensor comprising at least one photodiode, which can be connected via a first transistor or a first diode having a first potential.
  • the photodiode can also be connected via a second transistor to the input of a readout amplifier, wherein further between this second transistor and the input of the readout amplifier, a third transistor is arranged, via which the input of the readout amplifier with a second potential can be connected.
  • means (C2) are provided which allow a temporary storage of the integrated signal value up to the readout time.
  • the essence of the invention is therefore to combine the possibilities of increasing the sensitivity at low optical intensities with the possibilities of reducing the sensitivity of the sensor at high light energies while maintaining the "global shutter" exposure control
  • the invention provides a circuit which is suitable for integration in one or two-dimensional arrays of optoelectronic sensor elements (image sensors) and which allows non-linear characteristics, both by increasing the sensitivity for low-intensity optical signals, and by reducing the sensitivity for to realize high sensitivity optical signals.
  • the presented circuit can also be used in two-dimensional arrays and read out with the signal timing for double sampling.
  • the first and the second potential are at a substantially identical voltage level.
  • this circuit is not possible because the first potential in this case must be controlled to control the effective diode threshold voltage independently of the second potential.
  • the "sample and hold" element is preferably realized by the second transistor and the parasitic capacitances which are connected to the input of the readout buffer. These parasitic capacitances also form the conversion capacity in the amplification mode of my signals. To better control this conversion capacity, an additional ground potential can be connected to this node. This capacity is usually in the range of some femtofarads. In order to enable amplification of small signals, the total capacitance connected to the input of the readout buffer has to be smaller than the parasitic capacitance of the photodiode.
  • the output of the readout amplifier or readout buffer is connected to a column bus via a row select transistor.
  • all transistors used in the circuit are formed as MOS transistors.
  • the following description refers to an implementation with ⁇ -type MOS transistors ( ⁇ MOS), but the invention also covers the possible implementation with P-type MOS transistors or a combination of both transistor types.
  • ⁇ MOS ⁇ -type MOS transistors
  • PMOS transistors all voltages are to be inverted at the given location with respect to the ⁇ MOS transistor, as the expert Reader is well known and apparent.
  • a further preferred embodiment of the present invention is characterized in that the gate voltage of the second transistor is controlled such that in a first phase of the integration time of the current generated by the photodiode discharges only a capacitance at the input of the readout amplifier, and that the gate voltage of the first Transistor, respectively, in the case of a first diode, the first potential is regulated so that in a final phase of the integration time, a part or all of the current generated by the photodiode current through the channel of the first transistor and the first diode is compensated.
  • This control ensures that for high intensities the sensitivity is reduced and for small intensities the sensitivity is increased.
  • the voltages are adjusted so that the gate voltage of the first transistor is below the gate voltage of the second transistor, and that the gate voltage of the first transistor is at least a threshold voltage above the saturation signal of the readout buffer.
  • the anode voltage (first potential) of the diode is set so that the anode voltage minus the diode threshold voltage is below the gate voltage minus the threshold voltage of the second transistor and the anode voltage minus the diode threshold voltage is above the saturation signal of the read buffer.
  • the gate voltages (respectively the gate voltage and the anode voltage in the case of a diode) so that the difference between the two voltages is greater than the tolerance of the threshold voltages plus the tolerance of the voltage values, this difference being particularly preferably> 100 mV is selected.
  • the second transistor is opened, so that the conversion node (storage node) is isolated from the photodiode.
  • the gate of the first transistor is in this phase until the end of the readout phase on a Held potential that is at least one threshold voltage above the ground voltage.
  • a first diode this is set analogously above the first potential with respect to the effective diode threshold voltage. This ensures that charge carriers collected by the photodiode do not completely discharge the photodiode and overflow the storage node, but are compensated by the channel of the first transistor, respectively the first diode, if the potential of the photodiode reaches a value close to the ground voltage (large optical intensities).
  • the gate voltages of the first and the second transistor can be varied during the integration time.
  • the response characteristic sensitivity depending on the intensity
  • Sensor arrays can be set even more variable. Care must be taken during the "hold" phase that the gate voltage of the first transistor remains at least at a value which prevents the complete discharge of the photodiode but below the lowest value of the gate voltage of the second transistor used during the integration phase.
  • the first diode must be regulated according to the first potential.
  • the present invention relates to a method for operating an optoelectronic sensor, as described above.
  • the method is characterized in that the gate voltage of the first transistor or in the case of a first diode, the first potential, and the gate voltage of the second transistor are set or regulated such that in a first phase of the integration time of the photodiode collected charge carriers only one Conversion node capacity discharge that in a second phase after reaching an equal potential at the output of the photodiode and the input of the readout amplifier from the photodiode charge carriers accumulated both Photodiode capacitance and the said conversion node capacity discharged, and that after falling below the threshold value of the first transistor or the first diode at the output of the photodiode in a third phase collected by the photodiode charge carriers are at least partially provided via the first transistor or via the first diode, and that after expiration of the integration time, the second transistor is opened and the gate voltage of the first transistor or the first potential in the case of a first diode
  • This mode of operation achieves the above-mentioned reduction of the sensitivity for high intensities respectively increase of the sensitivity for low intensities and the possibility to store the signal value in the pixel up to the readout time after expiration of the integration time.
  • Global Shutter exposure control
  • the gate voltage of the first transistor is set to the highest value during the reset phase, which is used during the integration phase, but at least a threshold voltage above the ground voltage but below the gate voltage of the second transistor.
  • the gate voltage of the first transistor is set to the same value as during the reset phase, but at least a threshold voltage above the ground voltage.
  • the gate chip of the second transistor can be varied, but always remains larger than the gate voltage of the first transistor, and preferably during the integration phase, the gate voltage of the first transistor is gradually reduced.
  • the gate voltage of the first transistor may keep constant or successively reduce.
  • the procedure may preferably be such that during the integration time, the gate voltage of the second transistor is switched at least once to the bulk potential of this transistor and switched back to its original value.
  • the present invention relates to a one- or two-dimensional Aixay of opto-electronic sensors, as described above. Likewise, it relates to a method of operating such an array.
  • Fig. 1 circuit diagram of an optoelectronic sensor with reduced sensitivity at high intensities
  • FIG. 2 shows a circuit diagram of an optoelectronic sensor with reduced sensitivity at high intensities with a shunt transistor and conversion node capacitance
  • FIG 3 shows a circuit diagram of an optoelectronic sensor with a large dynamic range (preferred implementation of the circuit according to the invention).
  • Fig. 5 circuit diagram of an optoelectronic sensor with a large dynamic range in which the first transistor is replaced by a diode.
  • the optically generated charge is collected by a reverse-polarized photodiode 1 and integrated on the parasitic capacitance of the photodiode and connected to the photodiode capacitors.
  • a reduction of the sensitivity at high intensities can be achieved by deducting a certain signal-dependent current after reaching a certain signal level from the integration capacitance C 1, C 2 (thus proposed, for example, in WO 01/46655 already mentioned in the introduction).
  • This can be achieved by polarizing the gate of MOS transistor T1 during the integration phase in a pixel scheme according to one of FIGS. 1-3, such that, starting from a desired signal value, the MOS transistor T1 is activated by subthreshold conductivity (conductivity below the threshold value) signal-dependent current from the integration capacity Cl dissipates.
  • the polarization of the gate of this transistor Tl can be adjusted such that different effective integration times are realized for different optical intensities. This is implemented in a realization with an N-photodiode to P-substrate and with N-channel MOS transistors as follows:
  • the gate of the reset transistor Tl in Figures 1-3 Before the beginning of the integration time the gate of the reset transistor Tl in Figures 1-3, at least one threshold voltage above the reset potential V is re polarized set. As a result, the integration capacity Cl in Figure 1, respectively. Cl and C2 are charged in Figure 2 and 3 to the reset potential V reset .
  • the gate of the reset transistor Tl is polarized to a value below the reset potential plus threshold voltage, but at least one threshold voltage above the saturation voltage of the read-out buffer (VG1).
  • the current collected by the photodiode 1 which is linear with the incident light intensity, discharges the integration capacitance C1, respectively C1 and C2.
  • the integration capacity within the integration time is discharged to the value VG1-VTH (threshold voltage of T1). From this point leads the Transistor Tl a portion of the current generated by the photodiode 1 again from the integration capacity. The voltage on the integration capacity now decreases more slowly until it finally stabilizes at a value at which the entire current generated by the photodiode 1 is compensated via the transistor Tl.
  • the gate of the reset transistor Tl is polarized to a lower value VG2.
  • the integration capacity is again discharged through the entire photocurrent. Since a shorter time is available until the end of the integration time, optical intensities which have the integration capacity discharged to VG1-VHT in the first time interval result in reduced sensitivity.
  • the characteristic can be determined arbitrarily by inserting further stages.
  • An increase in the sensitivity of integrating optoelectronic sensors in CMOS technology can be achieved by reducing the conversion capacity, which converts the photogenerated charges into a voltage signal.
  • this capacitance is formed by the parasitic capacitance of the photodiode and by the parasitic capacitances of the read-out electronics connected to the photodiode. These capacities can only be limitedly reduced by the minimum structures that can be realized in a particular technology. By inserting a MOS transistor and appropriately polarizing the gate voltage of this transistor between the photodiode and the readout buffer, the parasitic capacitance of the photodiode can be separated from the conversion capacitance.
  • FIG. 1 An example circuit of an optoelectronic sensor which makes this possible is indicated in FIG.
  • the conversion capacitor C2 is reset to the reset voltage V reS e by closing the reset transistor T5. charged.
  • the gate of the Transistor T2 is maintained at a constant voltage during the reset phase VGT2. This voltage is selected so that the gate voltage of the MOS transistor T2 minus a threshold voltage is smaller than the reset voltage, which after opening the reset transistor T5 on the conversion node «. N3 is reached.
  • the gate voltage is selected but at least one threshold voltage above the bulk potential of the transistor T2. As a result, the photodiode 1 is not brought to the reset potential during the reset, but stabilizes at a potential VGT2 - VTH.
  • the end of the integration time can be determined by reducing the gate voltage at T2 to a potential below the bulk potential plus a threshold voltage (opening T2) and sampling the voltage signal at C2 or by reading and initiating the reset.
  • the photodiode can continue to discharge. This can lead to the photodiode completely discharging and the optically generated charges flowing through the substrate overflowing onto the storage node and distorting the read-out signal value.
  • the invention offers a solution to this problem.
  • the gate voltage of the transistor T2 can be changed to increase the sensitivity by means of signal-dependent charge injection. (eg opening and closing several times on VGT2) According to the invention, the procedure is as follows:
  • the circuit diagram of the exemplary embodiment of an optoelectronic sensor according to the invention is shown in FIG.
  • the optoelectronic sensor according to the invention has a photodiode 1, which can be connected by means of MOS transistor Tl with a reset voltage V res et. Furthermore, the sensor has a MOS transistor T2, which connects the photodiode to the readout buffer T3. The input terminal of the readout buffer T3 is further connected to a MOS transistor T5 with the reset potential.
  • the gate terminal of the transistor T2 is polarized during the reset and integration phase so that the gate voltage minus the threshold voltage is lower than the reset potential, which adjusts itself at the input of the readout buffer N3, but at least one threshold voltage above the saturation signal of Readout buffer T3.
  • the gate of the transistor Tl is polarized so that its potential is below the gate potential of T2, but at least a threshold voltage above the saturation signal of the readout buffer T3.
  • the difference between the two gate voltages should be greater than the tolerance of the threshold voltages plus the tolerance of the voltage values (typically> 100mV).
  • the potential of the transistor T2 can be varied, but should always remain greater than the gate potential of the transistor Tl.
  • the gate potential of the transistor Tl can be reduced.
  • charge carriers collected by the photodiode 1 discharge only the conversion capacitance C2, and generate a maximum voltage signal per charge carrier.
  • the inventive sensor remains in this phase during the entire integration time.
  • the potentials on nodes l and N3 equalize.
  • discharged from the photodiode 1 trapped charge carriers the parasitic capacitance Cl of the photodiode 1 as the same as the conversion capacitance C2 and generate a mean voltage signal per carrier.
  • the inventive sensor remains in this phase until the end of the integration time.
  • the parasitic capacitances of the photodiode 1 and of the readout node are discharged to such an extent that some or all of the current generated by the photodiode is compensated by means of transistor T1.
  • the gate potential of Tl can be gradually or continuously reduced according to known technique or kept at a suitable fixed value.
  • the voltage signal detected at node N3 is sampled by reducing the gate potential of T2 to a value below the bulk potential plus a threshold voltage (opening T2). Until the voltage signal is read out, the gate potential of T1 remains at least a threshold voltage above the ground potential. This prevents the parasitic photodiode capacitance from completely discharging and excess charges overflowing onto the storage node.
  • the node N3 is brought to the reset potential V rese t by means of the reset transistor T5 and the gate of transistor T1 is set to the value at the beginning of the integration time.
  • FIG. 5 shows an alternative circuit in which the first transistor Tl is replaced by a diode Dl.
  • the reset potential of diode Dl and transistor T5 must be designed differently.
  • Reset potential V re seti is applied to diode D 1 (in a variation of the realization, this potential can be regulated during the integration time) while at transistor T 5 resp. T3 the potential V re se t2 is applied.
  • Figure 5 can be achieved by deducted from reaching a certain signal level of the integration capacity Cl, C2, a certain signal-dependent current is (is thus made, for example, in WO 01/46655 already mentioned). This is achieved by setting the reset voltage N ese u of the diode D 1 during the integration phase in such a way that, starting from a desired signal value , the diode D 1 conducts a signal-dependent current from the integration capacitance C 1 by conductance above the diode threshold value , During the integration time, the voltage V reS et ⁇ can be adapted to the diode Dl such that different effective integration times are realized for different optical intensities. This is the case for a realization with an N-photodiode opposite to P + / N-well junction diode D1 (typically with a threshold potential V onD_ or of a range from 0.3 to 0.7 V).
  • the conversion capacitor C2 is charged to the reset voltage V reSet by closing the reset transistor T5.
  • the gate of transistor T2 is maintained at a constant voltage during the reset phase VGT2. This voltage is chosen so that the gate voltage of the MOS transistor T2 minus a threshold voltage is smaller than the reset voltage, which is reached after opening of the reset transistor T5 on the conversion node N3.
  • the gate voltage is selected but at least one threshold voltage above the bulk potential of the transistor T2. As a result, the photodiode 1 is not brought to the reset potential during the reset, but stabilizes at a potential VGT2 - VTH.
  • the reset voltage V reset i in FIG. 5 is set to the highest voltage used during the integration.
  • This voltage minus the threshold voltage of the diode (D1) is at least above the saturation value of the readout buffer but below the gate voltage minus the threshold voltage of the second transistor (T2 in FIG. 5) (typically> 100mV).
  • the current collected by the photodiode 1, which is linear with the incident light intensity, is compensated in a first phase by the channel of MOS transistor T2 and only discharges the capacitance C2. Once the potential on N3 is discharged to a value below the gate voltage of T2 minus the threshold voltage, the capacitances C1 and C2 are discharged equally.
  • the Integration capacity (C1 + C2) within the integration time to the value V reSet ⁇ - Discharged by diode. From this time, the diode Dl performs a part of the current generated by the photodiode 1 again from the integration capacity. The voltage on the integration capacity now decreases more slowly until it finally stabilizes at a value at which the entire current generated by the photodiode 1 is compensated via the diode D1. In a further phase of the integration time, for example after 90% of the integration time, the reset voltage V reS e t ⁇ set to a lower value. As a result, the compensation of the current generated by the photodiode 1 breaks off. The integration capacity is again discharged through the entire photocurrent. Since up to the end of the integration period a shorter time is available, results for optical intensities which the integration capacity up to V res et ⁇ the first time interval - to discharge V on the diode, a reduced sensitivity.
  • the characteristic curve can also be arbitrarily determined here by adding further stages.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Nonlinear Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Photometry And Measurement Of Optical Pulse Characteristics (AREA)
  • Facsimile Heads (AREA)

Abstract

La présente invention concerne un capteur optoélectronique comprenant au moins une photodiode (1) qui peut être raccordée à un premier potentiel (Vreset,Vreset1) par un premier transistor (T1) ou par une première diode (D1) et qui peut être raccordée à l'entrée d'un amplificateur de lecture (T3) par un deuxième transistor (T2). Un troisième transistor (T5) est monté entre le deuxième transistor (T2) et l'entrée de l'amplificateur de lecture (T3) et permet de raccorder l'entrée de l'amplificateur de lecture (T3) à un second potentiel (Vreset, Vreset2). Ce capteur optoélectronique comprend également des systèmes (C2) qui permettent de stocker temporairement la valeur de signal intégrée jusqu'à un moment de lecture. Le capteur optoélectronique selon cette invention présente une grande plage dynamique, c'est-à-dire que la sensibilité est augmentée en cas de petits signaux et est réduite en cas de grands signaux et qu'il est possible de stocker en pixels la valeur du signal après l'intégration jusqu'à un moment de lecture (commande d'exposition </= GLOBAL SHUTTER >/= ).
EP03753208A 2002-10-29 2003-10-28 Capteur optoelectronique Withdrawn EP1557032A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CH18102002 2002-10-29
CH181002 2002-10-29
PCT/CH2003/000704 WO2004040904A1 (fr) 2002-10-29 2003-10-28 Capteur optoelectronique

Publications (1)

Publication Number Publication Date
EP1557032A1 true EP1557032A1 (fr) 2005-07-27

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP03753208A Withdrawn EP1557032A1 (fr) 2002-10-29 2003-10-28 Capteur optoelectronique

Country Status (7)

Country Link
US (1) US20060170491A1 (fr)
EP (1) EP1557032A1 (fr)
JP (1) JP2006505159A (fr)
KR (1) KR20050065652A (fr)
CN (1) CN1708976A (fr)
AU (1) AU2003271499A1 (fr)
WO (1) WO2004040904A1 (fr)

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CN1708976A (zh) 2005-12-14
US20060170491A1 (en) 2006-08-03
AU2003271499A1 (en) 2004-05-25
WO2004040904A1 (fr) 2004-05-13
JP2006505159A (ja) 2006-02-09

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