EP1556890A1 - Elektronisches bauteil mit unterfülstoffen aus thermoplasten und verfahren zu dessen herstellung - Google Patents
Elektronisches bauteil mit unterfülstoffen aus thermoplasten und verfahren zu dessen herstellungInfo
- Publication number
- EP1556890A1 EP1556890A1 EP03776797A EP03776797A EP1556890A1 EP 1556890 A1 EP1556890 A1 EP 1556890A1 EP 03776797 A EP03776797 A EP 03776797A EP 03776797 A EP03776797 A EP 03776797A EP 1556890 A1 EP1556890 A1 EP 1556890A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- thermoplastic
- electronic component
- contacts
- chip
- flip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 239000000945 filler Substances 0.000 title description 2
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 238000005476 soldering Methods 0.000 claims abstract description 21
- 239000000463 material Substances 0.000 claims abstract description 12
- 230000009477 glass transition Effects 0.000 claims abstract description 11
- 229920001169 thermoplastic Polymers 0.000 claims description 36
- 239000004416 thermosoftening plastic Substances 0.000 claims description 36
- 239000004033 plastic Substances 0.000 claims description 21
- 229920003023 plastic Polymers 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 14
- 229910000679 solder Inorganic materials 0.000 claims description 9
- 238000005516 engineering process Methods 0.000 claims description 7
- 238000002844 melting Methods 0.000 claims description 7
- 230000008018 melting Effects 0.000 claims description 7
- -1 polyethylene Polymers 0.000 claims description 6
- 238000004806 packaging method and process Methods 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 3
- 229930182556 Polyacetal Natural products 0.000 claims description 2
- 239000004952 Polyamide Substances 0.000 claims description 2
- 239000004698 Polyethylene Substances 0.000 claims description 2
- 239000004743 Polypropylene Substances 0.000 claims description 2
- 239000006185 dispersion Substances 0.000 claims description 2
- 238000001746 injection moulding Methods 0.000 claims description 2
- 229920002647 polyamide Polymers 0.000 claims description 2
- 229920000515 polycarbonate Polymers 0.000 claims description 2
- 239000004417 polycarbonate Substances 0.000 claims description 2
- 229920000573 polyethylene Polymers 0.000 claims description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 claims description 2
- 239000005020 polyethylene terephthalate Substances 0.000 claims description 2
- 229920006324 polyoxymethylene Polymers 0.000 claims description 2
- 229920001155 polypropylene Polymers 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 239000012815 thermoplastic material Substances 0.000 claims description 2
- 238000011990 functional testing Methods 0.000 abstract description 10
- 230000004927 fusion Effects 0.000 abstract 1
- 230000006378 damage Effects 0.000 description 3
- 229920001187 thermosetting polymer Polymers 0.000 description 3
- 238000001721 transfer moulding Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 239000002985 plastic film Substances 0.000 description 1
- 229920006255 plastic film Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H01L2924/01—Chemical elements
- H01L2924/01068—Erbium [Er]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/01079—Gold [Au]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Definitions
- the invention relates to an electronic component with a semiconductor chip, which has flip-chip contacts and is fixed on a rewiring substrate, and to a method for producing the same.
- Electronic components with flip-chip contacts and a rewiring substrate are packaged in a plastic housing made of thermosets.
- a plastic housing made of thermosets.
- the object of the invention is to specify an electronic component and a method for its production, which increases the reliability of electronic components.
- an electronic component with a semiconductor chip which has flip-chip contacts on its active upper side, which are on contact pads of a rewiring substrate are fixed. This fixation can be carried out by means of a solder connection and / or by means of a conductive adhesive.
- the intermediate space formed by the flip-chip contacts between the rewiring substrate and the semiconductor chip has a thermoplastic as the underfill. The glass transition temperature of this thermoplastic used as an underfill is below the melting temperature of the soldering material of the external contacts of the electronic component.
- Such a component has the advantage that the failures of the electronic components are reduced when external contacts are soldered onto external contact surfaces and when external contacts of the electronic component are soldered onto higher-level circuit carriers.
- the glass transition temperature and thus the softening point is in any case above the highest functional test temperature for electronic components, which can be between 70 and 150 ° C depending on the area of application. Consumer components do not become as hard and therefore with a smaller one highest functional test temperature tested as commercial components, such as electronic components for automotive technology, which are cyclically loaded with a highest functional test temperature of 150 ° during the function test.
- the glass transition temperature for the thermoplastic to be used as the underfill is then correspondingly higher.
- Another advantage of this electronic component is that the housing no longer has to be pre-dried before every soldering process in order to drive off the moisture, since a higher degree of moisture can be tolerated with the use of a thermoplastic as an underfill, without destroying the structure or the structure of the component.
- thermoplastic One of the substances from the group polyamide, polyacetal, polycarbonate, polyethylene, polypropylene, polyethylene terephthalate or mixtures thereof can be used as the thermoplastic.
- the desired softening temperature range and melting temperature range can be set in particular by mixing these thermoplastics. This ensures that the thermoplastic has the same strength at the highest functional test temperature as at room temperature, especially since the glass transition temperature for the thermoplastic is only reached above this.
- thermoplastic In contrast to soldering, in which an electronic component is only partially heated and can only partially reach critical temperatures, the electronic components for the function test are completely exposed to a highest functional test temperature ⁇ , which can be up to 150 ° C. At such a temperature, the thermoplastic should have the same consistency and strength as at room temperature. Only at the much higher soldering temperature External contacts, which can reach 250 ° C, the thermoplastic as a filler has a plastic compliance or melt properties that prevent the components of the electronic component, in particular the semiconductor chip, the flip-chip contacts and the contact ' Terminal pads of the rewiring substrate damaged or destroyed or their connections to each other are interrupted.
- a plastic package in which the semiconductor chip and the flip-chip contacts are packed can have a thermoplastic with the same glass transition temperature as the underfill. This has the advantage that the plastic housing pack and the underfill can be introduced in a single transfer molding step.
- the flip-chip contacts can be securely fixed on corresponding contact connection areas of the U-wiring substrate, especially since the housing can be produced in the construction of the electronic component according to the invention without the semiconductor chip having its flip chip prior to packaging -Contacts must be pressed through a plastic film or a plastic layer on corresponding contact pads of the rewiring substrate.
- the plastic housing package can also have a thermoplastic with a glass transition temperature which is above the melting temperature of the soldering material of the external contacts.
- a thermoplastic with a glass transition temperature which is above the melting temperature of the soldering material of the external contacts.
- the soldering temperature when partially reached, only the thermoplastic softening at a lower temperature, which is used as an underfill, will yield softening or molten.
- This plastic giving way of the underfill is sufficient, however, to prevent damage or destruction of the connections between the semiconductor chip and the rewiring substrate.
- two successive transfer molding processes are required in order to apply the two different thermoplastics first as an underfill and then as a plastic packaging.
- the thermoplastic can advantageously have a molten state in a temperature range between 200 ° C. and 220 ° C. In such a molten state, the thermoplastic is yielding in such a way that loads caused by water vapor formation can be compensated for. In addition, this temperature range is well above a highest functional test temperature and below a soldering temperature of the external contacts.
- a method for producing an electronic component has the following method steps. First, a rewiring substrate with contact pads on its upper side and external contact areas on its lower side is produced. In the rewiring substrate, the external contact areas on the underside are connected to the contact connection areas on the top side of the rewiring substrate via vias and rewiring lines. In addition, a semiconductor chip is produced using flip-chip technology with flip-chip contacts on its active top side.
- the flip-chip contacts are placed on the rewiring substrate. brings and electrically connected to the contact pads. Finally, the space between the active Top of the semiconductor chip and the top of the rewiring substrate are filled with an underfill made of thermoplastic.
- thermoset is used to fill up the intermediate space between the semiconductor chip and the rewiring substrate, which thermoplastic damages or destroys the connection between the semiconductor chip and the rewiring substrate when moisture occurs, in particular when soldering external contacts or when soldering the external contacts to a higher-level circuit carrier could.
- the flip-chip contacts can be soldered to the contact pads of the rewiring substrate or with a before the thermoplastic is introduced as an underfill
- Conductive adhesive can be fixed. Since this process step takes place before the underfill is introduced, a secure, reliable electrical connection can be created via the flip-chip contacts to the rewiring substrate and thus to the external contact areas of the rewiring substrate.
- the underfill can be applied with the appropriate heating using dispersion technology, so that a high-pressure mold can be dispensed with. If the plastic housing pack consists of the same material as the underfill material, the plastic housing pack can be realized simultaneously with the underfill material. In this case, it is advantageous to apply the thermoplastic by means of injection molding technology, so that underfilling and molding of the
- Plastic packaging can be done in one step. Before the thermoplastic is introduced onto the top of the rewiring substrate, it is heated to a processing temperature above the highest functional test temperature and below the melting temperature of the soldering material for external contacts. It is preferably provided that the thermoplastic is heated to temperatures between 200 and 220 ° C. before being applied to the rewiring structure.
- Figure 1 shows a schematic cross section of an electronic component which is applied to a circuit carrier.
- FIG. 2 shows a schematic cross section of a critical section of an electronic component.
- FIG. 3 shows a schematic cross section of an electronic component with a plastic housing pack, which is applied to a circuit carrier.
- FIG. 1 shows a schematic cross section of an electronic component 1, which is applied with its external contacts 10 to a circuit carrier 12 of a higher-level electronic circuit.
- the electronic component 1 essentially consists of two main components, namely a semiconductor chip 2 and a rewiring substrate 6.
- the rewiring substrate 6 has essentially five layers. Starting from its top 13, the five layers are staggered towards the bottom 15 as explained below.
- the lower solder stop layer 23 covers the underside 15 of the rewiring substrate 6 except for external contact surfaces 13, on which external contacts 10 are soldered in the form of solder balls.
- the external contact areas 14 belong to the lower rewiring layer 22, which is electrically connected to the upper rewiring layer 20 via vias 16.
- the upper solder stop layer 19 only leaves the contact connection areas 5 free of solder resist from the upper rewiring layer 20.
- the semiconductor chip 2 has an active upper side 4 and a passive rear side 24. Contact surfaces 18 are arranged on the active top side 4 and carry flip chip contacts 3 in the form of solder balls or bumps.
- the two main components of the electronic component 1 are electrically connected to one another via the flip-chip contacts 3 of the semiconductor chip 2 and the contact connection areas 5 of the upper rewiring layer 20 of the rewiring substrate 6.
- thermoplastic 8 Semiconductor chips 2 and the upper side 13 of the rewiring substrate 6 are filled with a thermoplastic 8.
- thermoplastic 8 or the thermoplastic mixture has a glass transition temperature between 155 ° C and 250 ° C.
- the critical phase in the assembly of such an electronic component 1 and in the assembly of such an electronic component 1 on the top of a circuit carrier 12 lies in the heating to the soldering temperature of the external contacts 10.
- FIG. 2 shows a schematic cross section through a critical section of an electronic component 1.
- This critical section is the intermediate space 7 between the active ven upper side 4 of the semiconductor chip 2 and the upper side 13 of the rewiring substrate 6.
- This intermediate space has a fixed connection in the form of flip-chip contacts 3 between the contact surfaces 18 of the semiconductor chip 2 and contact connection surfaces 5 of the upper rewiring layer 20 of the rewiring substrate 6. Since plastics are hygroscopic, they absorb moisture when stored temporarily.
- vapor bubbles 25 can form and exert pressure on the upper sides of the rewiring substrate 6 and the semiconductor chip 2 connected via the flip chip contacts 3.
- An underfill 9 made of thermoplastic 8, which fills the intermediate space 7, can yield to this pressure, especially since it is plastically flexible or is molten in the area of the soldering temperature and can thus weaken the load caused by such a vapor bubble 25.
- FIG. 3 shows a schematic cross section of an electronic component 1 with a plastic housing pack 11, which is applied to a circuit carrier 12.
- Components with the same functions as in the previous figures are identified by the same reference symbols and are not discussed separately.
- the difference between this electronic component 1 and the component 1 shown in FIG. 1 is that the passive rear side of the semiconductor chip 2 is not freely accessible as in FIG. 1, but is covered with a plastic housing package 11.
- This' Künststoffgekorusepackung 11 has in this embodiment of the invention according to FIG 3 the same thermoplastic material 8 from which the underfilling is already formed. 9
- the underfill 9 and the plastic housing package 11 were applied in a single transfer molding step. In order to avoid possible partial deformation or melting of the plastic housing package 11 during soldering, the plastic housing package 11 can be partially cooled during the soldering process.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10250541 | 2002-10-29 | ||
DE10250541A DE10250541B9 (de) | 2002-10-29 | 2002-10-29 | Elektronisches Bauteil mit Unterfüllstoffen aus Thermoplasten und Verfahren zu dessen Herstellung |
PCT/DE2003/003463 WO2004040640A1 (de) | 2002-10-29 | 2003-10-20 | Elektronisches bauteil mit unterfüllstoffen aus thermoplasten und verfahren zu dessen herstellung |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1556890A1 true EP1556890A1 (de) | 2005-07-27 |
Family
ID=32010484
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP03776797A Withdrawn EP1556890A1 (de) | 2002-10-29 | 2003-10-20 | Elektronisches bauteil mit unterfülstoffen aus thermoplasten und verfahren zu dessen herstellung |
Country Status (7)
Country | Link |
---|---|
US (1) | US20060088954A1 (de) |
EP (1) | EP1556890A1 (de) |
JP (1) | JP4545591B2 (de) |
KR (1) | KR100789349B1 (de) |
CN (1) | CN100449719C (de) |
DE (1) | DE10250541B9 (de) |
WO (1) | WO2004040640A1 (de) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102004031889B4 (de) * | 2004-06-30 | 2012-07-12 | Infineon Technologies Ag | Halbleiterbauteil mit einem Gehäuse und einem teilweise in eine Kunststoffgehäusemasse eingebetteten Halbleiterchip und Verfahren zur Herstellung desselben |
WO2006043122A1 (en) * | 2004-10-21 | 2006-04-27 | Infineon Technologies Ag | Semiconductor package and method to produce the same |
WO2007017341A1 (de) * | 2005-08-11 | 2007-02-15 | Siemens Aktiengesellschaft | Fluxing encapsulants - giessharze für dca-anwendungen auf basis kationisch härtbarer epoxidharze |
DE102005047856B4 (de) * | 2005-10-05 | 2007-09-06 | Infineon Technologies Ag | Halbleiterbauteil mit in Kunststoffgehäusemasse eingebetteten Halbleiterbauteilkomponenten, Systemträger zur Aufnahme der Halbleiterbauteilkomponenten und Verfahren zur Herstellung des Systemträgers und von Halbleiterbauteilen |
KR101726262B1 (ko) * | 2015-01-02 | 2017-04-13 | 삼성전자주식회사 | 패키지 기판용 필름, 이를 사용한 반도체 패키지 및 반도체 패키지를 포함하는 표시 장치 |
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JP2000003943A (ja) * | 1992-06-25 | 2000-01-07 | Nitto Denko Corp | フィルムキャリア、これらを用いた半導体装置およびフィルムキャリアの製造方法 |
US6329220B1 (en) * | 1999-11-23 | 2001-12-11 | Micron Technology, Inc. | Packages for semiconductor die |
US20020109241A1 (en) * | 2000-12-19 | 2002-08-15 | Takashi Kumamoto | Molded flip chip package |
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EP0051165A1 (de) * | 1980-11-03 | 1982-05-12 | BURROUGHS CORPORATION (a Michigan corporation) | Aufnahmevorrichtung für auswechselbare ICs mit thermoplastischer Befestigung |
JPH0677811B2 (ja) * | 1986-01-20 | 1994-10-05 | 株式会社ハイベツク | 自動半田付け装置 |
JP3088877B2 (ja) * | 1992-06-25 | 2000-09-18 | 日東電工株式会社 | フィルムキャリアの製造方法および半導体装置 |
US5371404A (en) * | 1993-02-04 | 1994-12-06 | Motorola, Inc. | Thermally conductive integrated circuit package with radio frequency shielding |
US5371328A (en) * | 1993-08-20 | 1994-12-06 | International Business Machines Corporation | Component rework |
US5659203A (en) * | 1995-06-07 | 1997-08-19 | International Business Machines Corporation | Reworkable polymer chip encapsulant |
US5783867A (en) * | 1995-11-06 | 1998-07-21 | Ford Motor Company | Repairable flip-chip undercoating assembly and method and material for same |
JP3376203B2 (ja) * | 1996-02-28 | 2003-02-10 | 株式会社東芝 | 半導体装置とその製造方法及びこの半導体装置を用いた実装構造体とその製造方法 |
JPH1084014A (ja) * | 1996-07-19 | 1998-03-31 | Shinko Electric Ind Co Ltd | 半導体装置の製造方法 |
JPH1167988A (ja) * | 1996-10-17 | 1999-03-09 | Ngk Spark Plug Co Ltd | 配線基板構造物及び配線基板 |
US5981312A (en) * | 1997-06-27 | 1999-11-09 | International Business Machines Corporation | Method for injection molded flip chip encapsulation |
JPH11219984A (ja) * | 1997-11-06 | 1999-08-10 | Sharp Corp | 半導体装置パッケージおよびその製造方法ならびにそのための回路基板 |
JP3741553B2 (ja) * | 1998-11-20 | 2006-02-01 | シャープ株式会社 | 半導体装置の接続構造および接続方法ならびにそれを用いた半導体装置パッケージ |
US6373717B1 (en) * | 1999-07-02 | 2002-04-16 | International Business Machines Corporation | Electronic package with high density interconnect layer |
JP4179736B2 (ja) * | 1999-07-16 | 2008-11-12 | 松下電器産業株式会社 | 半導体素子実装済部品の製造方法及び半導体素子実装済完成品の製造方法 |
EP1204136B1 (de) * | 1999-07-16 | 2009-08-19 | Panasonic Corporation | Verfahren zur Herstellung einer verpackten Halbleiteranordnung |
JP3598245B2 (ja) * | 1999-10-21 | 2004-12-08 | 松下電器産業株式会社 | 電子部品の実装方法及び基板モジュール |
JP2001203318A (ja) * | 1999-12-17 | 2001-07-27 | Texas Instr Inc <Ti> | 複数のフリップチップを備えた半導体アセンブリ |
US6700209B1 (en) * | 1999-12-29 | 2004-03-02 | Intel Corporation | Partial underfill for flip-chip electronic packages |
JP3491827B2 (ja) * | 2000-07-25 | 2004-01-26 | 関西日本電気株式会社 | 半導体装置及びその製造方法 |
JP2002083904A (ja) * | 2000-09-06 | 2002-03-22 | Sanyo Electric Co Ltd | 半導体装置およびその製造方法 |
-
2002
- 2002-10-29 DE DE10250541A patent/DE10250541B9/de not_active Expired - Fee Related
-
2003
- 2003-10-20 JP JP2004547404A patent/JP4545591B2/ja not_active Expired - Fee Related
- 2003-10-20 CN CNB2003801025133A patent/CN100449719C/zh not_active Expired - Fee Related
- 2003-10-20 EP EP03776797A patent/EP1556890A1/de not_active Withdrawn
- 2003-10-20 WO PCT/DE2003/003463 patent/WO2004040640A1/de active Search and Examination
- 2003-10-20 US US10/515,517 patent/US20060088954A1/en not_active Abandoned
- 2003-10-20 KR KR1020057007606A patent/KR100789349B1/ko not_active IP Right Cessation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2000003943A (ja) * | 1992-06-25 | 2000-01-07 | Nitto Denko Corp | フィルムキャリア、これらを用いた半導体装置およびフィルムキャリアの製造方法 |
US6329220B1 (en) * | 1999-11-23 | 2001-12-11 | Micron Technology, Inc. | Packages for semiconductor die |
US20020109241A1 (en) * | 2000-12-19 | 2002-08-15 | Takashi Kumamoto | Molded flip chip package |
Also Published As
Publication number | Publication date |
---|---|
US20060088954A1 (en) | 2006-04-27 |
WO2004040640A1 (de) | 2004-05-13 |
CN100449719C (zh) | 2009-01-07 |
DE10250541B3 (de) | 2004-04-15 |
CN1751386A (zh) | 2006-03-22 |
JP4545591B2 (ja) | 2010-09-15 |
DE10250541B9 (de) | 2004-09-16 |
KR100789349B1 (ko) | 2007-12-28 |
KR20050050679A (ko) | 2005-05-31 |
JP2006504275A (ja) | 2006-02-02 |
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