WO1999003145A1 - Verfahren zur herstellung einer klebeverbindung zwischen einem elektronischen bauelement und einem trägersubstrat - Google Patents
Verfahren zur herstellung einer klebeverbindung zwischen einem elektronischen bauelement und einem trägersubstrat Download PDFInfo
- Publication number
- WO1999003145A1 WO1999003145A1 PCT/DE1998/000870 DE9800870W WO9903145A1 WO 1999003145 A1 WO1999003145 A1 WO 1999003145A1 DE 9800870 W DE9800870 W DE 9800870W WO 9903145 A1 WO9903145 A1 WO 9903145A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- component
- carrier substrate
- opening
- adhesive
- contact elements
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 67
- 238000000034 method Methods 0.000 title claims description 31
- 239000000853 adhesive Substances 0.000 claims description 72
- 230000001070 adhesive effect Effects 0.000 claims description 72
- 239000011248 coating agent Substances 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 9
- 230000009969 flowable effect Effects 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000001465 metallisation Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 239000003292 glue Substances 0.000 abstract description 3
- 239000012530 fluid Substances 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 description 12
- 238000005476 soldering Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 6
- 230000035515 penetration Effects 0.000 description 3
- 230000002028 premature Effects 0.000 description 3
- 230000001419 dependent effect Effects 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
- H05K3/305—Affixing by adhesive
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92225—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/01032—Germanium [Ge]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01068—Erbium [Er]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09072—Hole or recess under component or special relationship between hole and component
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10189—Non-printed connector
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10954—Other details of electrical connections
- H05K2201/10977—Encapsulated connections
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- the invention relates to a method for producing an adhesive connection between an electronic component and a carrier substrate with the features specified in the preamble of claim 1.
- solder bumps solder bumps
- a plurality of wireless, electrically conductive connections between a chip and a carrier substrate provided with an electronic circuit can advantageously be produced in one operation.
- an adhesive must be introduced between the chip and the carrier substrate in a so-called "underfill process" so that the soldered joints are not damaged in the event of changes in temperature Dispensing device applied to the carrier substrate along at least one chip edge.
- the adhesive flows into the narrow gap between the chip and the substrate. After curing, the adhesive absorbs mechanical stresses and thus protects the soldered connection and increases its service life .
- the adhesive is only on one or apply two chip edges, the adhesive gradually spreading out to the opposite side of the chip under the chip. Since it is not possible to apply the entire volume of adhesive to one edge of the chip, the application must be repeated several times until finally all contact elements are surrounded by the adhesive.
- Such a method is described, for example, in the article "Key process controls for under-filling flip chips" by Alec. J. Babiarz, Solid State Technology, April 1997.
- a disadvantage of this is that between the individual application steps the flow time of the adhesive is always repeated dependent breaks have to be taken and glue is applied again until the entire gap between chip and substrate is finally filled in. Long waiting times have to be accepted, especially with larger chips. The long waiting times increase the manufacturing time considerably, which in turn increases significantly increase the manufacturing costs.
- the inventive method for producing an adhesive connection between an electronic component and a carrier substrate with the characterizing features of claim 1 has the advantage that the entire adhesive volume required to produce the adhesive connection can be applied in a single step with the dispensing device. Waiting times dependent on the flow time of the adhesive are hereby advantageously avoided, as a result of which the production costs for the connection can be considerably reduced.
- the method according to the invention is extremely advantageous in particular for producing adhesive bonds in the case of larger chips with an edge length of up to 3 cm. Further advantageous refinements and developments of the invention are made possible by the features specified in the subclaims.
- capillary flowable adhesive along a closed path running around the circumference of the component in the immediate vicinity of the component, so that initially all the contact elements lying on the edge of the component are flowed around by the adhesive.
- a closed adhesive front then extends between the component and the carrier substrate to the at least one opening provided in the carrier substrate below the component, air in the gap being able to escape through the opening.
- the opening in the form of a hole arranged centrally below the component, since the adhesive then spreads particularly uniformly under the component between the central opening and the contact elements. If the adhesive is applied to the side of the carrier substrate equipped with the component, so that it first flows around the contact elements and then spreads out to the at least one opening, the adhesive front may already have reached the opening in one section, but in another section not yet. A premature penetration of the adhesive into the opening before all the air is displaced from the gap can advantageously be prevented by a coating on the side of the carrier substrate which is equipped with the component and which extends around the edge of the
- Opening is applied around and consists of a material that is poorly wettable by the adhesive.
- the coating is preferably a metallization made of copper or gold.
- a stepped projection can also be arranged on the side of the carrier substrate provided with the component around the edge of the opening, which, like the metallization, prevents premature penetration of the adhesive into the opening.
- FIGS. 4a to 4d different phases of the spreading of an adhesive front in the one shown in FIGS. 1 to 3 Embodiment
- FIGS. 5 and 6 show a second exemplary embodiment of the method according to the invention for producing an adhesive connection between a substrate and a flip-chip component. Description of the embodiments
- a flip-chip component 2 is soldered onto a carrier substrate 1, which can be, for example, a circuit board made of FR4 substrate, a ceramic carrier, a chip carrier component or some other suitable substrate.
- a carrier substrate can be, for example, a circuit board made of FR4 substrate, a ceramic carrier, a chip carrier component or some other suitable substrate.
- a packaged flip chip component in, for example, multi-chip modules or a so-called chip scale package can also be applied to the carrier substrate.
- the illustration shown here is limited to a single component. As can be seen in FIG.
- the component 2 is provided on its connection side with contact elements 3 distributed over the circumference, which are designed as solder bumps.
- the component 2 with the Solder bumps 3 are placed on a corresponding grid of contact areas 4 of the carrier substrate 1 and are soldered to them in a reflow soldering station 2. After the reflow soldering, the component 2 with the contact areas 4 of the carrier substrate 1 is shown in FIG However, it is equally possible for the flip-chip component to be glued to the contact surfaces 4 with an isotropically conductive adhesive applied to the contact elements 3 or to be welded onto the contact surfaces in the thermocompression process.
- a central opening 5 with a circular cross section is provided in the carrier substrate 1 below the component 2 and extends from the component side of the carrier substrate to the opposite rear side.
- a plurality of openings can also be introduced into the carrier substrate below the component.
- the opening 5 can, for example, be drilled into the substrate before the component 2 is applied or can be introduced into the carrier substrate using a process known for the production of plated-through holes.
- a capillary flowable adhesive for example an epoxy resin adhesive with an SiO 2 filler
- the adhesive 10 is applied to the carrier substrate 1 at the edge of the component 2 using a dispensing device.
- the entire amount of adhesive required to produce the adhesive connection is applied in one go along the closed line represented by the arrows in FIG. 1.
- the capillary adhesive 10 applied to all four sides of the component immediately penetrates into the space between the solder bumps 3, flows around all the solder bumps 3, as can be seen in FIG. 2 in connection with FIG. 4a, and then spreads in the direction of the arrow up to the opening 5 in the gap 8.
- Fig. 4 shows a cross section through the Gap 8 in Fig. 2. In Figures 4a to 4d, the spread of the adhesive 10 in the gap 8 can be seen particularly well. After the application of the adhesive 10, the solder bumps 3 are first flowed around and a closed adhesive front is formed which contracts in the direction of the arrow toward the opening 5. As shown in Fig.
- an annular coating 9 is applied to the carrier substrate 1 around the edge of the opening 5.
- the coating can be produced with the aid of a process known from printed circuit board technology for producing conductor tracks and consists of a material which is poorly wettable by the adhesive.
- a metallization of copper or gold is preferably provided as the coating. Since the organic circuit board material is wetted more quickly by the adhesive, the metallization regulates the flow rate of the adhesive front in such a way that the
- the adhesive front completely contracts around the metallization, as shown in FIG. 4c, and only then wets the metallization and penetrates into the opening 5, as shown in FIG. 4d. This ensures that no air bubbles are trapped in the gap 8. It is particularly advantageous that in this exemplary embodiment the soldering bumps 3 arranged on the edge of the component 2 are first surrounded by the adhesive and thus protected.
- FIGS. 5 and 6 Another exemplary embodiment of the method according to the invention is shown in FIGS. 5 and 6.
- the component 2 is placed on the carrier substrate in the known flip-chip technology and is soldered to it.
- an opening 5 extends through the carrier substrate 1 at the location of the applied component 2.
- the opening 5 should have a diameter sufficient for the capillary flowability of the adhesive.
- the component 2 is applied to the circuit board such that the opening 5 is located centrally below the component.
- no metallization delimiting the edge of the opening 5 is provided in this exemplary embodiment.
- the entire amount of capillary flowable adhesive 10 required for the underfill process is now applied to the upside-down side of the carrier substrate 1 in the region of the opening 5. Due to the capillary action of the channel-like opening 5, the adhesive 10 penetrates into the opening 5 until it reaches the gap 8. As shown in FIG. 6, the adhesive 10 spreads in the gap 8 with an approximately circular adhesive front toward the solder bumps 3 until it completely flows around them. The air in the gap passes through the spaces between the solder bumps. In contrast to the first exemplary embodiment, the adhesive 10 in this exemplary embodiment only penetrates into the space between the solder bumps 3 at the end of the flow process.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11507956A JP2001501381A (ja) | 1997-07-08 | 1998-03-25 | 電子素子と支持基板との間の接着結合を形成するための方法 |
HU0000672A HUP0000672A3 (en) | 1997-07-08 | 1998-03-25 | Method for making a glued joint between an electronic component and a supporting substrate |
EP98928066A EP0923791A1 (de) | 1997-07-08 | 1998-03-25 | Verfahren zur herstellung einer klebeverbindung zwischen einem elektronischen bauelement und einem trägersubstrat |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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DE19729073.6 | 1997-07-08 | ||
DE19729073A DE19729073A1 (de) | 1997-07-08 | 1997-07-08 | Verfahren zur Herstellung einer Klebeverbindung zwischen einem elektronischen Bauelement und einem Trägersubstrat |
Publications (1)
Publication Number | Publication Date |
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WO1999003145A1 true WO1999003145A1 (de) | 1999-01-21 |
Family
ID=7834968
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE1998/000870 WO1999003145A1 (de) | 1997-07-08 | 1998-03-25 | Verfahren zur herstellung einer klebeverbindung zwischen einem elektronischen bauelement und einem trägersubstrat |
Country Status (6)
Country | Link |
---|---|
EP (1) | EP0923791A1 (de) |
JP (1) | JP2001501381A (de) |
KR (1) | KR20000068591A (de) |
DE (1) | DE19729073A1 (de) |
HU (1) | HUP0000672A3 (de) |
WO (1) | WO1999003145A1 (de) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19902450A1 (de) * | 1999-01-22 | 2000-08-03 | Festo Ag & Co | Miniaturisiertes elektronisches System und zu dessen Herstellung geeignetes Verfahren |
CN100369532C (zh) * | 2003-09-29 | 2008-02-13 | 松下电器产业株式会社 | 微型组件及其制造方法 |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE59809584D1 (de) * | 1998-12-24 | 2003-10-16 | Nokia Corp | Verfahren zum mechanischen Befestigen von elektrischen Bauteilen auf einer Platine sowie eine Vorrichtung hergestellt nach diesem Verfahren |
DE19908474C2 (de) | 1999-02-26 | 2001-02-15 | Siemens Ag | Verfahren zur Montage eines Halbleiterchips auf einer Tragschicht |
DE10047135B4 (de) * | 2000-09-22 | 2006-08-24 | Infineon Technologies Ag | Verfahren zum Herstellen eines Kunststoff umhüllten Bauelementes und Kunststoff umhülltes Bauelement |
DE10327767A1 (de) * | 2003-06-18 | 2005-01-05 | Marconi Communications Gmbh | Schaltungsbaugruppe und Herstellungsverfahren dafür |
JPWO2009044863A1 (ja) * | 2007-10-03 | 2011-02-10 | 株式会社フジクラ | モジュール、配線板、及びモジュールの製造方法 |
JP5442990B2 (ja) * | 2008-12-24 | 2014-03-19 | 京セラ株式会社 | 回路装置の製造方法及び電子機器の製造方法 |
DE102015207893B3 (de) | 2015-04-29 | 2016-10-13 | Robert Bosch Gmbh | Elektronische Baugruppe, insbesondere für ein Getriebesteuermodul |
US11152226B2 (en) * | 2019-10-15 | 2021-10-19 | International Business Machines Corporation | Structure with controlled capillary coverage |
DE102021133671A1 (de) * | 2021-12-17 | 2023-06-22 | Jenoptik Optical Systems Gmbh | Verfahren zum Herstellen eines Diodenlasers und Diodenlaser |
Citations (5)
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US4143456A (en) * | 1976-06-28 | 1979-03-13 | Citizen Watch Commpany Ltd. | Semiconductor device insulation method |
US4644445A (en) * | 1982-12-27 | 1987-02-17 | Seiko Epson Kabushiki Kaisha | Resin mounting structure for an integrated circuit |
US5218234A (en) * | 1991-12-23 | 1993-06-08 | Motorola, Inc. | Semiconductor device with controlled spread polymeric underfill |
WO1993015521A1 (en) * | 1992-01-24 | 1993-08-05 | Motorola, Inc. | Backplane grounding for flip-chip integrated circuit |
JPH06204272A (ja) * | 1993-01-07 | 1994-07-22 | Matsushita Electron Corp | 半導体装置の製造方法 |
-
1997
- 1997-07-08 DE DE19729073A patent/DE19729073A1/de not_active Withdrawn
-
1998
- 1998-03-25 WO PCT/DE1998/000870 patent/WO1999003145A1/de not_active Application Discontinuation
- 1998-03-25 HU HU0000672A patent/HUP0000672A3/hu unknown
- 1998-03-25 KR KR1019997002341A patent/KR20000068591A/ko not_active Application Discontinuation
- 1998-03-25 JP JP11507956A patent/JP2001501381A/ja active Pending
- 1998-03-25 EP EP98928066A patent/EP0923791A1/de not_active Withdrawn
Patent Citations (5)
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US4143456A (en) * | 1976-06-28 | 1979-03-13 | Citizen Watch Commpany Ltd. | Semiconductor device insulation method |
US4644445A (en) * | 1982-12-27 | 1987-02-17 | Seiko Epson Kabushiki Kaisha | Resin mounting structure for an integrated circuit |
US5218234A (en) * | 1991-12-23 | 1993-06-08 | Motorola, Inc. | Semiconductor device with controlled spread polymeric underfill |
WO1993015521A1 (en) * | 1992-01-24 | 1993-08-05 | Motorola, Inc. | Backplane grounding for flip-chip integrated circuit |
JPH06204272A (ja) * | 1993-01-07 | 1994-07-22 | Matsushita Electron Corp | 半導体装置の製造方法 |
Non-Patent Citations (2)
Title |
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"POWER AND ENCAPSULANT SUPPLY FROM A THROUGH HOLE IN A CARD", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 36, no. 11, 1 November 1993 (1993-11-01), pages 59, XP000424776 * |
PATENT ABSTRACTS OF JAPAN vol. 018, no. 556 (E - 1620) 24 October 1994 (1994-10-24) * |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19902450A1 (de) * | 1999-01-22 | 2000-08-03 | Festo Ag & Co | Miniaturisiertes elektronisches System und zu dessen Herstellung geeignetes Verfahren |
DE19902450B4 (de) * | 1999-01-22 | 2006-04-20 | Festo Ag & Co. | Miniaturisiertes elektronisches System und zu dessen Herstellung geeignetes Verfahren |
CN100369532C (zh) * | 2003-09-29 | 2008-02-13 | 松下电器产业株式会社 | 微型组件及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
DE19729073A1 (de) | 1999-01-14 |
EP0923791A1 (de) | 1999-06-23 |
HUP0000672A2 (hu) | 2000-06-28 |
HUP0000672A3 (en) | 2000-07-28 |
KR20000068591A (ko) | 2000-11-25 |
JP2001501381A (ja) | 2001-01-30 |
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