Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
• • C—CHEMISTRY; METALLURGY
  • C30—CRYSTAL GROWTH
  • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
  • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
  • C30B25/02—Epitaxial-layer growth
• • C—CHEMISTRY; METALLURGY
  • C30—CRYSTAL GROWTH
  • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
  • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
  • C30B29/10—Inorganic compounds or compositions
  • C30B29/36—Carbides
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
  • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
  • H10P14/2901—Materials
  • H10P14/2902—Materials being Group IVA materials
  • H10P14/2904—Silicon carbide
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
  • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
  • H10P14/2926—Crystal orientations
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
  • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
  • H10P14/3202—Materials thereof
  • H10P14/3204—Materials thereof being Group IVA semiconducting materials
  • H10P14/3208—Silicon carbide
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
  • H10P14/34—Deposited materials, e.g. layers
  • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
  • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
  • H10P14/3408—Silicon carbide
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
  • H10P90/19—Preparing inhomogeneous wafers
  • H10P90/1904—Preparing vertically inhomogeneous wafers
  • H10P90/1906—Preparing SOI wafers
  • H10P90/1914—Preparing SOI wafers using bonding
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
  • H10W10/01—Manufacture or treatment

Definitions

• the invention relates to a method of manufacturing a composite substrate of the SiCOI type comprising an epitaxy step carried out on the SiC layer of the composite substrate.
• Silicon carbide or SiC is a material which has physicochemical and electronic properties well suited to power electronics. These power devices operate vertically, the active layer being an epitaxial layer on a monocrystalline SiC substrate. Unfortunately, the crystalline growth of solid substrate is carried out by a sublimation type technique at more than 2000 ° C. and does not make it possible to obtain substrates with qualities, diameters and costs comparable with silicon substrates for example.
• the properties required for the solid SiC substrate are low electrical resistivity, excellent thermal conductivity and good epitaxial quality of the active layer epitaxied on this substrate.
• these substrates are not four inches in size and moreover are very expensive.
• a first solution consists of starting from an SOI substrate (obtained by the SIMOX or Smart-Cut " processes) and re-epitaxial of the cubic SiC after partial conversion of the surface silicon layer. In this case, only the 3C polytype is obtained.
• a second solution consists in making a stack of SiC material on an electrically insulating substrate. It is for example a stack of SiC / oxide / Si. This stacking is carried out by the Smart-Cut ® process . It has the advantage of making it possible to obtain SiC 6H, 4H and 3C as a thin layer. postponed. However, as explained above and taking into account the use of equipment commonly used in the microelectronics industry, in particular ion implantation equipment, the maximum thickness of the electrically active SiC films is of the order of 1 ⁇ m.
• the presence of the silicon support limits the epitaxy temperature to around 1413 ° C. maximum if one does not want the silicon to melt. However, this temperature is barely sufficient to obtain the 6H and 4H polytypes (1450 ° C. would allow better results). Cubic SiC inclusions in the layer are observed at the slightest surface defect. On the other hand, the unintentional doping of the SiC layers is increased at low temperature.
• the presence of oxide makes it a priori impossible to withstand the pseudo-substrate at the epitaxy temperatures required for silicon carbide.
• the oxide is strongly attacked in a hydrogen atmosphere which is the atmosphere for the epitaxy. This is confirmed by the article "Selective Epitaxial Growth of Silicon Carbide on Patterned Silicon Substrates using Hexachlorodisilane and Propane "by Chacko Jacob et al., Materials Science Forum Vols. 338-342 (2000), pages 249 to 252.
• the oxide vaporizes from 1200 ° C.
• silicon oxide as a bonding layer with silicon nitride, however for many applications, it is very important from an electrical point of view to have a layer of buried silicon oxide.
• a third solution consists in making a stack of SiC material on an electrically insulating substrate holding the high temperature. It is thus possible to produce a SiCOI substrate on a polycrystalline SiC or monocrystalline SiC support of poor quality or on another support holding the high temperature. It is the same stack as above where the support silicon is, for example, replaced by polycrystalline SiC. This solves the problem of silicon fusion. But there remains the problem of the degradation of the oxide. Obtaining such a stack is done by the Smart-Cut process. The SiC of the thin layer is of the desired polytype. There is apparently no mention in the corresponding technical literature of work on epitaxies of SiC of polytype 6H or 4H on SiCOI substrates.
• the inventors of the present invention have however managed to achieve epitaxies on all these different types of materials and have unexpectedly obtained several satisfactory results.
• the oxide did not deteriorate at high temperature (1410 ° C - 1600 ° C) when epitaxies were carried out on SiCOI substrates formed of an SiC support successively supporting a layer of silicon oxide and a layer thin SiC, allowing the realization of good quality epitaxies, comparable to epitaxies on massive SiC.
• the inventors also carried out epitaxies of SiC of polytype 6H and 4H on SiCOI substrates for which the support is made of silicon. Encouraging results have been obtained.
• the subject of the invention is therefore a method of manufacturing a composite substrate of the SiCOI type comprising the following steps: supplying an initial substrate comprising an Si or SiC support supporting a layer of Si0 2 on which a layer is applied thin SiC,
• - SiC epitaxy on the thin SiC layer characterized in that the epitaxy is carried out at the following temperatures: - from 1450 ° C. to obtain a epitaxy of polytype 6H or 4H on a thin transferred layer of polytype 6H or 4H respectively, if the support is in Sic, from 1350 ° C to obtain an epitaxy of polytype 3C on a thin transferred layer of polytype 3C, if the support is in Si or Sic, from 1350 ° C to obtain an epitaxy of polytype 6H or 4H on a thin transferred layer of polytype 6H or 4H respectively, if the support is in Si.
• a step can be provided for preparing the initial substrate in order to improve the surface quality of the transferred thin layer of SiC.
• This preparation step can consist in subjecting the surface of the transferred thin layer of SiC to an operation chosen from polishing, etching and etching with hydrogen.
• the invention also relates to the use of the composite substrate of the SiCOI type obtained by the above manufacturing process for the production of semiconductor devices.
• the invention also relates to a semiconductor device produced on a composite substrate of the SiCOI type obtained by the above manufacturing process.
• FIG. 1 is a cross-sectional view of a SiCOI substrate, the thin layer of SiC of which has received an epitaxy of SiC, according to the invention
• FIG. 2 is a cross-sectional view of a Schottky diode produced by applying the method according to the invention
• FIG. 3 is a cross-sectional view of a bipolar diode, of PIN type, produced by applying the method according to the invention
• FIG. 4 is a cross-sectional view of a MESFET transistor produced by applying the method according to the invention
• - Figure 5 is a cross-sectional view of a MOSFET transistor produced by applying the method according to the invention.
• Epitaxies of SiC have been produced on SiCOI substrates such as that shown in FIG. 1 and formed of a support 1 successively supporting a layer of silicon oxide 2 and a thin layer of SiC 3.
• the thin layer 3 is a postponed layer.
• the carry-over can be obtained by the Smart-Cut technique " .
• the pressure was atmospheric pressure or vacuum pressure.
• the gases used were hydrogen H 2 for a flow of 3 to
• silane SiH 4 at 4 to 2000 normal cm 3 / min (4 to 2000 sccm) and propane C 3 H 8 at 4 to 2000 normal cm 3 / min (4 to 2000 sccm) .
• the dopant used to deposit doped layers of SiC was nitrogen at the rate of 2 to 2000 normal cm 3 / min (2 to 2000 sccm).
• the epitaxy was performed by a CVD technique. Prior to epitaxy, the thin layer
• the thin layer 3 can be prepared by polishing or etching in order to improve the surface. It is also possible to carry out in situ an attack on the surface of the thin layer 3 with hydrogen.
• epitaxy qualities and the doping levels obtained are equivalent to those obtained starting from massive substrates.
• Epitaxies of SiC of polytype 6H and 4H on SiCOI substrates with thin layer of SiC of corresponding polytype and with silicon support were also carried out.
• the advantages of the epitaxy chain on solid substrate are preserved: epitaxial quality of the active layer equivalent to the quality epitaxied on this substrate, low resistance to the passing state according to the architecture of the component, the choice of support plate or sole doping for ohmic contact, - good thermal conductivity (depending on the architecture of the component).
• the thickness of SiC on oxide can be increased in a controlled manner and without limitation, which is not the case with stacks comprising a film of transferred SiC whose thickness is limited to About 1 ⁇ m.
• the re-epitaxy also allows technological stacking of different doping layers, which is obviously not the case with simple SiCOI.
• the epitaxial layer or layers allow the production of a pseudo-vertical device on SiC and insulating substrate (SiCOI) whatever the support of the transfer.
• FIG. 2 is a cross-sectional view of a Schottky diode produced by applying the method according to the invention.
• the initial SiCOI substrate comprises a support 101 in Si or in SiC successively supporting a layer of silicon oxide 102 and a thin layer transferred or transferred
• FIG. 2 levels of lithography make it possible to obtain the structure shown in FIG. 2 as well as the Schottky contact 105 on the epitaxial layer 114 and the ohmic contacts 106 on the epitaxial layer 104
• An etching 107 makes it possible to isolate the structure obtained ..
• the epitaxial layers are more doped than the commercially available substrates, which is another advantage.
• the initial SiCOI substrate comprises a support 201 in Si or in SiC successively supporting a layer of silicon oxide 202 and a thin layer transferred or transferred 203 in SiC. Three successive SiC epitaxies were carried out to obtain a first epitaxial layer
• Lithography levels make it possible to obtain the structure shown in FIG. 3 as well as the ohmic contact 205 on the epitaxial layer 224 and the ohmic contacts 206 on the epitaxial layer 204.
• FIG. 4 is a cross-sectional view of a MESFET transistor produced by applying the method according to the invention.
• the initial SiCOI substrate comprises a support 301 made of Si or SiC successively supporting a layer of silicon oxide 302 and a thin layer transferred or transferred 303 into SiC. Two successive SiC epitaxies were performed to obtain a first epitaxial layer
• FIG. 5 is a cross-sectional view of a MOSFET transistor produced by applying the method according to the invention.
• the initial SiCOI substrate comprises a support 401 made of Si or SiC successively supporting a layer of silicon oxide 402 and a thin layer transferred or transferred 403 into SiC.
• An epitaxy of SiC was carried out to obtain a p-doped 404 epitaxial layer.
• Two surface areas 405 and 406 of the epitaxial layer were n + doped by implantation.
• Ohmic contacts 407 and 408 were made on the surface areas 405 and 406 respectively.
• a layer of silicon oxide 410 was created until overlapping the surface areas 405 and 406.
• a grid 409 for example made of polysilicon, was deposited on the layer of gate oxide 410.
• the invention applies to any device for which the active layer obtained by the transfer of the Smart-Cut type onto a substrate of the insulating type on material does not have a satisfactory thickness or electrical qualities.

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• Chemical & Material Sciences (AREA)
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• Crystallography & Structural Chemistry (AREA)
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• Inorganic Chemistry (AREA)
• Crystals, And After-Treatments Of Crystals (AREA)
• Electrodes Of Semiconductors (AREA)
• Recrystallisation Techniques (AREA)
• Junction Field-Effect Transistors (AREA)
• Thin Film Transistor (AREA)

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• 2002
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• 2003
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  • 2003-09-01 JP JP2004537240A patent/JP2005537678A/ja active Pending
  • 2003-09-01 WO PCT/FR2003/050044 patent/WO2004027844A2/fr not_active Ceased
  • 2003-09-01 EP EP03780258A patent/EP1547145A2/de not_active Withdrawn
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