WO2024088942A1 - Procédé de fabrication d'un empilement semiconducteur hautement résistif et empilement associé - Google Patents
Procédé de fabrication d'un empilement semiconducteur hautement résistif et empilement associé Download PDFInfo
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- WO2024088942A1 WO2024088942A1 PCT/EP2023/079435 EP2023079435W WO2024088942A1 WO 2024088942 A1 WO2024088942 A1 WO 2024088942A1 EP 2023079435 W EP2023079435 W EP 2023079435W WO 2024088942 A1 WO2024088942 A1 WO 2024088942A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
Definitions
- TITLE METHOD FOR MANUFACTURING A HIGHLY RESISTIVE SEMICONDUCTOR STACK AND ASSOCIATED STACK
- the technical field of the invention is that of semiconductor stacks intended to form silicon on insulator substrates, also called “SOI” substrates for “Silicon On Insulator” in English, and more particularly SOI substrates used in the field of radio frequencies.
- Highly resistive semiconductor stacks such as silicon-on-insulator, or SOI, substrates, are widely used for radio frequency applications because they promote the integrity of the signals circulating in devices made on their surface.
- An SOI substrate comprises a first semiconductor layer, made of silicon, called a “support layer” or “base”, a second semiconductor layer, made of silicon, called “active layer”.
- the active layer is intended to accommodate microelectronic components, manufactured in or on the active layer. We also speak in this case of “initial” or “front end” components, also “FEOL” for “Front End Of Line” in English.
- the active layer is separated from the support layer by an insulating layer, for example made of silicon oxide, placed between the support layer and the active layer, and more particularly under the active layer.
- the insulating layer is then called “buried” or “BOX” for “Burned OXide”.
- the insulating layer makes it possible to confine the majority charge carriers in the active layer, which makes it possible to envisage a high operating frequency of the front end components, for example up to several tens of gigahertz.
- the charge carriers are then trapped at the grain boundaries, where the dangling silicon bonds are located.
- the trapping layer is deposited in low pressure vapor phase (also called “LPCVD” for “Low Pressure Chemical Vapor Deposition” in English), followed by rapid annealing at a temperature of 1000 ° C, so as to form the grains of silicon.
- the effectiveness of the trapping layer is based on the density of pendant silicon bonds and therefore on the density of grain boundaries.
- the heat treatments implemented during the manufacturing of microelectronic components at the active layer tend to reduce the number of grains and therefore reduce the number of grain boundaries.
- the polycrystalline silicon trapping layer therefore imposes a restricted thermal budget.
- Another approach to trapping charge carriers consists of forming bubbles in the support layer, in the vicinity of the interface between the support layer and the insulating layer. The pendant bonds at the free surface of each bubble then allow the trapping of the charge carriers.
- the article “Chemical and electrical properties of cavities in silicon and germanium”, SM Myers, DM Follstaedt, GA Petersen, CH Seager, HJ Stein & WR Wampler, Nuclear instruments and Methods in Physics Research B 106 (1995) 379-385 ] describes a process for forming bubbles in a silicon layer by implantation of helium ions. However, the bubbles formed are approximately 200 nm away from the interface between the support layer and the insulating layer.
- the maximum bubble density is located at a distance from the interface of between 1000 nm and 1500 nm.
- the trapping capacity at the interface level is therefore limited.
- modulating the implantation energy to bring the bubbles closer to the interface could cause exfoliation of the insulating layer.
- the implantation time can be long (of the order of 20 min to implant ions in a substrate of 300 mm in diameter, under an implantation current of 10 mA and a dose of 10 17 cm' 2 ).
- Another known solution is described in document FR3091011 A1 which discloses an SOI substrate comprising a layer of polycrystalline silicon carbide extending on the surface of the support layer.
- the carbide layer is preferably polycrystalline and thus makes it possible to trap the charge carriers, in the same way as a polycrystalline silicon trapping layer.
- the growth of the carbide layer is carried out by growth from the support layer using a carbon precursor or by CVD.
- the thickness of the disclosed carbide layer is limited to 5 nm.
- the carbide layer is chemically fragile and can be contaminated by species brought during additional manufacturing stages (such as the manufacturing of the insulating layer and/or the active layer) and having migrated up to the carbide layer.
- the invention relates to a method of manufacturing a semiconductor stack, comprising, from a first layer of silicon, called support layer: the formation of a layer of silicon carbide, extending over the layer support, having a thickness, measured from the support layer, greater than 5 nm, a fraction of carbon atoms of the silicon carbide layer, less than 20 nm from the support layer, being strictly greater than 50%; and annealing the support layer and the silicon carbide layer until forming cavities, each cavity extending into the support layer, from the silicon carbide layer, an oxygen concentration in contact with the silicon carbide layer.
- silicon carbide during the annealing step, being less than 10 ppm and preferably less than 5 ppm, or even zero.
- the silicon atoms of the support layer migrate towards the carbide layer thus forming, from the carbide layer, cavities, that is to say hollow zones located in the support layer.
- the cavities formed in the support layer provide pendant silicon bonds and thus make it possible to trap the charge carriers in the support layer.
- the arrangement of the cavities makes it possible to effectively trap the charge carriers as close as possible to the interface between the support layer and the carbide layer.
- the silicon carbide present is a semiconductor having an indirect band gap whose deviation is greater than 2 eV, or even 3 eV.
- the carbide layer thus prevents the circulation of charge carriers in the vicinity of the insulating layer.
- the stack since trapping does not rely on the presence of grain boundaries, which are sensitive to temperature, the stack then has improved morphological stability. Furthermore, during heat treatment, the temperature involving the coalescence of cavities is significantly higher than the temperature involving the coalescence of grains in a polycrystalline structure. The temperature involving the coalescence of the cavities is also higher than the temperatures used during additional manufacturing stages. Moreover, while the coalescence of the grains is accompanied by a disappearance of traps, the possible coalescence of the cavities takes place at a constant surface.
- the silicon carbide layer being richer in carbon, it makes it possible to activate the migration of the silicon atoms from the support layer during annealing and effectively form the cavities.
- the thickness of the silicon carbide layer greater than 5 nm improves its robustness, particularly chemical, with respect to additional manufacturing steps (such as the manufacturing of “front end” components). In fact, it is less affected by contaminants that can migrate.
- the silicon carbide layer can undergo oxidation by pitting (also known as pitting) when it is annealed in an environment comprising oxygen. Pitting damages the silicon carbide layer and can slow down the migration of silicon atoms and therefore the formation of cavities. Annealing carried out in an atmosphere poor in oxygen limits the appearance of pitting and therefore improves the reproducibility of the process.
- Annealing can be carried out for a period of between 15 min and 2 h at a temperature of between 900°C and 1100°C.
- the layer of silicon carbide resulting from the formation step is advantageously amorphous and the annealing of the layers is advantageously carried out so as to crystallize the layer of silicon carbide in a polycrystalline arrangement.
- the support layer is advantageously oriented in a plane.
- the thickness of the silicon carbide layer is preferably less than 500 nm.
- Each cavity may have facets, each facet being preferably oriented parallel to a crystallographic plane forming, for example, part of the family of crystallographic planes ⁇ 111 ⁇ or part of the family of crystallographic planes ⁇ 113 ⁇ .
- the cavities extend over a distance, measured perpendicular to the plane and from the layer of silicon carbide, preferably between 5 nm and 100 nm.
- the method preferably comprises the formation of an insulating layer extending over the layer of silicon carbide.
- the insulating layer is advantageously intended to form a “buried” layer called “BOX” for “Burned OXide” in English.
- the formation of the insulating layer is carried out by deposition, before said annealing.
- the annealing of the support layer, the silicon carbide layer and the insulating layer can be carried out under an atmosphere comprising an oxygen concentration of less than 1%.
- the formation of the insulating layer is carried out by transfer from a donor substrate, after annealing of the layers.
- the method can include the formation of a second crystalline layer, extending over the insulating layer.
- the insulating layer then forms a “BOX” layer.
- Another aspect of the invention relates to a semiconductor stack comprising: a first silicon layer, called the support layer; a layer of silicon carbide, extending over the support layer, having a thickness, measured from the support layer, greater than 5 nm; and cavities, each cavity extending into the support layer from the silicon carbide layer.
- the silicon carbide layer is advantageously polycrystalline.
- the support layer is oriented in a plane and the cavities extend over a distance, measured perpendicular to the plane and from the silicon carbide layer, of between 5 nm and 100 nm.
- each cavity when the cavities extend over a distance, measured perpendicular to the plane and from the layer of silicon carbide, greater than 15 nm, then each cavity has facets, each facet being oriented parallel to a crystallographic plane.
- each cavity has a pyramidal shape and has a base aligned with the interface between the support layer and the silicon carbide layer.
- the top of the pyramid extends into the support layer.
- the cavities are only located at the interface between the support layer and the silicon carbide layer. In other words, each cavity extends only into the support layer from the silicon carbide layer.
- the silicon carbide layer is non-porous.
- each cavity has a free surface surrounding an interior volume, at least one portion of the free surface separating said interior volume from the support layer and at least one other portion of the free surface separating the interior volume from the layer of silicon carbide.
- each portion of the free surface separating the interior volume of the cavity of the support layer comprises silicon atoms, at least part of which has a pendant bond.
- FIG. 1 schematically represents a first embodiment of a semiconductor stack according to the invention.
- FIG. 2 schematically represents a first mode of implementation of a manufacturing process according to the invention.
- FIG. 3a schematically represents a first example of a first step of the manufacturing process according to the invention.
- FIG. 3b schematically represents a second example of the first step of the manufacturing process according to the invention.
- FIG. 4 schematically represents a second step of the manufacturing process according to the invention.
- FIG. 5 schematically represents a third step of the manufacturing process according to the invention.
- FIG. 6 schematically represents a fourth step of the manufacturing process according to the invention.
- FIG. 8 schematically represents a fifth step of the manufacturing process according to the invention.
- FIG. 9 represents an image obtained by transmission microscopy of a semiconductor stack manufactured using the manufacturing process according to the invention.
- the invention aims to improve the semiconductor stacks intended to form an SOI substrate and in particular a substrate intended for radio frequency applications.
- FIG. 1 schematically represents a first embodiment of a semiconductor stack 10 according to the invention.
- the stack 10 comprises a first silicon layer 11, called the support layer; a layer of silicon carbide 12; and cavities 13.
- the support layer 11 extends for example along a given plane P. This is, for example, the plane of a silicon wafer from which an SOI substrate will be formed.
- the support layer 11 is advantageously a resistive support, that is to say having a resistivity greater than 1 k ⁇ cm.
- the silicon carbide layer 12 (also called SiC layer) extends over the support layer 11 along the given plane P.
- the SiC layer 12 is directly in contact with the support layer 11, thus forming an interface 112 between the two layers.
- the stack 10 is remarkable in that it comprises a plurality of cavities 13 extending into the support layer 11.
- Each cavity 13 is hollow, that is to say empty of any solid or liquid material. They may include a species in gaseous form having a low partial pressure. They are, however preferably completely empty.
- Each cavity 13 extends into the support layer 11, from the SiC layer 12. That is to say that each cavity 13 extends into the support layer 11 from the interface 112.
- Each cavity 13 then presents a free surface 131, 132 surrounding an interior volume 130 of the cavity 13. At least one portion 131 of the free surface separates said interior volume 130 from the support layer 11 and at least one other portion 132 of the free surface separates the interior volume 130 from the cavity of the SiC layer 12.
- the portion(s) 131 of the free surface separating the interior volume 130 from the cavity of the support layer 11 are formed of silicon atoms, at least part of which has a dangling bond.
- dangling bond we mean an atomic orbital not involved in a chemical bond with other elements.
- the pendant connections make it possible to trap the charge carriers circulating in the support layer 11 and in the vicinity of the SiC layer 12.
- the pendant bonds and the cavities also make it possible to trap impurities, such as hydrogen ions or atoms, helium atoms or metals such as lithium or copper, having migrated into the support layer 11 during, for example, additional manufacturing steps (such as the manufacturing of “front end” components).
- impurities such as hydrogen ions or atoms, helium atoms or metals such as lithium or copper
- the resistivity of the support layer 11 is therefore not degraded by additional manufacturing steps.
- thermodynamic stability of the cavities 13 and their formation by diffusion tend to favor faceting of the cavities.
- Portions 131 of the free surface 131, 132 of each cavity 13 then align preferentially along crystallographic planes of the support layer 11.
- the cavities 13 can be faceted by presenting portions parallel to crystallographic planes of the family of planes ⁇ 111 ⁇ (that is to say the planes (111), (-111), (1 -11) and (-1 -11)) or of the family of planes ⁇ 113 ⁇ (that is to say the planes (113), (-113), (1 -13) and (-1 -13)).
- the cavities 13 can then have the shape of an inverted pyramid, with a square base or a triangular base, said base of which coincides with the interface between the support layer 11 and the SiC layer 12.
- the faceting does not necessarily depend on the plane at the interface 112 of the support layer 11 with the SiC layer 12.
- Other families of crystallographic planes are possible. [0061] In order to determine the orientation of the crystallographic planes, it is advantageous to consider the cavities 13 extending over a distance 133, measured perpendicular to the plane P, greater than 15 nm. Indeed, beyond that, it can be difficult to distinguish the families of plans ⁇ 113 ⁇ .
- FIG. 1 represents by arrows the directions [111] and [001], normal to the crystallographic planes (001) and (111).
- Each cavity 13 preferably extends from the SiC layer 12 over a distance 133 of between 5 nm and 100 nm. Said distance 133 is measured perpendicular to the plane P in which the layer of SiC 12 extends, that is to say along [001] in the present example. Said distance 133 is measured from the carbide layer 12, that is to say from the interface 112 separating the support layer 11 and the carbide layer 12.
- the stack 10 also comprises an insulating layer 14 and an active layer 15.
- the stack 10 forms an SOI substrate.
- the insulating layer 14 extends over the SiC layer 12. It advantageously has a thickness of between 100 nm and 1000 nm. It comprises, for example, an oxide, such as silicon oxide Si ⁇ 2.
- the active layer 15 comprises a crystalline or polycrystalline semiconductor and extends over the insulating layer 14. The insulating layer 14 thus separates the SiC layer 12 and the active layer 15. It is said to be “buried” under the active layer 15.
- active layer 15 advantageously has a thickness of between 50 nm and 500 nm and comprises for example crystalline silicon or polycrystalline silicon or another crystalline semiconductor material used in the field of radio frequencies, such as indium phosphide or gallium nitride .
- the SiC 12 layer is advantageously polycrystalline. Thus, it contributes to the trapping of charge carriers, in the same way as a polycrystalline silicon trapping layer, as described in the prior art.
- the charge carriers are trapped by the dangling bonds located at the grain boundaries of the polycrystalline arrangement.
- FIG. 2 schematically represents a manufacturing process according to the invention, making it possible to manufacture the stack 10.
- the manufacturing method 20 comprises, from a support layer 11, a step 22 of forming a layer of silicon carbide 12 (called SiC layer), extending over the support layer 11.
- SiC layer silicon carbide 12
- Two Examples of silicon carbide layer 12 obtained are illustrated in [Fig. 3a] and [Fig. 3b],
- the SiC layer 12 is for example formed 22 by vapor phase deposition, also called “CVD” for "Chemical Vapor Deposition” in English, from the support layer 11. It is for example a plasma-assisted CVD deposition (or “PECVD” for “Plasma Enhanced CVD” in English).
- the SiC 12 layer is for example obtained by PECVD deposition of a carbon precursor, such as tetramethylsilane Si(CH3)4, also called “TMS”.
- TMS tetramethylsilane
- the support layer 11 extends in a plane P. It preferably has a crystallographic plane (001) in the plane P.
- the SiC layer 12 has a thickness 121, measured from the support layer 11 and perpendicular to the plane P. , greater than 5 nm and advantageously less than 500 nm.
- the method 20 further comprises a step 23 of annealing the support layer 11 and the SiC layer 12 until forming cavities 13 extending into the support layer 11, as illustrated in [Fig. 4], Each cavity 13 then extends into the support layer 11, from the SiC layer 12.
- the temperature increases the mobility of the silicon atoms of the support layer 11 and a part of these atoms, in particular those close to the SiC layer 12.
- the difference in fractions of silicon atoms between the support layer 11 and the SiC layer 12 tends to direct the migration of the silicon atoms from the support layer 11 towards the SiC layer 12, thus digging several cavities 13 in the support layer 11.
- the formation of each cavity 13 finds its starting point at the interface between the support layer 11 and the SiC layer 12.
- Each cavity 13 then extends into the support layer 11 in a direction substantially perpendicular to the plane P
- substantially perpendicular we mean perpendicular to within 20°.
- the annealing 23 of the support layer 11 and the SiC layer 12 is preferably simultaneous.
- each cavity 13 finds its starting point at the interface between the support layer 11 and the SiC layer 12, the method only forms cavities extending from the interface between the support layer 11 and the SiC layer 12. In other words, the method does not make it possible to form cavities distant from said interface between the support layer 11 and the SiC layer 12 (these cavities distant from the interface can be called pores or bubbles).
- the support layer 11 includes defects such as amorphous zones or grain boundaries, these defects can assist or facilitate the migration of silicon atoms towards the SiC layer 12.
- the annealing temperature 23 making it possible to form cavities 13 is advantageously between 900°C and 1100°C. Below 900°C, the mobility of the silicon atoms is not sufficient to form cavities 13 in a duration that can be compatible with an industrial rate. Beyond 1100°C, the mobility of the silicon atoms is such that it allows the migration of atoms between cavities 13, tending to form cavities that are few in number but of very large sizes (i.e. extending beyond 100 nm from the SiC layer 12). The trapping of charge carriers is improved when the density of cavities 13 (i.e. the number of cavities 13 per unit surface of the interface 112) increases. On the other hand, trapping deteriorates when the density of cavities 13 decreases.
- the SiC 12 layer is advantageously formed at a temperature between 300°C and 500°C. In this way, it presents, before annealing 23, an amorphous phase.
- Annealing 23 of the layers, and in particular of the SiC layer 12, between 900°C and 1100°C has the effect of crystallizing the SiC layer 12 in a polycrystalline arrangement.
- This crystallization has two beneficial effects. Initially, the grain boundaries of the polycrystalline arrangement contribute to the trapping of the charge carriers, reinforcing the trapping achieved by the cavities 13. Secondly, the crystallization also accelerates the migration of the silicon atoms of the support layer 11 towards the SiC layer 12, in a manner similar to a pumping of silicon atoms, having the effect of accelerating the kinetics of formation of the cavities 13.
- the SiC 12 layer is, before and after annealing, non-porous.
- the SiC 12 layer is polycrystalline (for example after annealing)
- the non-porosity is provided by the grain boundaries of the SiC 12 layer.
- Annealing 23 is advantageously carried out for a period of between 15 min and 2 h, so that the migration of the silicon atoms of the support layer 11 makes it possible to obtain cavities 13 extending at least 5 nm from the SiC 12 layer and at most 100 nm from this layer.
- the dimension of the cavities 13 (measured perpendicular to the plane P and from the SiC layer 12) is proportional to the duration of the annealing 23.
- An annealing duration of the order of 15 min is compatible with an industrial rate.
- An annealing time of the order of 2 h makes it possible to form cavities 13 of large sizes, close to 100 nm, extending the coverage of the trapping of the charge carriers in the support layer 11.
- the annealing time of around 2 hours is also compatible with an industrial rate. Indeed, annealing can be carried out in an oven, making it possible to treat several plates simultaneously, for example several dozen.
- the ion implantation that can be implemented in the prior art carries out treatment plate by plate.
- the migration of silicon atoms, and therefore the kinetics of formation of cavities 13, is accelerated when the SiC layer 12 has a fraction of carbon atoms (also called carbon fraction) which is, before annealing 23, at least equal to the fraction of silicon atoms.
- the SiC layer 12 thus has, before annealing 23, a carbon fraction greater than 50% and advantageously less than 70%.
- the fraction of silicon in the SiC layer 12 is thus, before annealing 23, less than 50.
- the kinetics of formation of the cavities 13 is especially accelerated when the difference in fractions between the carbon and silicon atoms is significant in the vicinity of the interface 112 between said SiC layer 12 and the support layer 11.
- the fraction carbon of the SiC layer 12 beyond 20 nm of the support layer 11 does not, however, show any significant impact on the kinetics of formation of the cavities 13.
- the SiC layer 12 has a greater thickness 121 at 20 nm (measured perpendicular to the plane P and from the interface 112 with the support layer 11), as illustrated by [Fig. 3a]
- it presents a part, extending at least 20 nm from the support layer 11 and in which the carbon fraction is greater than 50% and advantageously less than or equal to 70%.
- the SiC layer 12 When the SiC layer 12 has a thickness 121 less than or equal to 20 nm, as illustrated by [Fig. 3b], it then presents, over its entire thickness 121, a carbon fraction greater than 50% and advantageously less than or equal to 70 %.
- the carbon fraction of the SiC layer 12, less than 20 nm from the support layer 11 (measured perpendicular to the plane P and from the interface 112), is advantageously between 50% and 70%. .
- the SiC 12 layer reacts with oxygen and can oxidize, for example by pitting.
- Annealing 23 is therefore carried out by minimizing the contact of oxygen with the SiC layer 12.
- Annealing 23 of the stack 10 is carried out by maintaining a concentration of oxygen in contact with the SiC layer 12 which is less than 10 ppm, preferably less than 5 ppm, or even zero.
- Annealing 23 is for example carried out in a neutral atmosphere, comprising for example at least one neutral gas such as nitrogen or argon.
- the neutral atmosphere is then sized so that it then has an oxygen concentration of less than 10 ppm, or even less, at least for the duration of annealing 23.
- Method 20, according to the mode of implementation of [Fig. 2], can also include a step of forming 25 of an insulating layer 14 and a step of forming 26 of an active semiconductor layer 15 so that the final stack 10 forms an SOI substrate, as illustrated by [ Fig. 1],
- the formation 25 of the insulating layer 14, illustrated by [Fig. 6], is advantageously carried out by transfer from a donor substrate 30.
- the principle of transfer from a donor substrate 30 is known under the name SmartCut(TM).
- the formation 26 of the active layer 15 is advantageously also carried out by transfer from a donor substrate and if possible from the same donor substrate 30.
- the formation 25, 26 of the two aforementioned layers is carried out simultaneously.
- the method 20 comprises, before the formation 25 of the insulating layer 14, a step of smoothing 24 of said surface 122.
- Smoothing 24, illustrated by [Fig. 5] can be carried out by chemical-mechanical planarization or CMP for “Chemical Mechanical Polishing” in English.
- CMP Chemical-mechanical planarization
- the smoothing 24 is carried out so that the SiC layer 12 has a surface roughness less than or equal to 5 A. Surface roughness is also called average roughness or “RMS” roughness for “Root Mean Square” in English.
- the roughness of the surface 122 of the SiC layer can be evaluated using an atomic force microscope, or “AFM” for “Atomic Force Microscope” in English. The roughness can be evaluated on a portion of the surface 122 of approximately 1 pm 2
- the simultaneous formations 25, 26 of the insulating and active layers 14, 15 by transfer can be produced from the same donor substrate 30, the latter then comprising a semiconductor layer 35, for example made of crystalline or polycrystalline silicon or of crystalline indium phosphide or crystalline gallium nitride, over which extends an insulating layer 34, for example made of silicon oxide.
- the insulating layer 34 has, for example, a thickness of between 100 nm and 1000 nm.
- the underlying semiconductor layer 35 has for example a thickness greater than 50 nm, or even greater than 500 nm.
- the simultaneous formations 25, 26 can then comprise a sub-step of implanting light ions (for example hydrogen or helium ions) in the semiconductor layer 35 of the donor substrate 30 to a depth of between 50 nm and 500 nm under the insulating layer 34.
- the implantation is for example carried out at a dose of a few 10 16 /cm 2 and at an energy of a few tens of keV.
- the simultaneous formations 25, 26 then comprise a sub-step of cleaning the free surface 341 of the insulating layer 34 of the donor substrate 30, in order to allow direct bonding between said insulating layer 34 of said donor substrate 30 and the layer of SiC 12 from the stack 10.
- the cleaning of the free surface 341 of the insulating layer 34 advantageously involves known recipes from silicon technologies such as the so-called “RCA” recipe (for “Radio Corporation of America” in English) or another recipe called CARO, comprising a mixture of hydrogen peroxide and sulfuric acid.
- the bonding is then followed by an annealing called “separation annealing”, aimed at separating the semiconductor layer 35 of the donor substrate 30 in two parts, following a plane comprising the light ions previously implanted.
- the stack 10 thus comprises, after separation annealing, an insulating layer 14, as illustrated by [Fig. 1], extends over the SiC 12 layer (because it is stuck on the latter).
- the semiconductor layer 35 forms the active layer 15 of the stack 10.
- a planarization of the active layer 15 and/or a complementary annealing of the stack 10 can be carried out to prepare the active layer 15 and/or improve the adhesion of the layers of the stack 10.
- FIG. 7 schematically represents a second mode of implementation of the method 20.
- the step of forming 25 of the insulating layer 14 occurs before the step of annealing 23 of the stack 10.
- This inversion of the steps makes it possible to simplify the annealing step 23 in that the neutral atmosphere, previously described, no longer needs to have an oxygen concentration less than 10 ppm. It can be less than 1% only.
- the manufacturing process 20 is thus simpler to implement, particularly with industrial equipment.
- the insulating layer 14 is formed on the SiC layer 12, as illustrated by [Fig. 8], It forms a barrier making it possible to reduce or even stop the diffusion of species coming from the surrounding atmosphere towards the SiC layer 12.
- the stack 10 can then simply be annealed 23 in a neutral atmosphere having a concentration of oxygen less than 1%.
- the formation 25 of the insulating layer 14 before annealing is preferably carried out by CVD deposition, for example of a tetraethyl orthosilicate precursor Si(OCH2CH3)4 (also called “TEOS”).
- the CVD deposition is advantageously assisted by plasma (called PECVD) to produce, from the precursor, a layer of silicon dioxide SiO2.
- PECVD plasma
- This deposition can be carried out at a temperature between 300°C and 500 °C, so as not to anticipate the annealing 23 of the stack 10.
- the deposition is carried out so as to form an insulating layer 14 having a thickness 121, measured perpendicular to the plane P, between 100 nm and 1000 nm.
- the formation 25 of the insulating layer 14 is advantageously carried out in the same equipment as that used to form the SiC layer 12. This makes it possible to prevent water vapor coming from the external atmosphere (for example example of the clean room), is not deposited on the SiC 12 layer (at the risk of oxidizing the latter).
- the method 20 can also include, to manufacture a stack 10 of the SOI substrate type, the formation 26 of the active layer 15. Unlike the mode of implementation of [Fig. 2], the method 20 according to [Fig. 7] only forms the active layer 15 after annealing 23.
- the active layer 15 can be formed by transfer from a donor substrate 30 as illustrated by [Fig. 6], The donor substrate 30, however, here only comprises the crystalline or polycrystalline semiconductor layer 35.
- the formation 25 of the insulating layer 14 before the annealing 23 thus makes it possible to simplify the step 26 of forming the active layer 15 by transfer, in that there is only one layer which is transferred.
- the formation 26 of the active layer 15 by transfer preferably comprises an implantation of light ions, as described above. However, the implantation depth is adjusted in order to transfer, onto the stack 10, an active layer 15 having a thickness of between 50 nm and 500 nm.
- the bonding of the donor substrate 30 is also preferably prepared as described above. The free surface of the donor substrate 30 is in particular also activated by means of an oxygen or nitrogen plasma in order to improve bonding.
- the insulating layer 14 of the stack 10 may also comprise, before the formation 26 of the active layer 15, a smoothing 24 of a surface 141 of the insulating layer intended to receive the active layer 15.
- the smoothing 24 is advantageously similar to the smoothing described with reference to [Fig. 5],
- the method 20 can also include, in a manner common to the embodiments of [Fig. 2] and [Fig. 7], a step of supplying 21 of the support layer 11, prior to the step of forming the SiC layer 12.
- the supply of the support layer 11, the supply step 21 can include the preparation of the support layer 11 so as to allow, or even promote, during annealing 23, the diffusion of the silicon atoms of the support layer 11 towards the SiC layer 12.
- the preparation may include the removal of organic or metallic contaminants, dopants or particles.
- Removal can be done by implementing known recipes such as a wet recipe called “CARO” (aimed at removing organic contaminants) or sequences of the “RCA” recipe, including for example a cleaning called “HF” ( aimed at removing dopants), so-called “SC1” cleaning (aimed at removing organic contaminants and particles) and/or so-called “SC2” cleaning (aimed at removing metallic contaminants).
- CARO wet recipe
- HF cleaning
- SC1 aimed at removing organic contaminants and particles
- SC2 so-called “SC2” cleaning
- FIG. 9 presents an image obtained by transmission electron microscopy (called “TEM” for “Transmission Electron Microscopy” in English) in bright field, of a semiconductor stack 10 according to the invention.
- This stack was obtained by means of the method according to the present invention.
- the stack 10 comprises a support layer 11 of monocrystalline silicon, a polycrystalline SiC layer 12 and a plurality of cavities 13 extending in the support layer 11, from the interface 112 between the support layer 11 and the SiC layer 12
- the support layer 11 has a plane [001] at the interface 112 with the SiC layer 12 so that the cavities have facets extending along crystallographic planes ⁇ 111 ⁇ (represented by an arrow oriented in the direction [111). ], normal to the planes (111)).
- the SiC layer also has different crystal structures, for example a majority of grains crystallized according to the 3C polytype and a minority of grains in other polytypes including 4H and 6H. This difference in structure also contributes to the appearance of the SiC 12 layer observed in [Fig. 9],
- the SiC 12 layer is non-porous.
- the support layer 11 is also non-porous.
- the height of the cavities 13 is between 10 nm and 40 nm. This height is measured perpendicular to the plane P and from the SiC 12 layer.
- Each cavity 13 has a pyramidal shape and has a base aligned with the interface between the support layer 11 and the SiC layer 12. In other words, the base of the pyramid coincides with this interface.
- the top of the pyramid is located in the support layer 11, at varying depths depending on the size of the cavities 13.
- the cavities 13 are located only at the interface between the support layer 11 and the SiC layer 12.
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- Manufacturing & Machinery (AREA)
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Abstract
Description
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FRFR2211053 | 2022-10-25 | ||
FR2211053A FR3141281A1 (fr) | 2022-10-25 | 2022-10-25 | Procédé de fabrication d’un empilement semiconducteur hautement résistif et empilement associé |
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110250416A1 (en) * | 2003-09-30 | 2011-10-13 | Michel Bruel | Methods of making substrate structures having a weakened intermediate layer |
US9882010B2 (en) * | 2015-05-19 | 2018-01-30 | Seiko Epson Corporation | Silicon carbide substrate and method for producing silicon carbide substrate |
FR3091011A1 (fr) | 2018-12-21 | 2020-06-26 | Soitec | Substrat de type semi-conducteur sur isolant pour des applications radiofréquences |
WO2022023630A1 (fr) * | 2020-07-28 | 2022-02-03 | Soitec | Procede de report d'une couche mince sur un substrat support muni d'une couche de piegeage de charges |
-
2022
- 2022-10-25 FR FR2211053A patent/FR3141281A1/fr active Pending
-
2023
- 2023-10-23 WO PCT/EP2023/079435 patent/WO2024088942A1/fr active Application Filing
- 2023-10-25 TW TW112140801A patent/TW202437338A/zh unknown
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110250416A1 (en) * | 2003-09-30 | 2011-10-13 | Michel Bruel | Methods of making substrate structures having a weakened intermediate layer |
US9882010B2 (en) * | 2015-05-19 | 2018-01-30 | Seiko Epson Corporation | Silicon carbide substrate and method for producing silicon carbide substrate |
FR3091011A1 (fr) | 2018-12-21 | 2020-06-26 | Soitec | Substrat de type semi-conducteur sur isolant pour des applications radiofréquences |
WO2022023630A1 (fr) * | 2020-07-28 | 2022-02-03 | Soitec | Procede de report d'une couche mince sur un substrat support muni d'une couche de piegeage de charges |
Non-Patent Citations (1)
Title |
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S.M. MYERSD.M. FOLLSTAEDTG.A. PETERSENC.H. SEAGERH.J. STEINW.R. WAMPLER: "Chemical and electrical properties of cavities in silicon and germanium", NUCLEAR INSTRUMENTS AND METHODS IN PHYSICS RESEARCH, vol. 106, 1995, pages 379 - 385, XP004001842, DOI: 10.1016/0168-583X(96)80033-4 |
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