EP1547145A2 - PROCEDE DE FABRICATION D' UN SUBSTRAT COMPOSITE DU TYPE SiCOI COMPRENANT UNE ETAPE D' EPITAXIE - Google Patents
PROCEDE DE FABRICATION D' UN SUBSTRAT COMPOSITE DU TYPE SiCOI COMPRENANT UNE ETAPE D' EPITAXIEInfo
- Publication number
- EP1547145A2 EP1547145A2 EP03780258A EP03780258A EP1547145A2 EP 1547145 A2 EP1547145 A2 EP 1547145A2 EP 03780258 A EP03780258 A EP 03780258A EP 03780258 A EP03780258 A EP 03780258A EP 1547145 A2 EP1547145 A2 EP 1547145A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- sic
- layer
- epitaxy
- polytype
- thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000000407 epitaxy Methods 0.000 title claims abstract description 60
- 239000000758 substrate Substances 0.000 title claims abstract description 58
- 238000000034 method Methods 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000002131 composite material Substances 0.000 title claims abstract description 16
- 238000005530 etching Methods 0.000 claims description 6
- 239000001257 hydrogen Substances 0.000 claims description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 3
- 238000002360 preparation method Methods 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 12
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 85
- 229910010271 silicon carbide Inorganic materials 0.000 description 80
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 76
- 229910052710 silicon Inorganic materials 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 239000010703 silicon Substances 0.000 description 14
- 239000000463 material Substances 0.000 description 11
- 229910052814 silicon oxide Inorganic materials 0.000 description 10
- ATUOYWHBWRKTHZ-UHFFFAOYSA-N Propane Chemical compound CCC ATUOYWHBWRKTHZ-UHFFFAOYSA-N 0.000 description 4
- 239000007787 solid Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 239000001294 propane Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 238000000859 sublimation Methods 0.000 description 1
- 230000008022 sublimation Effects 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- LXEXBJXDGVGRAR-UHFFFAOYSA-N trichloro(trichlorosilyl)silane Chemical compound Cl[Si](Cl)(Cl)[Si](Cl)(Cl)Cl LXEXBJXDGVGRAR-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/7602—Making of isolation regions between components between components manufactured in an active substrate comprising SiC compounds
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/36—Carbides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02378—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02433—Crystal orientation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/02447—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02529—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
Definitions
- the invention relates to a method of manufacturing a composite substrate of the SiCOI type comprising an epitaxy step carried out on the SiC layer of the composite substrate.
- Silicon carbide or SiC is a material which has physicochemical and electronic properties well suited to power electronics. These power devices operate vertically, the active layer being an epitaxial layer on a monocrystalline SiC substrate. Unfortunately, the crystalline growth of solid substrate is carried out by a sublimation type technique at more than 2000 ° C. and does not make it possible to obtain substrates with qualities, diameters and costs comparable with silicon substrates for example.
- the properties required for the solid SiC substrate are low electrical resistivity, excellent thermal conductivity and good epitaxial quality of the active layer epitaxied on this substrate.
- these substrates are not four inches in size and moreover are very expensive.
- a first solution consists of starting from an SOI substrate (obtained by the SIMOX or Smart-Cut " processes) and re-epitaxial of the cubic SiC after partial conversion of the surface silicon layer. In this case, only the 3C polytype is obtained.
- a second solution consists in making a stack of SiC material on an electrically insulating substrate. It is for example a stack of SiC / oxide / Si. This stacking is carried out by the Smart-Cut ® process . It has the advantage of making it possible to obtain SiC 6H, 4H and 3C as a thin layer. postponed. However, as explained above and taking into account the use of equipment commonly used in the microelectronics industry, in particular ion implantation equipment, the maximum thickness of the electrically active SiC films is of the order of 1 ⁇ m.
- the presence of the silicon support limits the epitaxy temperature to around 1413 ° C. maximum if one does not want the silicon to melt. However, this temperature is barely sufficient to obtain the 6H and 4H polytypes (1450 ° C. would allow better results). Cubic SiC inclusions in the layer are observed at the slightest surface defect. On the other hand, the unintentional doping of the SiC layers is increased at low temperature.
- the presence of oxide makes it a priori impossible to withstand the pseudo-substrate at the epitaxy temperatures required for silicon carbide.
- the oxide is strongly attacked in a hydrogen atmosphere which is the atmosphere for the epitaxy. This is confirmed by the article "Selective Epitaxial Growth of Silicon Carbide on Patterned Silicon Substrates using Hexachlorodisilane and Propane "by Chacko Jacob et al., Materials Science Forum Vols. 338-342 (2000), pages 249 to 252.
- the oxide vaporizes from 1200 ° C.
- silicon oxide as a bonding layer with silicon nitride, however for many applications, it is very important from an electrical point of view to have a layer of buried silicon oxide.
- a third solution consists in making a stack of SiC material on an electrically insulating substrate holding the high temperature. It is thus possible to produce a SiCOI substrate on a polycrystalline SiC or monocrystalline SiC support of poor quality or on another support holding the high temperature. It is the same stack as above where the support silicon is, for example, replaced by polycrystalline SiC. This solves the problem of silicon fusion. But there remains the problem of the degradation of the oxide. Obtaining such a stack is done by the Smart-Cut process. The SiC of the thin layer is of the desired polytype. There is apparently no mention in the corresponding technical literature of work on epitaxies of SiC of polytype 6H or 4H on SiCOI substrates.
- the inventors of the present invention have however managed to achieve epitaxies on all these different types of materials and have unexpectedly obtained several satisfactory results.
- the oxide did not deteriorate at high temperature (1410 ° C - 1600 ° C) when epitaxies were carried out on SiCOI substrates formed of an SiC support successively supporting a layer of silicon oxide and a layer thin SiC, allowing the realization of good quality epitaxies, comparable to epitaxies on massive SiC.
- the inventors also carried out epitaxies of SiC of polytype 6H and 4H on SiCOI substrates for which the support is made of silicon. Encouraging results have been obtained.
- the subject of the invention is therefore a method of manufacturing a composite substrate of the SiCOI type comprising the following steps: supplying an initial substrate comprising an Si or SiC support supporting a layer of Si0 2 on which a layer is applied thin SiC,
- - SiC epitaxy on the thin SiC layer characterized in that the epitaxy is carried out at the following temperatures: - from 1450 ° C. to obtain a epitaxy of polytype 6H or 4H on a thin transferred layer of polytype 6H or 4H respectively, if the support is in Sic, from 1350 ° C to obtain an epitaxy of polytype 3C on a thin transferred layer of polytype 3C, if the support is in Si or Sic, from 1350 ° C to obtain an epitaxy of polytype 6H or 4H on a thin transferred layer of polytype 6H or 4H respectively, if the support is in Si.
- a step can be provided for preparing the initial substrate in order to improve the surface quality of the transferred thin layer of SiC.
- This preparation step can consist in subjecting the surface of the transferred thin layer of SiC to an operation chosen from polishing, etching and etching with hydrogen.
- the invention also relates to the use of the composite substrate of the SiCOI type obtained by the above manufacturing process for the production of semiconductor devices.
- the invention also relates to a semiconductor device produced on a composite substrate of the SiCOI type obtained by the above manufacturing process.
- FIG. 1 is a cross-sectional view of a SiCOI substrate, the thin layer of SiC of which has received an epitaxy of SiC, according to the invention
- FIG. 2 is a cross-sectional view of a Schottky diode produced by applying the method according to the invention
- FIG. 3 is a cross-sectional view of a bipolar diode, of PIN type, produced by applying the method according to the invention
- FIG. 4 is a cross-sectional view of a MESFET transistor produced by applying the method according to the invention
- - Figure 5 is a cross-sectional view of a MOSFET transistor produced by applying the method according to the invention.
- Epitaxies of SiC have been produced on SiCOI substrates such as that shown in FIG. 1 and formed of a support 1 successively supporting a layer of silicon oxide 2 and a thin layer of SiC 3.
- the thin layer 3 is a postponed layer.
- the carry-over can be obtained by the Smart-Cut technique " .
- the pressure was atmospheric pressure or vacuum pressure.
- the gases used were hydrogen H 2 for a flow of 3 to
- silane SiH 4 at 4 to 2000 normal cm 3 / min (4 to 2000 sccm) and propane C 3 H 8 at 4 to 2000 normal cm 3 / min (4 to 2000 sccm) .
- the dopant used to deposit doped layers of SiC was nitrogen at the rate of 2 to 2000 normal cm 3 / min (2 to 2000 sccm).
- the epitaxy was performed by a CVD technique. Prior to epitaxy, the thin layer
- the thin layer 3 can be prepared by polishing or etching in order to improve the surface. It is also possible to carry out in situ an attack on the surface of the thin layer 3 with hydrogen.
- epitaxy qualities and the doping levels obtained are equivalent to those obtained starting from massive substrates.
- Epitaxies of SiC of polytype 6H and 4H on SiCOI substrates with thin layer of SiC of corresponding polytype and with silicon support were also carried out.
- the advantages of the epitaxy chain on solid substrate are preserved: epitaxial quality of the active layer equivalent to the quality epitaxied on this substrate, low resistance to the passing state according to the architecture of the component, the choice of support plate or sole doping for ohmic contact, - good thermal conductivity (depending on the architecture of the component).
- the thickness of SiC on oxide can be increased in a controlled manner and without limitation, which is not the case with stacks comprising a film of transferred SiC whose thickness is limited to About 1 ⁇ m.
- the re-epitaxy also allows technological stacking of different doping layers, which is obviously not the case with simple SiCOI.
- the epitaxial layer or layers allow the production of a pseudo-vertical device on SiC and insulating substrate (SiCOI) whatever the support of the transfer.
- FIG. 2 is a cross-sectional view of a Schottky diode produced by applying the method according to the invention.
- the initial SiCOI substrate comprises a support 101 in Si or in SiC successively supporting a layer of silicon oxide 102 and a thin layer transferred or transferred
- FIG. 2 levels of lithography make it possible to obtain the structure shown in FIG. 2 as well as the Schottky contact 105 on the epitaxial layer 114 and the ohmic contacts 106 on the epitaxial layer 104
- An etching 107 makes it possible to isolate the structure obtained ..
- the epitaxial layers are more doped than the commercially available substrates, which is another advantage.
- the initial SiCOI substrate comprises a support 201 in Si or in SiC successively supporting a layer of silicon oxide 202 and a thin layer transferred or transferred 203 in SiC. Three successive SiC epitaxies were carried out to obtain a first epitaxial layer
- Lithography levels make it possible to obtain the structure shown in FIG. 3 as well as the ohmic contact 205 on the epitaxial layer 224 and the ohmic contacts 206 on the epitaxial layer 204.
- FIG. 4 is a cross-sectional view of a MESFET transistor produced by applying the method according to the invention.
- the initial SiCOI substrate comprises a support 301 made of Si or SiC successively supporting a layer of silicon oxide 302 and a thin layer transferred or transferred 303 into SiC. Two successive SiC epitaxies were performed to obtain a first epitaxial layer
- FIG. 5 is a cross-sectional view of a MOSFET transistor produced by applying the method according to the invention.
- the initial SiCOI substrate comprises a support 401 made of Si or SiC successively supporting a layer of silicon oxide 402 and a thin layer transferred or transferred 403 into SiC.
- An epitaxy of SiC was carried out to obtain a p-doped 404 epitaxial layer.
- Two surface areas 405 and 406 of the epitaxial layer were n + doped by implantation.
- Ohmic contacts 407 and 408 were made on the surface areas 405 and 406 respectively.
- a layer of silicon oxide 410 was created until overlapping the surface areas 405 and 406.
- a grid 409 for example made of polysilicon, was deposited on the layer of gate oxide 410.
- the invention applies to any device for which the active layer obtained by the transfer of the Smart-Cut type onto a substrate of the insulating type on material does not have a satisfactory thickness or electrical qualities.
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Inorganic Chemistry (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Electrodes Of Semiconductors (AREA)
- Recrystallisation Techniques (AREA)
- Junction Field-Effect Transistors (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0210884A FR2844095B1 (fr) | 2002-09-03 | 2002-09-03 | Procede de fabrication d'un substrat composite du type sicoi comprenant une etape d'epitaxie |
FR0210884 | 2002-09-03 | ||
PCT/FR2003/050044 WO2004027844A2 (fr) | 2002-09-03 | 2003-09-01 | PROCEDE DE FABRICATION D'UN SUBSTRAT COMPOSITE DU TYPE SiCOI COMPRENANT UNE ETAPE D'EPITAXIE |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1547145A2 true EP1547145A2 (fr) | 2005-06-29 |
Family
ID=31503071
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP03780258A Withdrawn EP1547145A2 (fr) | 2002-09-03 | 2003-09-01 | PROCEDE DE FABRICATION D' UN SUBSTRAT COMPOSITE DU TYPE SiCOI COMPRENANT UNE ETAPE D' EPITAXIE |
Country Status (6)
Country | Link |
---|---|
US (1) | US20060125057A1 (fr) |
EP (1) | EP1547145A2 (fr) |
JP (1) | JP2005537678A (fr) |
FR (1) | FR2844095B1 (fr) |
TW (1) | TW200416878A (fr) |
WO (1) | WO2004027844A2 (fr) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7230274B2 (en) * | 2004-03-01 | 2007-06-12 | Cree, Inc | Reduction of carrot defects in silicon carbide epitaxy |
CA2584950A1 (fr) * | 2006-04-26 | 2007-10-26 | Kansai Paint Co., Ltd. | Composition d'appret en poudre et methode pour former un film de revetement |
US7696000B2 (en) * | 2006-12-01 | 2010-04-13 | International Business Machines Corporation | Low defect Si:C layer with retrograde carbon profile |
FR2977069B1 (fr) | 2011-06-23 | 2014-02-07 | Soitec Silicon On Insulator | Procede de fabrication d'une structure semi-conductrice mettant en oeuvre un collage temporaire |
JP2017055086A (ja) | 2015-09-11 | 2017-03-16 | 昭和電工株式会社 | SiCエピタキシャルウェハの製造方法及びSiCエピタキシャルウェハの製造装置 |
JP6723416B2 (ja) * | 2019-06-28 | 2020-07-15 | 昭和電工株式会社 | SiCエピタキシャルウェハの製造方法 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63103893A (ja) * | 1986-10-20 | 1988-05-09 | Sanyo Electric Co Ltd | 6H−SiC基板の製造方法 |
JPH01220458A (ja) * | 1988-02-29 | 1989-09-04 | Fujitsu Ltd | 半導体装置 |
JPH06188163A (ja) * | 1992-12-21 | 1994-07-08 | Toyota Central Res & Dev Lab Inc | 半導体装置作製用SiC単結晶基板とその製造方法 |
US5840221A (en) * | 1996-12-02 | 1998-11-24 | Saint-Gobain/Norton Industrial Ceramics Corporation | Process for making silicon carbide reinforced silicon carbide composite |
US5880491A (en) * | 1997-01-31 | 1999-03-09 | The United States Of America As Represented By The Secretary Of The Air Force | SiC/111-V-nitride heterostructures on SiC/SiO2 /Si for optoelectronic devices |
JP3719323B2 (ja) * | 1997-03-05 | 2005-11-24 | 株式会社デンソー | 炭化珪素半導体装置 |
JPH10261615A (ja) * | 1997-03-17 | 1998-09-29 | Fuji Electric Co Ltd | SiC半導体の表面モホロジー制御方法およびSiC半導体薄膜の成長方法 |
JPH10279376A (ja) * | 1997-03-31 | 1998-10-20 | Toyo Tanso Kk | 炭素−炭化ケイ素複合材料を用いた連続鋳造用部材 |
FR2774214B1 (fr) * | 1998-01-28 | 2002-02-08 | Commissariat Energie Atomique | PROCEDE DE REALISATION D'UNE STRUCTURE DE TYPE SEMI-CONDUCTEUR SUR ISOLANT ET EN PARTICULIER SiCOI |
US6328796B1 (en) * | 1999-02-01 | 2001-12-11 | The United States Of America As Represented By The Secretary Of The Navy | Single-crystal material on non-single-crystalline substrate |
JP2000223683A (ja) * | 1999-02-02 | 2000-08-11 | Canon Inc | 複合部材及びその分離方法、貼り合わせ基板及びその分離方法、移設層の移設方法、並びにsoi基板の製造方法 |
DE69930266T2 (de) * | 1999-07-30 | 2006-11-30 | Nissin Electric Co., Ltd. | Material zum ziehen von sic-einkristallen und verfahren zur herstellung von sic-einkristallen |
FR2817395B1 (fr) * | 2000-11-27 | 2003-10-31 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede |
JP2002220299A (ja) * | 2001-01-19 | 2002-08-09 | Hoya Corp | 単結晶SiC及びその製造方法、SiC半導体装置並びにSiC複合材料 |
-
2002
- 2002-09-03 FR FR0210884A patent/FR2844095B1/fr not_active Expired - Fee Related
-
2003
- 2003-09-01 US US10/526,657 patent/US20060125057A1/en not_active Abandoned
- 2003-09-01 JP JP2004537240A patent/JP2005537678A/ja active Pending
- 2003-09-01 WO PCT/FR2003/050044 patent/WO2004027844A2/fr active Application Filing
- 2003-09-01 EP EP03780258A patent/EP1547145A2/fr not_active Withdrawn
- 2003-09-02 TW TW092124198A patent/TW200416878A/zh unknown
Non-Patent Citations (1)
Title |
---|
See references of WO2004027844A2 * |
Also Published As
Publication number | Publication date |
---|---|
WO2004027844A2 (fr) | 2004-04-01 |
WO2004027844A3 (fr) | 2004-05-21 |
FR2844095A1 (fr) | 2004-03-05 |
JP2005537678A (ja) | 2005-12-08 |
FR2844095B1 (fr) | 2005-01-28 |
US20060125057A1 (en) | 2006-06-15 |
TW200416878A (en) | 2004-09-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6650463B2 (ja) | 電荷トラップ層を備えた高抵抗率の半導体・オン・インシュレーターウェハーの製造方法 | |
EP0996150B1 (fr) | Procédé de réalisation de composants passifs et actifs sur un même substrat isolant | |
JP7275172B2 (ja) | 優れた性能、安定性および製造性を有する無線周波数シリコン・オン・インシュレータ・ウエハ・プラットフォーム | |
EP3127142A1 (fr) | Procédé de fabrication d'une plaque de semi-conducteur adaptée pour la fabrication d'un substrat soi, et plaque de substrat soi ainsi obtenue | |
EP2332171B1 (fr) | Procede de fabrication d'une structure semi-conductrice plan de masse enterre | |
EP1332517B1 (fr) | Procede de revelation de defauts cristallins et/ou de champs de contraintes a l'interface d'adhesion moleculaire de deux materiaux solides | |
EP1547145A2 (fr) | PROCEDE DE FABRICATION D' UN SUBSTRAT COMPOSITE DU TYPE SiCOI COMPRENANT UNE ETAPE D' EPITAXIE | |
JPWO2020014007A5 (fr) | ||
FR3068506A1 (fr) | Procede pour preparer un support pour une structure semi-conductrice | |
JPWO2020014441A5 (fr) | ||
FR3118828A1 (fr) | Procédé de collage direct de substrats | |
EP0901158B1 (fr) | Circuit intégré de puissance, procédé de fabrication d'un tel circuit et convertisseur incluant un tel circuit | |
WO2024088942A1 (fr) | Procédé de fabrication d'un empilement semiconducteur hautement résistif et empilement associé | |
EP4235749A1 (fr) | Procédé de collage par activation de surface par bombardement d'ions ou d'atomes d'une première surface d'un premier substrat à une deuxième surface d'un deuxième substrat | |
JPH09328333A (ja) | 絶縁体上半導体構造およびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 20050211 |
|
AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES Owner name: COMMISSARIAT A L'ENERGIE ATOMIQUE |
|
17Q | First examination report despatched |
Effective date: 20090709 |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES Owner name: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: SOITEC Owner name: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
18D | Application deemed to be withdrawn |
Effective date: 20120403 |