Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/12—Mountings, e.g. non-detachable insulating substrates
  • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/12—Mountings, e.g. non-detachable insulating substrates
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
  • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
  • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
  • H05K3/341—Surface mounted components
  • H05K3/3431—Leadless components
  • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/11—Printed elements for providing electric connections to or between printed circuits
  • H05K1/119—Details of rigid insulating substrates therefor, e.g. three-dimensional details
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09009—Substrate related
  • H05K2201/09036—Recesses or grooves in insulating substrate
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09009—Substrate related
  • H05K2201/09045—Locally raised area or protrusion of insulating substrate
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
  • H05K2203/04—Soldering or other types of metallurgic bonding
  • H05K2203/046—Means for drawing solder, e.g. for removing excess solder from pads
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
  • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
  • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

• the invention relates to an intermediate carrier for electronic components with a carrier body made of plastic, on the surface of which contact bumps are integrally formed, the surface of which is at least partially provided with a solderable metal layer, which is conductively connected to at least one conductor track of the carrier body.
• the invention relates to a method for solder contacting such an intermediate carrier.
• An intermediate carrier of this type is known, for example, from EP 0 971 405 A2.
• These intermediate carriers which are also referred to as PSGA (polymer stud grid array), are used, for example, for the connection contacting of semiconductor chips on printed circuit boards.
• PSGA polymer stud grid array
• the intermediate carriers themselves are usually produced by injection molding, as described in EP 0 971 405 A2, with the contact bumps being molded on, but these contact bumps can also be formed by other methods, for example by hot stamping foils, all types of plastics, Thermoplastics, thermosets, also epoxy resins, can be used.
• the contact bumps on the intermediate carriers can be used both for contacting a semiconductor chip or another component on the intermediate carrier and for contacting the intermediate carrier on a printed circuit board.
• soldered connections for ever higher packing densities of components is limited by the accuracy with which the solder paste at the individual contact points of a printed circuit board or of a component can be applied.
• solder mask In order to avoid short circuits between the soldering points, it has hitherto been necessary to separate these connection points from one another on the connecting substrate by means of solder mask.
• this solder resist can only be applied with a limited accuracy, so that both the miniaturization and the production yield are limited in this way.
• the geometry of the circuits, the solder mask and the solder paste must be very precisely aligned with each other, but the tolerances add up, which are inevitable for each of these three elements.
• the application of the solder paste at precisely defined locations is very difficult to handle.
• a short circuit occurs when contacting a component, this error can no longer be remedied, since the component can no longer be separated from the connecting substrate.
• the aim of the invention is therefore to provide an intermediate carrier of the type mentioned at the outset and a method for solder contacting of such an intermediate carrier, the requirements for the solder application being less high than in previous methods and nevertheless a higher security of the soldered connections against short circuits being achieved.
• this goal is achieved with an intermediate carrier of the type mentioned at the outset in that the contact bumps have an easily wettable liquid solder conductor which extends from their tip to their foot and in that in the foot region of the contact bumps in each case solder receiving areas are formed with a suction effect, which each have a wetting barrier with respect to the adjacent contact bump.
• solder no longer has to be applied in a punctiform manner only to the contact surfaces or contact elements with a high degree of accuracy, but rather that it can be distributed over all the contact points in a much simpler manner, since reflow soldering anyway the areas between the contact points are vacuumed empty.
• the amount of solder applied to the surface must be coordinated with the capacity of the solder receiving areas at the contact bumps.
• the intermediate carrier according to the invention With the intermediate carrier according to the invention, smaller distances between the contact points can thus also be achieved, so that the overall packing density can be increased. Another advantage is that the targeted extraction of the solder also results in an additional self-alignment of the contact bumps with respect to a circuit carrier, so that the accuracy of the arrangement of components is also increased in this way, which is a great advantage, for example, for contacting optical components represents.
• the solder receiving areas to be provided on the contact bumps according to the invention can be formed as depressions in the surface of the carrier body in the foot area of the contact bumps. They can enclose the foot area of the bump more or less far in the manner of a completely or partially closed annular groove. However, it is also possible that the each extend asymmetrically away from the foot area of a contact bump. If, for example, the solder pick-up areas of adjacent contact bumps are arranged in the opposite direction, the distances between the contact bumps can be particularly small. The invention is particularly advantageous for flip-chip assembly of semiconductor components.
• the solder receiving areas can also be formed as capillary channels in the bumps themselves.
• slit-like or cross-shaped incisions in the longitudinal direction of the contact bumps can be formed as capillary channels, which either already serve as solder receiving areas themselves or, via their capillary action, lead the excess solder to an additional depression arranged in the surface of the carrier body.
• the tracks that conduct the solder on the contact bumps can be formed by metallization with corresponding materials that are readily wettable.
• the wetting or capillary effect can, however, be enhanced by grooves or channels provided on the surface or in the interior of the contact bumps, as already indicated above. It is also conceivable, for example, for the contact bumps to be corrugated in whole or in part on their outer circumference.
• a method according to the invention for solder contacting such an intermediate carrier on a circuit carrier with flat contact elements arranged on its upper side has the following steps:
• the intermediate carrier is placed on the circuit carrier in such a way that its contact bumps each rest on the solder layer via associated contact elements and -
• the solder layer is liquefied by heating, whereby a solder connection is formed between a contact element and a contact stool, and excess solder is sucked out of the areas between the contact elements via the contact stool into the solder receiving areas.
• FIG. 1 shows the arrangement of an intermediate carrier on a semiconductor component prepared for solder contact
• FIG. 2 shows the arrangement of FIG. 1 during the soldering
• FIG. 3 shows the intermediate carrier and the component of FIG. 1 after the soldering process
• FIG. 4 shows a section IV-IV from FIG. 1,
• FIG. 5 shows a sectional view corresponding to FIG. 4 of a modified embodiment of an intermediate carrier
• FIGS. 6 to 8 shows an intermediate carrier modified compared to FIG. 1 in the stages corresponding to FIGS. 1 to 3
• FIG. 9 shows a section IX-IX from FIG. 8 and FIG. 10 shows a perspective sectional view of an intermediate carrier according to FIG. 1.
• the intermediate carrier 1 shown in FIGS. 1 to 3 consists of plastic material and has on its underside one-piece molded contact stool 2 for contacting flat contact elements 3 of a circuit carrier, in the present example a semiconductor chip 4. It is therefore the so-called Flip-chip assembly of an inaccurate semiconductor.
• the intermediate carrier 1 shown only in a detail is contacted after the connection to the semiconductor 4, for example on another circuit carrier, such as a printed circuit board.
• This contacting of the intermediate carrier can take place with connection elements (not shown), for example conventional connection elements or also further contact stools, these additional contact blocks can be provided in a manner not shown ker either on the same side next to the Halbleiterele ⁇ element 4 or on the opposite side of the Eisenträ ⁇ gers.
• the more precise design of the intermediate carrier 1 is shown schematically in a perspective sectional illustration in FIG. 10.
• the contact bumps 2 are each surrounded by annular depressions 11, which develop a suction effect for liquid solder when it reaches the foot 2c of the contact bumps via the tips 2a and the easily wettable peripheral surfaces 2b of the contact bumps due to their surface tension.
• the contact bumps are entirely or partially provided with a metallic coating 12 which extends over the circumferential surface into the respective depression 11 and over the outer edge of the depression to a conductor track 13 on the surface of the intermediate carrier 1. In this way, the bumps are electrically connected to the desired conductor tracks of the intermediate carrier.
• the outer edge of the depression 11 acts in each case as a wetting barrier or capillary barrier, so that the solder sucked into the depression does not penetrate beyond the edge and, above all, cannot short-circuit the insulating gap 14 between the individual contact bumps.
• the conductor tracks 13 shown in FIG. 10 are only indicated for the sake of example.
• the electrical connections can of course be designed in any way.
• conductive connections can also lead via edge regions of the intermediate carrier or via bores to the opposite surface and to conductor tracks or components arranged there.
• FIG. 4 shows a top view of two adjacent contact bumps with a grid spacing d1, which are each surrounded by annular depressions 11.
• FIG. 5 shows a modification of this, wherein instead of the annular depressions, depressions widened on one side in opposite directions 16 are provided. In this way the bumps
• FIGS. 1 to 3 The contacting process can be followed using FIGS. 1 to 3.
• the circuit carrier 4 is covered in the area of the connection elements 3 with a continuous solder layer 5 which extends continuously over all contact elements 3.
• the intermediate carrier 1 is then put on and positioned by means of straightening bumps 6, positioning pins 7 engaging in positioning holes 8 of the circuit carrier 4.
• positioning pins and positioning holes could also be reversed on the opposite part.
• the solder 5 is liquefied, so that the tips 2a of the bumps 2 are immersed in the liquid solder layer.
• the surplus solder between the individual contact elements 3 is sucked off towards the feet 2c of the respective contact bumps by the surface conduction and wetting of the contact bumps and deposited in the depressions 11.
• FIGS. 6 to 9 The same process is described in FIGS. 6 to 9 with the aid of a modified intermediate carrier 21.
• This intermediate carrier 21 has contact bumps 22 which each have cross-shaped slots 23 running in their length. Otherwise, the intermediate carrier 21 is designed in exactly the same way as the intermediate carrier 1. It is also placed on a circuit carrier 4 and soldered to it in the same way as this. The process takes place in the same way as already described with reference to Figures 1 to 3. The only difference is that the excess solder is not sucked over the outer surfaces of the bumps into additional recesses in the intermediate carrier, but that this excess solder is sucked directly into the cross-shaped slots 23, which serve as solder receiving areas. Of course, additional depressions could also be provided in the intermediate carrier 21 in this case.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Power Engineering (AREA)
• Manufacturing & Machinery (AREA)
• Wire Bonding (AREA)
• Electric Connection Of Electric Components To Printed Circuits (AREA)
• Combinations Of Printed Boards (AREA)

Applications Claiming Priority (3)

Publications (1)

Family

ID=7699039

Family Applications (1)

Country Status (8)

Families Citing this family (7)

Family Cites Families (10)

• 2001
  • 2001-09-14 DE DE10145348A patent/DE10145348C1/de not_active Expired - Fee Related
• 2002
  • 2002-09-09 TW TW091120465A patent/TW563238B/zh not_active IP Right Cessation
  • 2002-09-13 EP EP02774350A patent/EP1425792A2/de not_active Withdrawn
  • 2002-09-13 US US10/489,592 patent/US20040251527A1/en not_active Abandoned
  • 2002-09-13 WO PCT/DE2002/003429 patent/WO2003025974A2/de not_active Application Discontinuation
  • 2002-09-13 JP JP2003529499A patent/JP2005503036A/ja active Pending
  • 2002-09-13 KR KR10-2004-7003555A patent/KR20040036938A/ko not_active Application Discontinuation
  • 2002-09-13 CN CNA028179595A patent/CN1555572A/zh active Pending

Non-Patent Citations (1)

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