EP1280127A2 - Dispositif d'affichage à matrice active - Google Patents

Dispositif d'affichage à matrice active Download PDF

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Publication number
EP1280127A2
EP1280127A2 EP02017077A EP02017077A EP1280127A2 EP 1280127 A2 EP1280127 A2 EP 1280127A2 EP 02017077 A EP02017077 A EP 02017077A EP 02017077 A EP02017077 A EP 02017077A EP 1280127 A2 EP1280127 A2 EP 1280127A2
Authority
EP
European Patent Office
Prior art keywords
switching
signal
image mode
display device
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02017077A
Other languages
German (de)
English (en)
Other versions
EP1280127A3 (fr
Inventor
Makoto Kitagawa
Mitsugu Kobayashi
Makoto Fujioka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Tottori Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2001228044A external-priority patent/JP4306980B2/ja
Priority claimed from JP2001228045A external-priority patent/JP4259775B2/ja
Priority claimed from JP2001228046A external-priority patent/JP4259776B2/ja
Application filed by Tokyo Sanyo Electric Co Ltd, Tottori Sanyo Electric Co Ltd, Sanyo Electric Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Publication of EP1280127A2 publication Critical patent/EP1280127A2/fr
Publication of EP1280127A3 publication Critical patent/EP1280127A3/fr
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/10—Special adaptations of display systems for operation with variable images
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/18—Use of a frame buffer in a display terminal, inclusive of the display panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/12—Synchronisation between the display unit and other units, e.g. other display units, video-disc players
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory

Definitions

  • This invention relates to a display device, which makes a selection between two display modes; a moving image mode where an image signal consecutively inputted is consecutively displayed and a still image mode where an image signal stored in a frame memory is displayed.
  • liquid crystal display (LCD) device and electric luminescence (EL) display device have been used widely as they have relatively small power consumption.
  • Fig. 4 shows a circuit diagram of an active matrix LCD as an example of a conventional display device.
  • a controlling circuit 200 is connected to a LCD panel 100.
  • the LCD panel 100 comprises a first substrate with a plurality of pixel electrodes and a second substrate with a single common electrode 10 facing to a plurality of the pixel electrodes with a liquid crystal sandwiched between the first and second substrates.
  • a plurality of the pixel electrodes 1 and a pixel TFT 2 for switching having a thin film transistor (TFT) for each of the pixel electrodes are placed in a matrix configuration.
  • a gate line 3 is placed in the row direction and a data line 4 is placed in the column direction of the matrix of the pixel electrodes 1.
  • the gate line 3 is connected to the gate of the each pixel TFT 2 and the data line 4 is connected to the drain of the each pixel TFT 2.
  • the gate line 3 is connected to a gate line shift resistor 5 placed near the display area.
  • the data line 4 is connected to a data bus line 7 through a data line selection TFT 6, the gate of which is connected to the output terminal of a data line shift resistor 8.
  • the data line selection TFT 6 and the data line shift resistor 8 configure a data line driver for consecutively selecting the data line 4 and supplying the data signal.
  • a storage capacitor 9 for storing a pixel voltage is placed for each of the pixel along with a liquid crystal capacitor placed in parallel.
  • the control circuit 200 has a data processing unit 21, a CPU interface 22, a timing controller 23, and a digital-analog converter (DAC) 24.
  • the data processing unit 21 produces a signal suitable for the LCD panel by performing the sampling with an adequate timing, converting the signal into digital signal, adjusting the brightness and contrast, and applying the gamma correction.
  • the CPU interface 22 receives a command of a CPU, not shown in the figure, which controls a device with a LCD such as PDA and cellular phone, and sends the controlling signal out to each part of the device based on the command received.
  • the timing controller 23 outputs various kinds of timing signal to the LCD panel 100 based on a vertical start signal and a horizontal synchronous signal extracted from the image signal.
  • the DAC 24 converts a RGB digital data outputted from the data processing unit 21 into the voltage suitable for the pixel voltage of the LCD panel 100 and outputs the converted voltage.
  • FIGs. 5 and 6 are the timing charts showing several timing signals.
  • a vertical synchronous signal Vsync is a clock outputting a "high level" every time when a vertical synchronous period begins for indicating the start of one frame period.
  • a vertical start signal STV is inputted to the gate line shift resistor 5.
  • the gate line shift resistor 5 is a shift resistor, which starts the operation in response to the vertical start signal STV.
  • a gate line clock CKV is inputted to the gate shift resistor 5 and the shift resistor for each of the gate line clock CKVs consecutively supplies the gate signal to the gate line 3.
  • Half a cycle of the gate line clock CKV is equal to the horizontal synchronous period.
  • the horizontal start signal STH is inputted to the data line shift resistor 8 of the date line driver.
  • the data line shift resistor 8 starts the operation in response to the horizontal start signal STH.
  • a data line clock CKH is inputted to the data shift resistor 8 and the out put of the data shift resistor 8 changes for each of the data line clock CKHs, consecutively supplying the data line selection signal to the data line selection TFT 6.
  • the data line selection TFT 6 provided with the data line selection signal turns on and the data signal DATA is supplied to the pixel electrode 1 from the data bus line through the data line 4 and the pixel TFT 2. As shown in the figure, there is a plurality of the data bus lines 7.
  • the pixel voltage is simultaneously applied to a plurality of the pixel electrodes 1.
  • the gate line clock CKV is inputted again for selecting the next gate line 3.
  • display, of one screen image is completed. Every time data for one row, or, for example, the data for 176 pixels is written, there is a horizontal blanking period, where no data is inputted for a certain period of time.
  • a display device with a frame memory capable of storing image data for one screen display is widely used and the display is made by using the data stored in the frame memory.
  • Fig. 7 shows the circuit diagram of the display device with a frame memory. The same components as those in Fig. 4 have the same reference numerals as in Fig. 4 and the explanation about these configurations will be omitted.
  • the frame memory 25 is a SRAM, which stores the digital image data of the entire pixels of the liquid crystal panel 100 inputted through the CPU interface 22. The image data stored in the frame memory 25 is converted into the pixel voltage by the DAC 24 and then supplied to each of the pixel electrodes.
  • An oscillator 26 produces a base clock and supplies it to the timing controller 23.
  • the timing controller 23 produces the data line clock CKH by multiplying the frequency of the basic clock.
  • a counter in the timing controller counts the base clock for outputting one pulse for a predetermined number of data line clocks, producing the horizontal start signal STH and the gate line clock CKV. Also, another counter counts the base clock, producing the vertical start signal STV.
  • the power consumption is relatively small since there is no need to input the display data from outside.
  • the device does not have an enough imaging speed for displaying a moving image.
  • the object of this invention is directed to a display device with relatively small power consumption capable of displaying a moving image.
  • the active matrix display device of this invention has a plurality of gate lines, a plurality of data lines disposed in the direction perpendicular to the gate line, a switching element placed at the crossing of the gate line and the data line, and a plurality of pixel electrodes connected to each of the switching elements.
  • An image signal is supplied to the entire pixel electrodes from the data line for each frame period.
  • the active matrix display device displays an image based on the pixel voltage between the pixel electrode and the common electrode.
  • the active matrix display device has a moving image mode, where a moving image is displayed based on the output of the data processing unit which performs a certain processing on consecutively inputted image signal and a still image mode, where a still image is displayed based on the output of the memory which stores the image signal of a plurality of the pixels.
  • the switching timing from the still image mode to the moving image mode differs from the switching timing from the moving image mode to the still image mode.
  • the switching timing from the still image mode to the moving image mode when a first switching signal, which switches from the still image mode to the moving image mode, is received during one frame period, the still image mode continues until the end of the frame period and the moving image mode begins at the next frame period.
  • the switching timing from the moving image mode to the still image mode when a second switching signal, which switches from the moving image mode to the still image mode, is received during one frame period, the image signal is read out from the address of the memory corresponding to the pixel supplying the pixel voltage at this moment and the switching to the still image mode is immediately performed.
  • Fig. 1 shows a display device of an embodiment of this invention.
  • the same components as those in the device of Figs 4 or 7 are denoted by the same reference numerals and the explanation about these components will be omitted.
  • a liquid crystal panel 100 of this embodiment is the same as that of the prior arts.
  • a control circuit 200 of this embodiment however, a data processing unit 21 and a frame memory 25 are placed.
  • the data processing unit 21 produces and outputs a signal suitable for the LCD panel 100 by adjusting the brightness and contrast and applying the gamma correction to the consecutively inputted image signal. And a moving image is displayed based on this signal.
  • a still image mode a still image is displayed based on the image signal stored in the frame memory.
  • the switching between the moving image mode with a fast imaging speed for displaying a moving image and the still image mode with a slow imaging speed and relatively small power consumption for displaying the still image is made so that the power consumption of the display device can be kept low.
  • the still image mode is a default use mode. In this case, when a moving image signal is received, or when a user performs a key operation, a CPU, which controls a device with the display device such as cellular phone and PDA, outputs a signal for making the switch from the still image mode to the moving image mode.
  • the CPU outputs a signal for making the switch from the moving image mode to the still image mode when a certain amount of time elapses after a completion of the moving mode, or after the user finishes the key operation.
  • the switching signal is outputted to a CPU interface 22 from the CPU through a timing controller 23, which then performs the switching of the selector 27.
  • the output from the data processing unit 21 and the output from the frame memory 25 is selected, making the switch between the moving image mode and the still image mode.
  • the display operation is performed based on the timing signals shown in Figs. 5 and 6 in the same manner as the conventional devices.
  • various kinds of timing signals are external timing signals produced by using a clock extracted from the image signal inputted from outside.
  • an internal timing signal produced based on a base clock outputted from an oscillator 26 connected to the timing controller 23 is used.
  • these timing signals are basically the same signal, the external timing signal extracted from the external signal and the internal timing signal outputted from the oscillator 26 provided inside the device are differentiated and referred to differently in this specification.
  • the signal extracted from the external signal will be indicated as the external vertical synchronous signal and the signal based on the output from the oscillator will be referred to as the internal vertical synchronous signal.
  • the display device of this embodiment can be basically operable in the same manner as the device of Figs. 4 and 7. However, the manner for selecting the operation modes is different. Since the external timing signal and the internal timing signal are produced independently from each other, the external vertical synchronous signal and the internal vertical synchronous signal are not totally synchronized. Also, the switching signal for switching between the modes is inputted from the CPU of the device through the CPU interface. And the command for this operation is totally independent from both of the timing signals.
  • a first embodiment relating to the mode switching will be explained.
  • the switching from the moving image mode to the still image mode will be explained.
  • a horizontal counter and a vertical counter of the timing controller are forcibly reset and the display scanning begins from the pixel located at the first row of the first column in the newly selected mode. That is, when the mode-switching signal is inputted, the timing controller 23 outputs a vertical start signal STV and a horizontal start signal STH, starting the operation of a shift resistor.
  • the first embodiment has the following problem. Since the mode-switching signal is not synchronized with the vertical synchronous signal, it is usually inputted during the frame period. However, before this frame period begins, a gate line shift resistor 5 and a data line shift resistor 8 have already started the operation. Suppose the pixel in the n-row of the m-column is provided with the pixel voltage. When the mode-switching signal is inputted under this condition, the counter is forcibly reset, starting the supply of the pixel voltage from the pixel located at the first row of the first column. However, the shift resistor is to select both the pixel at the first row of the first column and the pixel at the n-th row of the m+1th row. As a result, at the frame with the mode-switching is done, the second row and the n+1th row, the third row and the n+2th row are both selected simultaneously, displaying the same images at the upper portion and the lower portion of the screen.
  • Fig. 2 is the timing chart for making ae switch from the moving image mode to the still image mode.
  • the operation is based upon the external timing signal inputted from outside.
  • the external timing signal is inputted as the timing signal itself.
  • the image signal is an analog signal such as a NTSC and a PAL
  • the external timing signal is extracted from the image signal. In some cases, the signal is extracted inside of the control circuit 200, it will be, however, referred to as the external timing signal here.
  • the switching signal for making the switch from the moving image mode to the still image mode (it will be indicated as the moving to still image switching signal) is received.
  • the vertical counter inside of the timing controller is reset by the vertical start signal STV for counting the gate line clock CKV and the horizontal counter is reset by the horizontal start signal STH for counting the data line clock CKH, resulting in the counting value of (n, m) of these counters. Therefore, this counting value is showing the coordinates of the pixel provided with the pixel voltage at this moment. If the image signal is read out from the address of the frame memory 25 corresponding to this counting value, the image signal corresponding to the next pixel electrode can be read out from the frame memory 25.
  • the internal timing signal can be outputted without resetting the counting value of the vertical counter or the horizontal counter. Then the selector 27 is switched for selecting the frame memory 25, and the switching to the still image mode is immediately made. The image signal is supplied to the next pixel electrode from the corresponding address of the frame memory 25. In this way, two gate lines are not selected at the same time. Thus, there is no messy display upon the switching between the modes.
  • the data clock (the base clock) of the external timing signal and the base clock outputted from the oscillator 26 are not synchronized, it does not cause any problem because the counter inside of the timing controller is not reset.
  • the operation stops just a short period of time, about one cycle of the base clock upon the switching between the modes.
  • the timing controller 23 is set up not to output the clock shorter than one base clock for preventing the false operation. Therefore, upon the switching between the modes, the operation stops for more than one cycle of the base clock, about the ⁇ t period shown in the figure,.
  • Fig. 3 is a timing chart of the switching from the still image mode to the moving image mode.
  • the switching signal for making the switch from the still image mode to the moving image mode (it will be indicated as the still to moving image switching signal)
  • the switching of the operation is not particularly performed.
  • the operation by the internal timing signal based on the output of the oscillator 26, that is, the still image mode continues till the end of the frame memory.
  • the next internal vertical synchronous signal is not outputted.
  • the external vertical synchronous signal is inputted. Therefore, at the beginning of the frame period after the external vertical synchronous signal is inputted, the mode is switched to the moving image mode based on the external timing signal. In this way of switching, two gate lines are not selected at the same time. Thus, there is no messy display upon the switching between the modes.
  • the external timing signal should be outputted several base clocks prior to the input of the external vertical synchronous signal.
  • the shift resistors 5, 8 do not start the operation because the vertical start signal STV or the horizontal start signal STH are not supplied. It is also possible to switch to the external timing signal immediately after the frame period of the still image mode.
  • the image signal and the timing signal are supplied within the control circuit 200. But in the moving image mode, the image signal is supplied from outside and the still image is displayed in the synchronization with the external signal. Therefore, in the second embodiment, the switching timing from the still image mode to the moving image mode and the switching timing from the moving image mode to the still image mode are different from each other. Each switching is performed through the most preferable procedure, improving the display quality.
  • the liquid crystal display device is explained as an example of the active matrix display device.
  • this invention is not limited to these embodiments. It is also applicable to EL display device, LED display device and vacuum luminescence display device.
  • the display device of this invention makes the display by making the switch between two modes; the moving image mode with the rapid imaging speed where the image is displayed based on the output from the data processing unit 21, and the still image mode with small power consumption where the image is displayed based on the output of the memory 25. Therefore, the display device with the small power consumption and yet with the high quality display is achieved.
  • the switching timing from the still image mode to the moving image mode and the switching timing from the moving image mode to the still image mode are different from each other. Each switching is performed through the most preferable procedure, improving the display quality.
  • the configuration of the display panel 100 can be exactly the same as that of the conventional devices. Only the configuration of the control circuit 200 should be modified, suppressing the manufacturing cost.
  • the device of this invention can be embodied with a relatively simple configuration.
  • the device of this invention can be embodied with a relatively simple configuration.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
EP02017077A 2001-07-27 2002-07-29 Dispositif d'affichage à matrice active Withdrawn EP1280127A3 (fr)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP2001228044A JP4306980B2 (ja) 2001-07-27 2001-07-27 アクティブマトリクス型表示装置及びその制御装置
JP2001228045A JP4259775B2 (ja) 2001-07-27 2001-07-27 アクティブマトリクス型表示装置及びその制御装置
JP2001228045 2001-07-27
JP2001228046A JP4259776B2 (ja) 2001-07-27 2001-07-27 アクティブマトリクス型表示装置及びその制御装置
JP2001228046 2001-07-27
JP2001228044 2001-07-27

Publications (2)

Publication Number Publication Date
EP1280127A2 true EP1280127A2 (fr) 2003-01-29
EP1280127A3 EP1280127A3 (fr) 2007-01-10

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP02017077A Withdrawn EP1280127A3 (fr) 2001-07-27 2002-07-29 Dispositif d'affichage à matrice active

Country Status (5)

Country Link
US (1) US7030871B2 (fr)
EP (1) EP1280127A3 (fr)
KR (1) KR100499845B1 (fr)
CN (1) CN1243334C (fr)
TW (1) TWI237142B (fr)

Cited By (4)

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WO2005052908A1 (fr) * 2003-11-27 2005-06-09 Robert Bosch Gmbh Procede de modification d'une image de repos pour un dispositif d'affichage
EP1557751A2 (fr) * 2004-01-26 2005-07-27 Nec Corporation Dispositif terminal mobile et sa methode d'affichage d'information
US8629069B2 (en) 2005-09-29 2014-01-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US9672792B2 (en) 2011-08-08 2017-06-06 Samsung Display Co., Ltd. Display device and driving method thereof

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JP2004004796A (ja) * 2002-04-25 2004-01-08 Matsushita Electric Ind Co Ltd 画像処理装置
JP2004045520A (ja) * 2002-07-09 2004-02-12 Toshiba Corp 平面表示装置の駆動方法
EP1617403A4 (fr) * 2003-04-23 2009-09-09 Vodafone Plc Procede et dispositif de traitement d'affichage
KR100535966B1 (ko) * 2003-08-08 2005-12-09 엘지전자 주식회사 3차원 엔진을 탑재한 이동통신 단말기의 소비전력 절감 방법
US7274361B2 (en) * 2003-09-26 2007-09-25 Mstar Semiconductor, Inc. Display control device with multipurpose output driver
US7586474B2 (en) * 2003-12-11 2009-09-08 Lg Display Co., Ltd. Liquid crystal display and method of driving the same
KR100692854B1 (ko) * 2004-02-20 2007-03-13 엘지전자 주식회사 일렉트로-루미네센스 표시 패널의 구동 방법 및 장치
JP4554961B2 (ja) * 2004-03-05 2010-09-29 Ｎｅｃ液晶テクノロジー株式会社 液晶表示装置およびその駆動方法
KR100604866B1 (ko) * 2004-06-08 2006-07-26 삼성전자주식회사 액정 표시 장치 구동을 위한 감마 구동 방식의 소스드라이버 및 소스 라인 구동 방법
JP2006106689A (ja) * 2004-09-13 2006-04-20 Seiko Epson Corp 液晶パネルの表示方法、液晶表示装置及び電子機器
JP2006203333A (ja) * 2005-01-18 2006-08-03 Canon Inc 双方向リモートコントロールユニット
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CN1400577A (zh) 2003-03-05
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US20030030607A1 (en) 2003-02-13
KR20030010555A (ko) 2003-02-05

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