EP1153424A1 - Structure electrode de condensateur - Google Patents

Structure electrode de condensateur

Info

Publication number
EP1153424A1
EP1153424A1 EP99967896A EP99967896A EP1153424A1 EP 1153424 A1 EP1153424 A1 EP 1153424A1 EP 99967896 A EP99967896 A EP 99967896A EP 99967896 A EP99967896 A EP 99967896A EP 1153424 A1 EP1153424 A1 EP 1153424A1
Authority
EP
European Patent Office
Prior art keywords
layer
oxygen
silicide
iridium
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99967896A
Other languages
German (de)
English (en)
Inventor
Nicolas Nagel
Robert Primig
Igor Kasko
Rainer Bruchhaus
Hermann Wendt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE1998160080 external-priority patent/DE19860080B4/de
Priority claimed from DE1999109295 external-priority patent/DE19909295A1/de
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1153424A1 publication Critical patent/EP1153424A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28568—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising transition metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material

Definitions

  • the invention is in the field of semiconductor technology and relates to a microelectronic structure with a base substrate, a silicon-containing layer and an oxygen barrier layer.
  • the barrier has to meet the following requirements. On the one hand, it must prevent silicon diffusion from the contact hole to the platinum electrode and, on the other hand, it must prevent oxygen diffusion from the platinum to the contact hole in order to rule out the electrically insulating oxidation of silicon. In addition, the barrier must remain stable even under the process conditions.
  • a possible construction of an initially mentioned microelectronic structure in the form of an electrode barrier system is described, for example, in US Pat. No. 5,581,439.
  • a titanium nitride layer which hinders silicon diffusion is buried in a silicon nitride layer, which at least laterally protects the titanium nitride layer from oxidation.
  • a palladium body with a platinum coating sits on the silicon nitride collar, which together form the electrode.
  • the titanium nitride layer should at least be protected from oxidation by the palladium.
  • Healing step in an oxygen-containing atmosphere can be prevented by complete oxidation of the iridium. This healing step is unfavorable in an oxygen-containing atmosphere, particularly with regard to the
  • Deep oxidation of the iridium can only be controlled with difficulty, so that if the layer of the iridium layer is uneven, the polysilicon can also be oxidized, as a result of which the electrical contact between the polysilicon and the iridium is interrupted.
  • barrier layers With all of the previously known barrier layers, however, there is a risk that they will no longer be sufficiently stable at the required high process temperatures, in particular when a temperature step is required to condition the high- ⁇ materials or the ferroelectric materials.
  • This object is achieved according to the invention in the case of a microelectronic structure of the type mentioned at the outset in that between the silicon-containing layer and the oxygen barrier layer there is an oxygen-containing iridium layer which can be produced by means of an atomization process (sputtering) in an oxygen-containing layer, the volume fraction of Oxygen in the atmosphere is between 2.5% and 15%.
  • the oxygen-containing iridium layer contained in the microelectronic structure prevents silicon diffusion from the silicon-containing layer into the oxygen barrier layer and into further layers which may be arranged above it.
  • the oxygen-containing iridium layer has a certain proportion of oxygen which prevents the formation of iridium silicide and thus pus diffusion of silicon prevented.
  • the interface between the oxygen-containing iridium layer and the silicon-containing layer remains at temperatures up to at least 800 ° C. Test-free of iridium silicide. This can be demonstrated, for example, by resistance measurements on the oxygen-containing iridium layer.
  • iridium silicide is expressed, for example, in a very low specific resistance of the oxygen-containing iridium layer of less than 100 ⁇ Ohm * cm, preferably even less than 30 ⁇ Ohm * cm.
  • iridium silicide which has a very high specific resistance of about 6 ohm * cm, the specific resistance of the structure formed from the silicon-containing layer and the oxygen-containing iridium layer would be significantly above 100 ⁇ Ohm * cm.
  • the low electrical resistance of the microelectronic structure is of great advantage in particular in the case of highly integrated semiconductor components, in particular in semiconductor memories with structure sizes of 0.25 ⁇ m and below.
  • the oxygen-containing iridium layer largely prevents contact between the silicon-containing layer and the oxygen barrier layer in order to prevent a possible reduction of the oxygen barrier layer by the silicon-containing layer and the associated oxidation of the silicon-containing layer.
  • An oxygen-containing iridium layer with the properties described above can be used, for example, by means of a
  • Manufacture atomization processes in an oxygen-containing atmosphere with a low oxygen content, the volume fraction of oxygen in the atmosphere being between 2.5% and 15%. Due to the limited volume fraction of oxygen in the atmosphere, oxygen is only built into the iridium layer to a certain degree, so that one can also speak of an anoxidized iridium layer.
  • the volume fraction of oxygen in the atmosphere is preferably about 5%. It has been shown in tests, withstand that the% at a volume fraction of about 2.5 oxygen produced sauerstoffhal ⁇ term iridium layers of a siliconization still largely, while oxygen-containing iridium layers were prepared in an atmosphere containing less than 2.5% oxygen already clearly tend to silicide. On the other hand, an oxygen-containing iridium layer, which was deposited at an oxygen volume concentration of at most 15%, does not yet lead to a disruptive oxidation of the silicon-containing layer located under the oxygen-containing iridium layer.
  • the oxygen-containing iridium layer In order to improve the adhesiveness of the oxygen-containing iridium layer, it is favorable to deposit the oxygen-containing iridium layer at a temperature of at least 250 ° C. This in particular improves the adhesive strength between the oxygen-containing iridium layer and silicon-containing insulation layers, which consist, for example, of silicon nitride and silicon oxide. Since the base substrate itself can consist of silicon oxide or silicon nitride, good deposition of the oxygen-containing iridium layer on the base substrate is also achieved by the deposition of the oxygen-containing iridium layer at elevated temperatures. In principle, the deposition temperature should be chosen so high that sufficient adhesion to the base substrate is guaranteed, whereby an adhesive strength of at least 100 kg / cm 2 can be achieved.
  • Another advantage of depositing the oxygen-containing iridium layer at a temperature of at least 250 ° C is that a further conditioning step to improve the adhesion of the oxygen-containing iridium layer is not necessary. If the separation temperature is not chosen too high, For example, between 250 ° C and 400 ° C, structures that have already been created are hardly subjected to thermal stress.
  • the oxygen barrier advantageously consists of a conductive metal oxide, with iridium dioxide and ruthenium dioxide in particular having proven themselves as metal oxide. Using these metal oxides also ensures good adhesion of the oxygen barrier layer to the oxygen-containing iridium layer.
  • the silicon-containing layer which is usually located below the oxygen-containing iridium layer, preferably consists of polysilicon, a metal silicide or a layer stack which comprises at least one polysilicon layer and a metal silicide layer located between the polysilicon layer and the oxygen-containing iridium layer.
  • the metal silicide preferably consists of at least one silicide from the group yttrium silicide, titanium silicide, zirconium silicide, hafnium silicide, vanadium silicide, niobsilicide, tantalum silicide, chromium silicide, molybdenum silicide, tungsten silicide, cobalamin silicide, palladium silicide, palladium silicide, palladium silicide, palladium silicide, palladium silicide, palladium silicide, palladium silicide, palladium silicide, palladium silicide, palladium silicide, palladium silicide, palladium silicide, palladium silicide, palladium silicide, palladium silicide, palladium silicide, palladium silicide, palladium silicide, palladium silicide, palladium silicide, palladium silicide, palladium si
  • the silicon-containing layer can This structure is present, for example, in the form of a contact hole filled with polysilicon, which is optionally delimited by a metal silicide layer towards the oxygen-containing iridium layer.
  • the oxygen-containing iridium layer preferably has a thickness of approximately 100 ⁇ m, advantageously even of approximately 20 to 50 nm.
  • the aim is to make the oxygen-containing iridium layer as thin and space-saving as possible.
  • the barrier layers contained in the microelectronic structure are advantageously covered by a metal-containing electrode layer.
  • the oxygen barrier layer should be covered as completely as possible by this layer.
  • the metal-containing electrode layer preferably consists of a metal (for example platinum, ruthenium, iridium, palladium, rhodium, rhenium, osmium) or a conductive metal oxide (MO x , for example ruthenium oxide, osmium oxide, rhodium oxide, iridium oxide, rhenium oxide or conductive perovskite, for example SrRu0 3 or (La, Sr) Co0 3 ). Platinum is particularly preferred as the metal.
  • the metal-containing electrode layer dielectric layer containing metal oxide which is the high ⁇ dielectric or the ferroelectric capacitor dielectric, in particular in the case of a semiconductor memory.
  • Metal oxides of the general ABO x or D0 X are used in particular for the dielectric metal oxide-containing layer, A being in particular for at least one metal from the group strontium (Sr), bismuth (Bi), niobium (Nb), lead (Pb), zircon (Zr ), Lanthanum (La), lithium (Li), potassium (K), calcium (Ca) and barium (Ba), B in particular for at least one metal from the group titanium (Ti), niobium (Nb), ruthenium (Ru) ,
  • X can be between 2 and 12.
  • these metal oxides have dielectric or ferroelectric properties, these properties possibly being detectable only after a high-temperature step for the crystallization of the metal oxides. Under certain circumstances, these materials are in polycrystalline form, and perovskite-like crystal structures, mixed crystals or superlattices can often be observed.
  • all perovskite-like metal oxides of the general form AB0 ⁇ are suitable for forming the dielectric metal oxide-containing ones
  • Dielectric materials with high ⁇ ( ⁇ > 20) or materials with ferroelectric properties are, for example, barium strontium titanate (BST, Ba :. X Sr x Ti0 3 ), niobium-doped strontium bismuth tantalate (SBTN, Sr x Bi y ( Ta z Nb ⁇ _ z ) 0 3 ), strontium titanate (STO, SrTi0 3 ), strontium bismuth tantalate (SBT, Sr x Bi y Ta 2 0 9 ), bismuth titanate (BTO, Bi 4 Ti 3 0 : 2 ), Lead zirconate titanate (PZT, Pb (Zr x Ti ⁇ _ x ) 0 3 ), strontium niobate (SNO, Sr 2 Nb 2 0 7 ), potassium titanate niobate (KTN) and lead lanthanum titanate ( PLTO, (Pb, La) Ti0 3 ).
  • Tantalum oxide (Ta 2 0 5 ) is also used as the high ⁇ dielectric.
  • dielectric means both a dielectric, paraelectric or ferroelectric layer, so that the dielectric metal oxide-containing layer may have dielectric, paraelectric or ferroelectric properties.
  • the microelectronic structure is preferably used in a semiconductor memory device which has at least a first and a second electrode and in between a layer containing metal oxide, which together form a storage capacitor.
  • the first electrode of this semiconductor memory device comprises at least the oxygen-containing iridium layer and the oxygen barrier layer, so that the first electrode also contains the necessary diffusion barriers in addition to an optional noble metal layer.
  • the base substrate consists in particular of silicon oxide
  • the base substrate is penetrated by at least one contact hole which is filled with polysilicon or another conductive material. If necessary, the filled contact hole closes with the surface of the
  • Base substrate flush with a metal silicide layer arranged in the contact hole. Finally, the oxygen-containing iridium layer sits on the surface of the base substrate, which completely covers the contact hole, protrudes laterally beyond it and there comes into direct contact with the base substrate.
  • Figures la to le individual process steps for producing a microelectronic structure Figures 2a to 2f further process steps for producing a microelectronic structure, Figure 3 circuit memory device as a microelectronic structure as part of a half ⁇ , Figure 4 utilization resistivity an oxygen-containing iridium film as a function of temperature ranges and
  • FIG. 5 shows the specific resistance of an oxygen-containing iridium layer as a function of the oxygen content in the atmosphere during the deposition
  • FIG. 6 shows the adhesive strength of an oxygen-containing iridium layer on a silicon oxide layer as a function of the deposition temperature
  • FIG. 7 shows the adhesive strength of an oxygen-containing iridium layer on a silicon nitride layer as a function of the deposition temperature
  • FIGS. 8 and 9 results of X-ray structure examinations on deposited oxygen-containing iridium layers.
  • a base substrate 5 made of silicon dioxide for example by deposition using tetraethyl
  • TEOS Ortho-silane
  • silicon nitride which is penetrated by a contact hole 10 filled with polysilicon 8.
  • the filled contact hole 10 is flush with the surface 15 of the base substrate 5.
  • CMP chemical mechanical polishing
  • a titanium layer of the same thickness can also be applied instead of the tungsten silicide, although the titanium is largely completely covered by the polysilicon 8 in a later high-temperature step is siliconized in the contact hole 10.
  • the silicon-containing layer 20 here represents the silicon-containing layer. It is also possible to apply a polysilicon layer instead of the tungsten silicide layer 20, so that there is an adhesive layer (polysilicon, silicide) between the subsequently applied oxygen-containing iridium layer and the base substrate.
  • a polysilicon layer instead of the tungsten silicide layer 20, so that there is an adhesive layer (polysilicon, silicide) between the subsequently applied oxygen-containing iridium layer and the base substrate.
  • An oxygen-containing iridium layer 25 is then applied to the tungsten silicide layer 20 by reactive sputtering of iridium. This takes place at a pressure between 0.005 and 0.02 mbar, preferably at 0.015 mbar and in an oxygen-argon mixture, the volume fraction of oxygen being between 2.5% and 15%, preferably 5% (2.5% ⁇ 0 2 / (0 + Ar) ⁇ 15%). After a sputtering process of approximately 100 seconds, an approximately 50 to 150 nm thick oxygen-containing iridium layer 25 has formed, which completely covers the tungsten silicide layer 20.
  • the deposited oxygen-containing iridium layer 25 resists iridium silicide formation on contact with the tungsten silicide even at very high temperatures, which can be up to 800 ° C., for example, in the case of a so-called ferroaneal that occurs later. This resistance is also observed with an oxygen-containing iridium layer 25 deposited directly on the polysilicon.
  • the oxygen-containing iridium layer 25 and the tungsten silicide layer 20 are etched together anisotropically, the two layers should continue to protrude slightly laterally beyond the contact hole 10 in order to completely cover the polysilicon contained therein.
  • the structure thus obtained is shown in FIG. 1b.
  • Base substrate 5 applied and anisotropically etched using a mask. Care must be taken to ensure that the iridium dioxide layer 30 completely covers the oxygen-containing iridium layer 25 and the tungsten silicide layer 20 on its side regions 32 as well. This ensures complete protection of the oxygen-containing iridium layer 25 and the tungsten silicide layer 20 against an oxygen attack and prevents contact between the oxygen-containing iridium layer 25 and a subsequently applied precious metal layer 35 made of platinum.
  • the separation of the oxygen-containing iridium layer 25 from the platinum layer 35 is intended in particular to prevent the formation of a platinum-iridium alloy, which could possibly lead to unfavorable interface properties of the platinum layer 35.
  • a strontium-bismuth-tantalate layer (SBT) 40 is applied to the noble metal layer 35 shown in FIG. deposited using beta diketonates. This is preferably done at temperatures between 300 and 800 ° C and in particular in the MOCVD process in an oxygen-containing atmosphere in order to protect the strontium and bismuth beta
  • the SBT layer 40 forms the dielectric layer containing metal oxide.
  • FIGS. 2a to 2f Process steps for producing a microelectronic structure with a buried oxygen-containing iridium layer are shown in FIGS. 2a to 2f.
  • a basic substrate 5 is assumed, which can optionally also be constructed from two layers.
  • the basic substrate 5 of a lower silicon dioxide layer 50 located thereabove with silicon nitride or TEOS layer 55.
  • the Grundsub ⁇ strat 5 also has a contact hole 10 which is not filled up to the surface 15 of the base substrate 5 with polysilane lizium. This structure is achieved in particular by etching back the polysilicon after filling the contact hole.
  • a platinum, titanium or cobalt layer with a thickness between 30 and 100 nm is first applied to this structure shown in FIG.
  • a metal silicide is formed exclusively in the area of the contact hole 10 filled with polysilicon. Due to different etching properties of the metal silicide formed compared to the unsilicated metal, the titanium, platinum or cobalt layer is removed again except for the self-aligned metal silicide 65 formed. However, the metal silicide 65 formed from titanium, platinum or cobalt silicide does not reach the surface 15 of the base substrate 5, so that the contact hole 10 is not yet completely filled.
  • the oxygen-containing iridium layer 25 it is also possible to leave the oxygen-containing iridium layer 25 at least partially on the surface 15 of the base substrate 5.
  • the base substrate 5 be deposited during the deposition of the oxygen-containing ones To heat iridium layer 25 to at least 250 ° C. For example, a temperature of around 300 ° C is favorable. At elevated temperatures, the adhesion of the oxygen-containing iridium layer to the metal silicide also improves.
  • the oxygen barrier layer 30 made of iridium dioxide is subsequently applied and structured, the contact hole 10 being completely covered by this layer. Then the noble metal layer 35, the dielectric metal oxide-containing layer 40 and the further noble metal layer 45 are applied and suitably structured.
  • a high-temperature annealing step (e.g. ferroaneal) in an oxygen-containing atmosphere for crystallization of the dielectric layer 40 containing metal oxide.
  • this treatment must be carried out at 800 ° C. for about 1 hour.
  • the SBT should crystallize completely in order to achieve the highest possible remanent polarization of the SBT layer 40.
  • the high-temperature annealing step can also take place before the further noble metal layer 45 is deposited.
  • FIG. 1 A semiconductor memory device which contains the microelectronic structure according to the invention is shown in FIG.
  • This device comprises a selection transistor 70 and a storage capacitor 75.
  • the selection transistor 70 has two separate doped regions 80 and 85 in a single-crystalline silicon substrate 90, which represent a source and a drain region (80, 85) of the selection transistor 70.
  • the gate electrode 95 with the underlying gate dielectric 100 is arranged on the silicon substrate 90 between the two doped regions 80 and 85.
  • the gate electronics trode 95 and the gate dielectric 100 are from the side
  • Isolation webs 105 and upper insulation layers 110 surrounded. The entire structure is completely covered by the base substrate 5.
  • a contact hole 10 extends through the base substrate 5 to the doped region 85, as a result of which the storage capacitor 75 seated on the base substrate 5 is connected to the selection transistor.
  • the storage capacitor 75 in turn consists of a lower electrode 115, a capacitor dielectric 40 and an upper electrode 45.
  • the lower electrode 115 comprises a platinum layer 35, an iridium dioxide layer 30 and an oxygen-containing iridium layer 25.
  • the lower electrode 115 is thus multilayered built up and also includes all the necessary barrier layers for protecting the polysilicon 8 located in the contact hole 10 against oxidation and for protecting against unwanted silicon diffusion.
  • the oxygen-containing iridium layer 25 can be characterized by a very low specific resistance. This is shown, for example, in FIG. 4, which shows measurement curves of anoxidized iridium (oxygen-containing iridium layer marked with Ir (O)) on different silicon-containing layers.
  • anoxidized iridium was deposited on polysilicon, titanium silicide or platinum silicide in a 5% strength oxygen atmosphere and subsequently treated for about 1 ⁇ hours at different temperatures.
  • the specific resistance in the temperature range between room temperature and 800 ° C is always less than 20 ⁇ Ohm * cm, with anoxidized iridium on platinum silicide even significantly below 10 ⁇ Ohm * cm.
  • FIGS. 8 and 9 show results of X-ray structure analyzes of deposited oxygen-containing iridium layers on polysilicon.
  • FIG. 8 shows results which were obtained immediately after the deposition of the oxygen-containing iridium layer, whereas in FIG. 9 the results obtained after tempering at 700 ° C. in a nitrogen atmosphere are plotted. It can be clearly seen by comparing FIGS. 8 and 9 that no silicide formation occurs during high-temperature treatment in the case of oxygen-containing iridium layers which have been deposited with an oxygen content of at least 2.5%.
  • the oxygen-containing iridium layer can also be characterized by its relatively low oxygen content.
  • the stoichiometric ratios of oxygen-containing iridium layer differ markedly from those oxide layer a Iridiumdi- (Ir ⁇ 2> - the s, for example, that in the oxygen-containing iridium layer more iridium is present as oxygen extremely therein.
  • oxygen-containing iridium layer does not form a continuous iridium silicide layer on a conductive silicon-containing layer, even at temperatures up to 800 ° C., which would lead to an increase in the electrical resistance.
  • the oxygen-containing iridium layer is therefore also particularly suitable as a barrier layer in a semiconductor memory that uses ferroelectric SBT or PZT as a capacitor dielectric.
  • FIGS. 6 and 7 show The adhesive strength of the oxidized iridium layer (Ir (O)) as a function of the deposition temperature.
  • FIG. 6 shows the adhesive strength of Ir (O) to a silicon oxide layer obtained by TEOS deposition
  • FIG. 7 shows the adhesive strength to a stoichiometric silicon nitride layer (Si 3 N 4 ).
  • the adhesive strength increases after a crack at approximately 250 ° C. with increasing deposition temperature. It is therefore advantageous to choose a sufficiently high separation temperature.
  • the adhesive strength can be determined in particular using a so-called “pull test”, which is also frequently referred to in the literature as a “peel test”, “forehead peel test” or “Sebastian five test”.
  • the pull test allows quantitative statements to be made about the adhesive strength of thin layers on substrates.
  • a cylindrical body (“stud") is generally attached to one of its end faces using a bonding layer with very good adhesive properties on the layer on the substrate.
  • the connecting layer should connect the cylindrical body with the layer sufficiently firmly.
  • a measuring device is subsequently used to determine what force is required to detach the cylindrical body from the substrate.
  • the connecting layer for fastening the cylindrical body to the layer should have a sufficiently high adhesive strength, which is above the expected adhesive strength of the oxygen-containing iridium layer to the substrate.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)
  • Physical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

L'invention concerne une structure micro-électronique comprenant une couche d'iridium oxygénée (25) intercalée entre une couche contenant du silicium (8, 20) et une couche barrière d'oxygène (30). Cette couche d'iridium peut être produite notamment par un procédé de pulvérisation en atmosphère oxygénée à faible fraction d'oxygène. La couche d'iridium oxygénée (25) est stable jusqu'à 800 DEG C et résiste la formation de siliciure d'iridium lors de son contact avec la couche contenant du silicium (20). On applique de telles structures micro-électroniques, de préférence, dans les mémoires à semi-conducteurs.
EP99967896A 1998-12-23 1999-12-22 Structure electrode de condensateur Withdrawn EP1153424A1 (fr)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
DE19860080 1998-12-23
DE1998160080 DE19860080B4 (de) 1998-12-23 1998-12-23 Mikroelektronische Struktur
DE19909295 1999-03-03
DE1999109295 DE19909295A1 (de) 1999-03-03 1999-03-03 Mikroelektronische Struktur
PCT/DE1999/004081 WO2000039842A1 (fr) 1998-12-23 1999-12-22 Structure electrode de condensateur

Publications (1)

Publication Number Publication Date
EP1153424A1 true EP1153424A1 (fr) 2001-11-14

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EP99967896A Withdrawn EP1153424A1 (fr) 1998-12-23 1999-12-22 Structure electrode de condensateur

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US (1) US6573542B2 (fr)
EP (1) EP1153424A1 (fr)
JP (1) JP3665570B2 (fr)
KR (1) KR100430324B1 (fr)
WO (1) WO2000039842A1 (fr)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6475911B1 (en) * 2000-08-16 2002-11-05 Micron Technology, Inc. Method of forming noble metal pattern
KR100391987B1 (ko) * 2000-09-18 2003-07-22 삼성전자주식회사 강유전체 캐퍼시터를 갖는 반도체 장치 및 그 제조방법
US6794705B2 (en) 2000-12-28 2004-09-21 Infineon Technologies Ag Multi-layer Pt electrode for DRAM and FRAM with high K dielectric materials
DE10114406A1 (de) 2001-03-23 2002-10-02 Infineon Technologies Ag Verfahren zur Herstellung ferroelektrischer Speicherzellen
JP2002359353A (ja) * 2001-03-26 2002-12-13 Seiko Epson Corp 強誘電体メモリ及び電子機器
KR100359299B1 (en) * 2001-03-26 2002-11-07 Samsung Electronics Co Ltd Semiconductor memory device having resist pattern and method for forming metal contact thereof
KR100410981B1 (ko) * 2001-05-18 2003-12-12 삼성전자주식회사 저저항을 갖는 반도체 소자의 금속배선구조 및 그의형성방법
KR20030002863A (ko) * 2001-06-30 2003-01-09 주식회사 하이닉스반도체 코어를 가진 플러그 구조 상의 강유전체 메모리소자 및 그제조방법
JP2003045960A (ja) * 2001-08-01 2003-02-14 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
KR100423906B1 (ko) * 2001-08-08 2004-03-22 삼성전자주식회사 강유전성 메모리 장치 및 그 제조방법
KR100422594B1 (ko) * 2001-09-12 2004-03-16 주식회사 하이닉스반도체 반도체 소자의 커패시터 및 제조방법
US6885570B2 (en) * 2001-11-09 2005-04-26 Interuniversitair Microelektronica Centrum vzw (IMEC vzw) Simplified bottom electrode-barrier structure for making a ferroelectric capacitor stacked on a contact plug
DE10207130B4 (de) * 2002-02-20 2007-09-27 Infineon Technologies Ag Verfahren zur Herstellung eines Bauelements sowie Bauelement mit einer Edelmetallschicht, einer Edelmetallsilizidschicht und einer oxidierten Silizidschicht
KR100471163B1 (ko) * 2002-03-14 2005-03-09 삼성전자주식회사 커패시터들을 갖는 반도체소자의 제조방법
US6583507B1 (en) * 2002-04-26 2003-06-24 Bum Ki Moon Barrier for capacitor over plug structures
JP2003332539A (ja) * 2002-05-17 2003-11-21 Nec Electronics Corp 強誘電体キャパシタ及びその製造方法並びに半導体記憶装置
WO2005074032A1 (fr) * 2004-01-28 2005-08-11 Fujitsu Limited Dispositif semiconducteur et son procédé de fabrication
US20050161717A1 (en) * 2004-01-28 2005-07-28 Fujitsu Limited Semiconductor device and method of fabricating the same
KR100615092B1 (ko) * 2004-08-16 2006-08-23 삼성전자주식회사 노드 도전막 패턴들에 각각 자기 정렬시킨 하부 전극들을갖는 에프. 램들 및 그 형성방법들
KR101101566B1 (ko) * 2006-03-30 2012-01-02 후지쯔 세미컨덕터 가부시키가이샤 반도체 장치 및 그 제조 방법
KR100881055B1 (ko) * 2007-06-20 2009-01-30 삼성전자주식회사 상변화 메모리 유닛, 이의 제조 방법, 이를 포함하는상변화 메모리 장치 및 그 제조 방법
US8021940B2 (en) * 2007-12-31 2011-09-20 Intel Corporation Methods for fabricating PMOS metal gate structures

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5566045A (en) 1994-08-01 1996-10-15 Texas Instruments, Inc. High-dielectric-constant material electrodes comprising thin platinum layers
US5576579A (en) * 1995-01-12 1996-11-19 International Business Machines Corporation Tasin oxygen diffusion barrier in multilayer structures
JPH09102591A (ja) * 1995-07-28 1997-04-15 Toshiba Corp 半導体装置及びその製造方法
JP3396131B2 (ja) * 1996-06-28 2003-04-14 三菱電機株式会社 半導体装置およびその製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0039842A1 *

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US20020070404A1 (en) 2002-06-13
JP3665570B2 (ja) 2005-06-29
WO2000039842A1 (fr) 2000-07-06
JP2002533953A (ja) 2002-10-08

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