EP1138065A1 - Procede de production d'une couche structuree contenant un oxyde metallique - Google Patents

Procede de production d'une couche structuree contenant un oxyde metallique

Info

Publication number
EP1138065A1
EP1138065A1 EP98962218A EP98962218A EP1138065A1 EP 1138065 A1 EP1138065 A1 EP 1138065A1 EP 98962218 A EP98962218 A EP 98962218A EP 98962218 A EP98962218 A EP 98962218A EP 1138065 A1 EP1138065 A1 EP 1138065A1
Authority
EP
European Patent Office
Prior art keywords
metal oxide
layer
sbt
containing layer
structuring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98962218A
Other languages
German (de)
English (en)
Inventor
Walter Hartner
Frank Hintermaier
Günther SCHINDLER
Volker Weinrich
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority claimed from PCT/DE1998/003249 external-priority patent/WO2000028584A1/fr
Publication of EP1138065A1 publication Critical patent/EP1138065A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02356—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31691—Inorganic layers composed of oxides or glassy oxides or oxide based glass with perovskite structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material

Definitions

  • the invention is in the field of semiconductor technology and relates to a method for producing a structured layer containing metal oxide.
  • Such layers are to be used in the future, inter alia, as a capacitor dielectric in semiconductor memories, since these layers have high dielectric constants or are ferroelectric.
  • metal oxide-containing layer should therefore be understood in the further layers with a dielectric constant ⁇ > 10 and ferroelectric layers.
  • the latter are characterized in particular by their ability to maintain a remanent (permanent) polarization that can be polarized by an electric field.
  • the polarization of the metal oxide-containing layer follows a hysteresis characteristic of the respective layer.
  • these layers In order for these layers to have the desired dielectric or ferroelectric properties, they usually have to polycrystalline.
  • Layers containing metal oxide consist either of a metal oxide, such as tantalum oxide (Ta 2 0 3 ) or titanium oxide (Ti0 2 ), or of a mixture of at least two metal oxides.
  • the latter are also often referred to as the ABO class, with O for oxygen, A and B for metals from the group strontium, calcium, barium, bismuth, cadmium, lead, titanium, tantalum, hafnium, tungsten, niobium, zirconium, scandiu , Yttrium, lanthanum, antimony, chromium and talium.
  • These metal oxides or metal oxide mixtures form crystal or crystal superlattices, the latter being the successive change of several Sub-lattice is understood.
  • a typical crystal structure is, for example, the layered perovskite structure, which occurs, for example, in the case of strontium bismuth tantalate (SrBi 2 Ta 2 0 9 ).
  • a method for producing a structured metal oxide-containing and polycrystalline layer is described, for example, in US Pat. No. 5,434,102.
  • a layer containing metal oxide is first applied to a substrate.
  • the still amorphous layer is then briefly heated to induce crystallization nuclei and then subjected to a heat treatment.
  • the layer containing metal oxide crystallizes completely to form a polycrystalline layer which can be structured further.
  • layers produced and structured in this way show stoichiometric deviations, which can lead to impairment of the desired dielectric or ferroelectric properties, in particular in the case of very fine structuring in the micrometer and submicron range (structure width approximately equal to or less than 1 ⁇ m).
  • One consequence of these stoichiometric deviations is a lower electrical load capacity of the layer containing metal oxide.
  • this is undesirable in particular in the case of highly integrated semiconductor components, for example in the case of semiconductor memories.
  • This object is achieved according to the invention by a method for producing a structured metal oxide-containing layer with the following method steps: provision of a substrate;
  • the basic idea of the invention is to carry out the heat treatment, in which the applied and initially essentially amorphous metal oxide-containing layer is subjected to a crystallization process, only after the structuring of the metal oxide-containing layer.
  • This creates particularly robust layers containing metal oxide, which e.g. have a low leakage current. It is also characteristic of the layers created in this way that the stoichiometric conditions are only insignificantly influenced by the structuring and the heat treatment.
  • the layers produced in this way prove to be particularly stable in the case of electrical layers which reach the electrical breakdown
  • the mobile and diffusion-friendly metal oxides can diffuse relatively quickly to active areas of components and irreversibly influence them.
  • the layer containing metal oxide is structured before it crystallizes.
  • the layer containing metal oxide is essentially still amorphous, so that there are no diffusion paths formed by grain boundaries. Rather, the amorphous layer containing metal oxide is only removed in layers by the structuring, so that a possible evaporation of metal oxides can only take place from the uppermost and thus extremely thin layer. Possible disturbances can therefore only extend to a few atomic layers and do not extend relatively far into the layer itself, as is already the case with polycrystalline layers, due to the diffusion facilitated there.
  • the layer containing metal oxide is essentially amorphous. This state occurs immediately after the deposition of the metal oxide-containing layer and is due to a non-crystalline structure, which may already be a few, but relatively small May have crystallites.
  • essentially amorphous layers containing metal oxides do not yet have the desired dielectric or ferroelectric properties, ie the dielectric constant is relatively low or no or only a negligibly low remanent polarization can be brought about.
  • these layers In order to improve or bring about the dielectric or ferroelectric properties, these layers must therefore be subjected to crystallization, these layers then being essentially polycrystalline after crystallization.
  • the aim is to achieve as complete a crystallization as possible with the formation of relatively large crystal domains, since it is precisely these crystal domains that determine the desired properties.
  • the method according to the invention is preferably used for the production of semiconductor memory elements in which the memory element is formed by a dielectric or ferroelectric capacitor.
  • Layer serves as a capacitor dielectric, which is located between two electrodes.
  • an electrode layer is preferably deposited on the substantially amorphous metal oxide-containing layer and structured together with the latter.
  • the subsequently deposited electrode layer protects the relatively sensitive layer containing metal oxide during structuring.
  • the number of process steps is reduced by structuring the electrode layer and the layer containing metal oxide together.
  • This step is, for example, a so-called rapid thermal process (RTP), in which the first nuclei are formed in the metal oxide-containing layer by a relatively short heating, but there is still no complete crystallization. This takes place only subsequently during the heat treatment under optimal conditions.
  • RTP rapid thermal process
  • the nucleation process can either be carried out immediately after the essentially amorphous metal oxide-containing layer has been applied, or can follow the structuring of the metal oxide-containing layer.
  • the metal oxide-containing layer preferably consists of strontium bismuth tantalate (SBT), strontium bismuth niobate tantalate (SBTN), lead zirconium titanate (PZT), barium strontium titanate (SBT), lead lanthanum titanate ( PLT), lead-lanthanum-zirconium-titanate (PLZT), bismuth-titanate (BTO) or metal oxides protruding from a derivative.
  • SBT strontium bismuth tantalate
  • SBTN strontium bismuth niobate tantalate
  • PZT lead zirconium titanate
  • PLT barium strontium titanate
  • PLT lead lanthanum titanate
  • PLT lead-lanthanum-zirconium-titanate
  • BTO bismuth-titanate
  • Figure 5 shows the leakage current behavior of the metal oxide-containing layer
  • Figure 6 shows the polarization behavior of a metal oxide-containing layer.
  • Ferroelectric SBT (strontium bismuth tantalate) should preferably be close to the ideal stoichiometry of SrBi 2 Ta 2 0 9 and have a perovskite-like crystal structure.
  • a semiconductor body is provided (1).
  • This usually comprises a silicon base substrate, into which active components, for example field effect transistors, are integrated.
  • the silicon base substrate is covered by a planarizing insulation layer, which usually consists of Si0 2 . This insulation layer is intended to represent the substrate.
  • At least one first electrode which preferably consists of platinum and has a height of approximately 50 to 300 nm, is located on the substrate.
  • Other preferred electrode materials are ruthenium, iridium and their conductive oxides.
  • An SBT layer is subsequently deposited on the substrate (2). This is preferably done by means of metal-organic chemical vapor deposition (MOCVD) in a suitable CVD reactor. Before the deposition, the starting products are in
  • Beta-diketonates are preferably used as complexing agents.
  • the starting products are introduced into the CVD reactor and mixed with an oxidizing agent, for example 0 2 or N 2 0. This serves to oxidize the metal complexes, so that metal oxides can be deposited as an amorphous layer on the substrate and the electrode thereon.
  • a nucleation process 3 follows, in the form of a rapid thermal process
  • RTP is carried out. This step is relatively short and is only a few seconds, a temperature for nucleation being set between 500 to 800 ° C, preferably between 600 and 750 ° C. During the nucleation process (3), first crystal nuclei are formed, which, however, cannot continue to grow due to the relatively short treatment time, so that even after this step the SBT layer is still essentially amorphous.
  • the SBT layer is anisotropically etched using a mask (4).
  • etching processes with a high physical component.
  • Such etching processes use, for example, an argon plasma.
  • Chlorine ions can also be present in the plasma, which, in addition to the physical removal, also have a chemical component.
  • the SBT layer is crystallized or heat-treated (5) at about 750 ° C. for about 1 hour in an oxygen-containing atmosphere.
  • the crystallization nuclei already formed thereby grow at the expense of the amorphous portions of the SBT layer, which leads to an essentially polycrystalline layer.
  • the crystallization should preferably take place in such a way that the grain size is as uniform as possible, the individual grains not becoming too large, so that the relatively thin SBT layer (approx. 20 to 180 nm, preferably approx. 40 to 150 nm) does not become too thick has large surface roughness.
  • FIG. 2 A further process sequence is shown in FIG. 2, in which a platinum layer is additionally deposited to form a second electrode.
  • Process steps (1) and (2) are identical to those shown in FIG. 1.
  • a platinum layer is then applied over the entire surface (6), this preferably being done by a sputtering process.
  • the platinum layer obtained has a material thickness of approximately 50 to 200 nm.
  • FIG. 1 Another possible modification of the manufacturing method according to the invention is shown in FIG. This modification differs from the process sequence described in FIG. 2 in that the nucleation process (3) is only carried out after the etching or structuring (7) of the SBT and the platinum layer.
  • the nucleation process (3) can in principle be carried out at any time between the deposition of the SBT layer and the heat treatment (5), that is to say before or after
  • a substrate 20 is provided. This corresponds to process step (1).
  • the substrate 20 is an SiO 2 layer on which a first electrode 22 with a barrier layer 24 located below it is arranged.
  • the first electrode 22 consists of platinum, the barrier layer 24, for example, of a titanium / titanium nitride combination or of other suitable materials.
  • the barrier layer 24 is intended in particular to prevent diffusion of the platinum at elevated process temperatures into the substrate 20 and into the contact hole 26 located there and filled with a conductive material. Polycrystalline silicon is preferably used as the conductive material.
  • the contact hole 26 connects the first electrode 22 to a source or drain region of a selection transistor, not shown here.
  • An SBT layer 28 is subsequently applied to the substrate 20 thus provided.
  • the deposition takes place as described above, in which an amorphous SBT layer 28 is initially formed.
  • a platinum layer 30 is applied to the entire surface of the SBT layer by means of a sputtering process.
  • RTP step through which the first crystallization nuclei form within the SBT layer 28.
  • this RTP step can also be carried out after the subsequent structuring or before the deposition of the platinum layer 30.
  • the structure thus obtained is shown in Figure 4b.
  • the SBT layer 28 is etched anisotropically together with the platinum layer 30 in accordance with method step (7). This is indicated by the arrows shown in Figure 4c. The result is the structure shown in this figure.
  • the etching (4) is carried out in such a way that the side regions 32 of the lower electrode 22 continue to be completely covered by the SBT layer 28, since these should contribute to the storage capacity.
  • the steps shown in FIGS. 4a to 4d can be suitably changed in order to produce the SBT layer 28.
  • the SBT layers produced using the method according to the invention were further characterized in terms of their ferroelectric properties.
  • comb-like test structures with different structure widths of the comb teeth were created with the same total base area of the individual comb-like structures. With a comb-like structure with a smaller structure width, this increases the overall circumference.
  • the comb-like structures consist of a layer stack formed from a lower platinum electrode, an SBT layer and an upper platinum electrode.
  • the SBT layers produced according to the invention have a low leakage current even with small structural widths (less than 1 ⁇ m). This indicates layers that are relatively resistant to breakthrough.
  • a second important characterization variable is the amount of the remanent polarization, which is plotted in FIG. 6. Here, too, it can be clearly seen that the polarization remains relatively constant even with small structures. Such a result could not be determined for the SBT layers produced using previously known methods.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un procédé de production d'une couche strontinium-wismut-tantalate (SBT), selon lequel, après son dépôt (2), la couche SBT est structurée (4, 7) comme couche encore amorphe et ensuite seulement elle est soumise à un processus de cristallisation (5). Les couches ainsi produites présentent une rigidité diélectrique assez élevée et aucun écart stoechiométrique sur les bords gravés.-
EP98962218A 1998-11-06 1998-11-06 Procede de production d'une couche structuree contenant un oxyde metallique Withdrawn EP1138065A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/DE1998/003249 WO2000028584A1 (fr) 1998-11-06 1998-11-06 Procede de production d'une couche structuree contenant un oxyde metallique

Publications (1)

Publication Number Publication Date
EP1138065A1 true EP1138065A1 (fr) 2001-10-04

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EP98962218A Withdrawn EP1138065A1 (fr) 1998-11-06 1998-11-06 Procede de production d'une couche structuree contenant un oxyde metallique

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EP (1) EP1138065A1 (fr)

Families Citing this family (9)

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Publication number Priority date Publication date Assignee Title
DE10219123B4 (de) * 2002-04-29 2004-06-03 Infineon Technologies Ag Verfahren zur Strukturierung keramischer Schichten auf Halbleitersubstanzen mit unebener Topographie
JP4666575B2 (ja) * 2004-11-08 2011-04-06 東京エレクトロン株式会社 セラミック溶射部材の製造方法、該方法を実行するためのプログラム、記憶媒体、及びセラミック溶射部材
JP4555865B2 (ja) * 2005-08-22 2010-10-06 トーカロ株式会社 耐損傷性等に優れる溶射皮膜被覆部材およびその製造方法
US20090130436A1 (en) * 2005-08-22 2009-05-21 Yoshio Harada Spray coating member having excellent heat emmision property and so on and method for producing the same
JP4571561B2 (ja) * 2005-09-08 2010-10-27 トーカロ株式会社 耐プラズマエロージョン性に優れる溶射皮膜被覆部材およびその製造方法
JP4643478B2 (ja) * 2006-03-20 2011-03-02 トーカロ株式会社 半導体加工装置用セラミック被覆部材の製造方法
US7850864B2 (en) * 2006-03-20 2010-12-14 Tokyo Electron Limited Plasma treating apparatus and plasma treating method
US7892964B2 (en) * 2007-02-14 2011-02-22 Micron Technology, Inc. Vapor deposition methods for forming a metal-containing layer on a substrate
US20160068990A1 (en) * 2013-04-18 2016-03-10 Drexel University Methods of forming perovskite films

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US5434102A (en) 1991-02-25 1995-07-18 Symetrix Corporation Process for fabricating layered superlattice materials and making electronic devices including same
EP0557937A1 (fr) * 1992-02-25 1993-09-01 Ramtron International Corporation Traitement à l'ozone gazeux pour circuits à mémoire ferroélectrique
US6025619A (en) * 1992-10-23 2000-02-15 Azuma; Masamichi Thin films of ABO3 with excess A-site and B-site modifiers and method of fabricating integrated circuits with same
JPH06350050A (ja) 1993-06-08 1994-12-22 Oki Electric Ind Co Ltd 半導体素子の電荷蓄積部の誘電体絶縁膜の形成方法
WO1998005071A1 (fr) 1996-07-26 1998-02-05 Symetrix Corporation Procede pour fabriquer un circuit integre avec des couches minces a structuration spontanee
JPH10223845A (ja) 1996-12-05 1998-08-21 Sanyo Electric Co Ltd 誘電体素子の製造方法
US6133092A (en) * 1998-07-24 2000-10-17 Symetrix Corporation Low temperature process for fabricating layered superlattice materials and making electronic devices including same

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US6586348B2 (en) 2003-07-01
US20010055890A1 (en) 2001-12-27

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