EP1166345A1 - Procede de production d'une structure microelectronique - Google Patents

Procede de production d'une structure microelectronique

Info

Publication number
EP1166345A1
EP1166345A1 EP00930977A EP00930977A EP1166345A1 EP 1166345 A1 EP1166345 A1 EP 1166345A1 EP 00930977 A EP00930977 A EP 00930977A EP 00930977 A EP00930977 A EP 00930977A EP 1166345 A1 EP1166345 A1 EP 1166345A1
Authority
EP
European Patent Office
Prior art keywords
layer
conductive layer
substrate
platinum
oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00930977A
Other languages
German (de)
English (en)
Inventor
Hermann Wendt
Elke Fritsch
Reinhard Stengl
Wolfgang Hoenlein
Siegfried Schwarzl
Gerhard Beitel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1166345A1 publication Critical patent/EP1166345A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material

Definitions

  • the invention is in the field of semiconductor technology and relates to a method for producing a microelectronic structure, in particular a method for producing semiconductor memories.
  • capacitor dielectric In the manufacture of semiconductor memories, e.g. represent a microelectronic structure, materials with a high dielectric constant or with ferroelectric properties are increasingly being used as a capacitor dielectric.
  • semiconductor memories have a multiplicity of memory cells which comprise at least one selection transistor and a storage capacitor.
  • the storage capacitor consists of the capacitor dielectric, which is located between two electrodes.
  • a suitable capacitor dielectric with a sufficiently high dielectric constant is, for example, barium strontium titanate (BST).
  • BST barium strontium titanate
  • this material requires an oxidizing atmosphere when it is deposited or aftertreatment is required, which can lead to electrode attack. In the worst case, the electrodes are oxidized and therefore unusable. Therefore, oxidation resistant materials, e.g. Platinum, suggested as electrode materials.
  • platinum tends to siliconize at high temperatures when it comes into direct contact with silicon, as a result of which the electrical conductivity of the electrodes is impaired. For this reason, a diffusion barrier is usually arranged between the platinum electrode and a contact hole filled with silicon, by means of which a platinum or silicon diffusion is to be prevented.
  • oxygen can diffuse relatively easily through platinum and thereby layers arranged under the platinum layer, for example the platinum or silicon diffusion barrier, oxidize.
  • a further diffusion barrier is therefore required, which in particular prevents oxygen diffusion.
  • a different thickness of the capacitor dielectric leads to different field strengths when a voltage is applied to the two electrodes of the storage capacitor, which can lead to early failures of the capacitor dielectric.
  • the local oxidation of the barrier layer in the edge regions of the layer stack can lead to an increase in volume and thus to high mechanical stresses or to a deterioration in the electrical contact with the substrate underneath.
  • either lateral passivation edge webs made of an insulating material are used in accordance with EP 0 739 030 A2, or the barrier layer is completely covered with a conductive oxygen-resistant layer.
  • Another option is to burying layer. The polishing step required for this, however, is relatively complex.
  • a layer structure arranged on a substrate which partially covers the substrate and has at least one first conductive layer extending up to a side wall of the layer structure, is provided; - A second conductive layer is applied to the layer structure and the substrate; and the second conductive layer is subsequently at least partially removed from the substrate using an etching process with physical removal, so that removed material is deposited at least partially on the side wall of the layer structure.
  • a second conductive layer is applied to the layer structure partially covering the substrate and to the substrate itself. It is not necessary for the second conductive layer to conform to the layer structure and the substrate. In contrast, the second conductive layer should at least cover the exposed substrate sufficiently with a certain layer thickness.
  • the side wall of the layer structure to be protected and in particular the first conductive layer reaching as far as the side wall are subsequently covered with material from the second conductive layer by a suitably selected removal and deposition process. This is done in particular by using an etching process with physical removal, as a result of which the material is removed from the second conductive layer, which subsequently rests on the surface of the layer structure and of the substrate can deposit. Such rearrangement processes are achieved, for example, by argon sputtering.
  • detached material also deposits on the side wall of the layer structure and covers it.
  • the amount of precipitation depends, among other things, on the inclination of the side wall, the energy dose of the striking argon ions and the angular distribution of the struck atoms.
  • the second conductive layer By removing the second conductive layer, it is largely removed from the top of the layer structure and the exposed substrate. Due to the geometric relationships, the removal of material from the side walls of the layer structure takes place significantly more slowly than from the top of the layer structure and the exposed substrate. On the other hand, material that has been removed can be deposited again on the entire surface of the layer structure and the substrate, but this is done with a cosine-shaped angular distribution with respect to the sputtering atoms encountering. The simultaneous removal and deposition processes, however, together lead to a net removal of the second conductive layer, in particular from the top of the layer structure and the exposed substrate, and to a net application of removed material, in particular onto the side walls of the layer structure.
  • the sputtering atoms are used by the etching substances used in the etching process, e.g. B. Argon, formed.
  • the second conductive layer should preferably have a sufficient thickness so that a sufficient amount of material for repositioning on the side walls or. the side wall of the Layer structure is present.
  • the aim is to cover at least the first conductive layer completely with the deposited material from the second conductive layer.
  • At least the second conductive layer is preferably completely removed from the substrate by means of the etching process. It is irrelevant whether the second conductive layer is also completely removed from the top of the layer stack or partially remains on it.
  • the first conductive layer generally represents a barrier and / or adhesive layer.
  • a third conductive layer can be located on this barrier and / or adhesive layer, which is used in particular as an electrode material in semiconductor memories.
  • This can be either a conductive metal layer or a conductive metal oxide layer.
  • the metal layer can in particular consist of platinum, ruthenium, iridium, osmium, rhodium, rhenium or palladium and the metal oxide layer in particular of ruthenium oxide, iridium oxide, rhenium oxide, osmium oxide, strontium-ruthenium oxide or rhodium oxide.
  • the layer structure preferably consists of the first conductive layer located at the bottom and the third conductive layer arranged on the upper side of the first conductive layer.
  • the second conductive layer which preferably consists of platinum, is applied to this layer structure and distributed with the etching process with physical removal on the surface of the substrate or the layer structure, so that a coherent platinum layer is formed in particular on the side wall of the layer structure. In particular, this should cover the edge areas of the first conductive layer and in particular protect them from an oxygen attack in subsequent process steps.
  • the layer structure after the back zen the second conductive layer on a surface consisting entirely of a material This has an advantageous effect on layer properties of layers to be subsequently applied to the layer structure.
  • the second and third conductive layers preferably consist of a noble metal, in particular of platinum.
  • the etching process is also intended to remove the second conductive layer as completely as possible from the substrate, so that adjacent layer structures are not electrically connected by the second conductive layer.
  • a dielectric layer containing metal oxide is deposited as conformingly as possible.
  • Metal oxides of the general ABO ⁇ or DO x are used in particular for the dielectric layer containing metal oxide, which is the high- ⁇ dielectric or the ferroelectric capacitor dielectric, in particular in the case of a semiconductor memory, A being in particular for at least one metal from the strontium group (Sr ), Bismuth (Bi), niobium (Nb), lead (Pb), zircon (Zr), lanthanum (La), lithium (Li), potassium (K), calcium (Ca) and barium (Ba), B especially for at least one metal from the group titanium (Ti), niobium (Nb), ruthenium (Ru), magnesium (Mg), manganese (Mn), zirconium (Zr) or tantalum (Ta), D for titanium (Ti) or tantalum ( Ta) and 0 stands for oxygen.
  • X can be between 2 and 12.
  • these metal oxides have dielectric or ferroelectric properties, the desired high dielectric properties ( ⁇ > 20) or the high remanent polarization in ferroelectrics possibly being achieved only after a high-temperature step for crystallizing the metal oxides.
  • these materials are in polycrystalline form, and perovskite-like crystal structures, mixed crystals, layered crystal structures or superlattices can often be observed.
  • all perovskite-like metal oxides of the general form AB0 X are suitable for forming the dielectric measuring layer containing tall oxide.
  • Dielectric materials with high ⁇ ( ⁇ > 50) or materials with ferroelectric properties are, for example, barium strontium titanate (BST, Ba ⁇ - x Sr x Ti0 3 ), niobium-doped strontium bismuth tantalate (SBTN, Sr x Bi y ( Ta z Nb ⁇ _ z ) 0 3 strontium titanate (STO, SrTi0 3 ), strontium bismuth tantalate (SBT, Sr x Bi y Ta 2 0 9 ), bismuth titanate (BTO, Bi 4 Ti 3 0 ⁇ 2 ), lead Zirconate titanate (PZT, Pb (Zr x Ti ⁇ - ⁇ ) 0 3 ), strontium niobate (SNO, Sr 2 Nb 2 0 ⁇ ), potassium titanate niobate (KTN) as well as lead lanthanum titanate (PLTO, ( Pb, La) Ti0 3 ) Tantalum
  • the microelectronic structure produced by the method according to the invention also has a uniform base for the deposition of the dielectric metal oxide-containing layer. This is achieved in particular in that both the third conductive layer and the second conductive layer consist of platinum, and thereby both the top of the layer structure and its side walls are covered with a platinum layer.
  • the surface of the layer structure consisting of the same material enables a relatively uniform edge covering of the layer structure with the dielectric layer containing metal oxide, as a result of which in particular locally high electrical field strengths can be avoided.
  • the platinum protective layer formed on the side wall of the layer structure largely protects the first conductive layer against oxidation.
  • the titanium layer 15 can also consist of tantalum and the titanium nitride layer 20 of tantalum nitride.
  • the three layers 15, 20 and 25 are subsequently etched together, with layer structures 30 separated from one another remaining on the surface 10 of the base substrate.
  • These layer structures 30 each comprise the titanium layer 15 and titanium nitride layer 20 arranged in the lower region and the platinum layer 25 located in the upper region.
  • the platinum layer 25 represents the third conductive layer, whereas the titanium layer 15 and the titanium nitride layer 20 together form the first conductive layer Layer.
  • a further layer, in particular an oxygen diffusion barrier can optionally be located between the platinum layer 25 and the titanium nitride layer 20, which layer can also be included in the first conductive layer.
  • the layer structures 30 each have at least one side wall 35, which in the present case are oriented almost perpendicular to the surface 10 of the substrate 5. However, the side wall 35 can also be inclined. The inclination depends in particular on the etching process used to structure the platinum layer 25, the titanium layer 15 and the titanium nitride layer 20. This is indicated by rounded corners 40 of the platinum layer 25. If the layer structure 30 is cylindrical, it has a single side wall 35 that completely encircles the layer structure. Below each layer structure 30 there is also a contact hole 42 filled with polysilicon, which penetrates through the substrate 5 and leads, for example, to a selection transistor (not shown here). A further platinum layer 45, which here represents the second conductive layer, is subsequently applied to the substrate 5 and to the layer structure 30.
  • the side wall 35 of the layer structure 30 is covered with the further platinum layer 45.
  • non-conforming methods for example sputtering or vapor deposition, can also be used to apply the platinum layer 45.
  • the further platinum layer 45 is then etched back by a sputter etching process.
  • gas mixtures of argon and other additives for example chlorine and oxygen, are generally used.
  • the additives in particular cause the platinum layer 45 to be etched back uniformly, as a result of which relatively smooth surfaces can be produced.
  • the actual removal of the further platinum layer 45 takes place during the sputter etching process by bombarding the further platinum layer 45 by means of directed argon ions, ie the argon ions are accelerated by means of an electric field and strike the further platinum layer 45 at a relatively high speed.
  • the angle at which the argon ions strike the further platinum layer 45 can be chosen freely, but should be set so that the further platinum layer 45 located between two layer structures 30 can be removed as completely as possible from the surface 10 of the substrate 5. This is necessary on the one hand for the complete electrical insulation of adjacent layer structures 30 and on the other hand for covering the side wall 35 of each layer structure 30 as completely as possible.
  • the striking argon ions are shown with arrows 50.
  • the platinum atoms knocked out of the further platinum layer 45 have an angular distribution which essentially corresponds to a cosine distribution.
  • the detached platinum atoms are marked with arrows 55.
  • metallic protective layers 60 are formed in the form of lateral edge webs on the side wall 35 of the layer structure 30. These consist almost entirely of removed material from the further platinum layer 45, which in turn has been almost completely removed from the surface 10 of the substrate 5. It is important that the layer structures 30 are no longer electrically connected to one another by the platinum layer 45. Due to the metallic protective layer 60 consisting of platinum, which completely covers the side wall 35 and extends as far as the platinum layer 25, the layer structure 30 is completely covered by a platinum layer. This provides a surface made of a single material for the subsequent deposition of the dielectric metal oxide-containing layer.
  • the metallic protective layer 60 protects the titanium layer 15 and the titanium layer 20 in their edge regions 65, ie in the region of the side wall 35 of the layer structure 30.
  • Another advantage of the microelectronic structure produced using this method is that the metallic protective layer 60 applied may Existing sharp edges of the layer structure covered and easily compensated. As a result, topologies that are difficult to cover are defused, which creates steady or continuous height transitions on which the dielectric metal oxide-containing layer to be subsequently applied can grow uniformly and without stress.
  • the metallic protective layer 60 has a slight inclination, which likewise contributes to improved deposition of the dielectric metal oxide-containing layer. The structure described is shown in FIG. 4. Finally, according to FIG.
  • a dielectric metal oxide-containing layer 70 for example a BST layer, is applied over the entire area and conformally to the layer structure 30 and the substrate 5. This preferably follows by means of a CVD process, the layer thickness being almost constant at least in the area of the metallic protective layer 60 and the platinum layer 25 due to the same material. Finally, an upper electrode layer 75 made of platinum is applied to the dielectric metal oxide-containing layer 70 over the entire surface and largely in conformity. Possibly. the dielectric metal oxide-containing layer 70 must still be subjected to a crystallization process by means of a high-temperature step in the presence of oxygen, by means of which the desired dielectric properties, ie either a high relative dielectric constant or remanent polarization, are to be improved.
  • the method according to the invention is used in particular in the production of semiconductor memories in which there are a large number of storage capacitors on an insulating substrate 5, which are preferably constructed in the form of a stack.
  • the first, second and third conductive layers represent the lower electrode, including the necessary barriers, which are covered by a capacitor dielectric (dielectric metal oxide-containing layer) and a further upper electrode layer.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un procédé de production d'une structure microélectronique. Une structure stratifiée (30) recouvre partiellement un substrat (5) et est pourvue d'au moins une couche conductrice (15, 20) qui s'étend jusqu'à une paroi latérale (35) de ladite structure stratifiée (30). Cette structure stratifiée (30) est recouverte d'une seconde couche conductrice (45) qui est ensuite enlevée dans la plus large mesure selon un procédé d'attaque impliquant une ablation physique, le matériau ainsi enlevé étant déposé sur la paroi latérale (35) de la structure stratifiée (30). Le matériau ainsi déposé forme une couche protectrice (60) sur la paroi latérale (35), laquelle doit protéger, dans la plus large mesure, la première couche conductrice (15, 20) contre une agression par l'oxygène.
EP00930977A 1999-03-12 2000-03-10 Procede de production d'une structure microelectronique Withdrawn EP1166345A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19911150A DE19911150C1 (de) 1999-03-12 1999-03-12 Verfahren zur Herstellung einer mikroelektronischen Struktur
DE19911150 1999-03-12
PCT/DE2000/000786 WO2000054318A1 (fr) 1999-03-12 2000-03-10 Procede de production d'une structure microelectronique

Publications (1)

Publication Number Publication Date
EP1166345A1 true EP1166345A1 (fr) 2002-01-02

Family

ID=7900804

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00930977A Withdrawn EP1166345A1 (fr) 1999-03-12 2000-03-10 Procede de production d'une structure microelectronique

Country Status (8)

Country Link
US (1) US20090011556A9 (fr)
EP (1) EP1166345A1 (fr)
JP (1) JP3889224B2 (fr)
KR (1) KR100420461B1 (fr)
CN (1) CN1156897C (fr)
DE (1) DE19911150C1 (fr)
TW (1) TW475223B (fr)
WO (1) WO2000054318A1 (fr)

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KR100391987B1 (ko) * 2000-09-18 2003-07-22 삼성전자주식회사 강유전체 캐퍼시터를 갖는 반도체 장치 및 그 제조방법
KR100799117B1 (ko) * 2001-12-21 2008-01-29 주식회사 하이닉스반도체 반도체 소자의 캐패시터 제조방법
US6821901B2 (en) * 2002-02-28 2004-11-23 Seung-Jin Song Method of through-etching substrate
JP2004281742A (ja) * 2003-03-17 2004-10-07 Japan Science & Technology Agency 半導体素子、半導体センサーおよび半導体記憶素子
TWI333808B (en) 2005-05-05 2010-11-21 Himax Tech Inc A method of manufacturing a film printed circuit board
US20070264427A1 (en) * 2005-12-21 2007-11-15 Asm Japan K.K. Thin film formation by atomic layer growth and chemical vapor deposition
CN103187244B (zh) * 2013-04-03 2016-05-11 无锡华润上华科技有限公司 一种改善半导体晶圆电容制程中介质分层的方法
KR102309880B1 (ko) * 2014-12-08 2021-10-06 삼성전자주식회사 전도성 박막

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US5585300A (en) * 1994-08-01 1996-12-17 Texas Instruments Incorporated Method of making conductive amorphous-nitride barrier layer for high-dielectric-constant material electrodes
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JP3101685B2 (ja) * 1995-02-28 2000-10-23 マイクロン・テクノロジー・インコーポレイテッド 再蒸着を用いた構造体の形成方法
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Also Published As

Publication number Publication date
KR20010102453A (ko) 2001-11-15
JP2002539608A (ja) 2002-11-19
US20090011556A9 (en) 2009-01-08
JP3889224B2 (ja) 2007-03-07
US20020155660A1 (en) 2002-10-24
CN1343370A (zh) 2002-04-03
KR100420461B1 (ko) 2004-03-02
CN1156897C (zh) 2004-07-07
WO2000054318A1 (fr) 2000-09-14
TW475223B (en) 2002-02-01
DE19911150C1 (de) 2000-04-20

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