EP1151365B1 - Schnelle spannungserzeugung auf dem chip für integrierte schaltungen niedriger leistung - Google Patents

Schnelle spannungserzeugung auf dem chip für integrierte schaltungen niedriger leistung Download PDF

Info

Publication number
EP1151365B1
EP1151365B1 EP98960305A EP98960305A EP1151365B1 EP 1151365 B1 EP1151365 B1 EP 1151365B1 EP 98960305 A EP98960305 A EP 98960305A EP 98960305 A EP98960305 A EP 98960305A EP 1151365 B1 EP1151365 B1 EP 1151365B1
Authority
EP
European Patent Office
Prior art keywords
circuit
signal
voltage
transition
boost
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP98960305A
Other languages
English (en)
French (fr)
Other versions
EP1151365A4 (de
EP1151365A1 (de
Inventor
Kuen-Long Chang
Chun-Hsiung Hung
Ken-Hui Chen
Tien-Shin Ho
I-Long Lee
Tzeng-Hei Shiau
Ray-Lin Wan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Macronix International Co Ltd
Original Assignee
Macronix International Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Macronix International Co Ltd filed Critical Macronix International Co Ltd
Publication of EP1151365A1 publication Critical patent/EP1151365A1/de
Publication of EP1151365A4 publication Critical patent/EP1151365A4/de
Application granted granted Critical
Publication of EP1151365B1 publication Critical patent/EP1151365B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc

Definitions

  • the present invention relates to on chip voltage generation techniques for producing a voltage on chip which is outside the range of a power supply voltage supplied to the chip; and more particularly to the generation of wordline voltages on low power memory devices like flash memory, mask ROM, and SRAM, where the power supply voltage may be less than the read potential required for sensing data in the memory.
  • Integrated circuits have in the past been manufactured in order to work with a power supply voltage of about 5 volts, within a specified range of +/-10%. Of course other power supply voltages have been utilized. There is a current trend for many applications to design integrated circuits to work with lower power supply voltages. Lower voltages generally result in lower power operation for the devices, and are easier to supply using batteries in small devices. For example, one low supply voltage which is emerging as a standard is specified to operate over a range of about 2.7 to 3.6 volts. Other standards are being developed around even lower voltages.
  • On chip circuits however are often designed to operate at higher voltages for some purposes.
  • wordlines which supply a gate potential to memory cells are often designed to operate at a read potential of 4 volts or more.
  • the low power supply voltage is insufficient to supply directly an on chip voltage high enough to drive the wordlines.
  • This problem is dealt with by including charge pumps or other voltage supply boosters on the integrated circuits in order to supply the higher working voltages on chip. See for example United States Patent No. 5,511,026 entitled BOOSTED AND REGULATED GATE POWER SUPPLY WITH REFERENCE TRACKING FOR MULTI-DENSITY AND LOW VOLTAGE SUPPLY MEMORIES.
  • the '026 patent describes an integrated circuit memory having charge pumps configured to supply wordline voltages at a level higher than the supply potential. Furthermore, the '026 patent describes the use of on chip charge pumps to provide a plurality of wordline voltages for multilevel/memory devices, so that a greater working margin is provided between the memory cell states, than would be normally available using a standard supply potential.
  • US 5,796,293 relates to voltage boosting circuits arranged to maintain a boosted voltage during high loading conditions. Each circuit is arranged, when activated, to provide a voltage boost to a signal line in response to a voltage sag.
  • US 5,708,387 relates to booster circuits.
  • the circuit is arranged, when activated, to cause a wordline supply voltage to be raised via a booster capacitor in response to a kick voltage.
  • US 5,034,625 relates to a semiconductor bias circuit comprising two charge pumps connected in parallel for supplying bias voltages.
  • EP 0 810 720 A2 relates to a booster circuit having first and second capacitors and a switch circuit for transferring potentials from the capacitors to boost the potential of a node.
  • an integrated circuit having a supply voltage input adapted to receive a supply voltage within a prespecified range of voltages, and including components on the integrated circuit using an on chip voltage higher than the prespecified range
  • the integrated circuit comprising: voltage boost circuit, coupled to the supply voltage input and operable to receive a boost signal, which boosts the on chip voltage at a node on the integrated circuit in response to a transition of the boost signal, said voltage boost circuit comprising one or more boosting stages, each boosting stage having a capacitor having a first terminal coupled to the node on the integrated circuit, and having a second terminal, and a driving circuit coupled to the second terminal of the capacitor, the voltage boost circuit having in at least one of the boosting stages a first mode which enables the driving circuit in the at least one boosting stage, in response to the transition, to boost the on chip voltage at a first rate of boosting until a first threshold by supplying current at a first rate to the second terminal of the capacitor, and a second mode which enables the driving circuit
  • Embodiments of the present invention provide an on chip voltage generation circuit suitable for use on integrated circuits such as flash memory devices with a low power supply voltage (e.g., 2.7 to 3.6 volts).
  • a low power supply voltage e.g., 2.7 to 3.6 volts
  • it can be characterized as an integrated circuit having a supply voltage input adapted to receive a supply potential within a pre-specified range of voltages, and including components on the integrated circuit that use an on chip voltage higher than the pre-specified range for the supply voltage.
  • a voltage boost circuit is coupled to the supply voltage input and to a boost signal, which boosts the on-chip voltage at a node on the integrated circuit in response to a transition of the boost signal.
  • the voltage boost circuit has a first mode which in response to the transition boosts the on-chip voltage at a first rate of boosting until a first threshold, and a second mode which after reaching the first threshold, boosts the on-chip voltage at a second rate of boosting until a second threshold.
  • the second rate of boosting in the preferred system is slower than the first rate of boosting.
  • a detection circuit is coupled to the node on the integrated circuit which receives the on-chip voltage, and to the voltage boost circuit. The detection circuit signals the voltage boost circuit when the node reaches the first threshold, and signals the voltage boost circuit when the node reaches the second threshold.
  • the first threshold is reached within less than 5 nanoseconds, and more preferably less than 2 nanoseconds of the transition in the boost signal.
  • the detection circuit includes a first detector which supplies a first control signal to the voltage boost circuit within a first time interval of the node reaching the first threshold. During the first time interval, the voltage boost circuit continues boosting at the first rate.
  • a second detector is coupled to the node, and supplies a second control signal to the voltage boost circuit within a second time interval of the node reaching the second threshold. During the second time interval, the voltage boost circuit continues boosting at the second rate, so that the on-chip voltage at the node increases less during the second time interval than during the first time interval.
  • the voltage boost circuit comprises a capacitor, and a driving circuit coupled to one terminal of the capacitor.
  • the driving circuit supplies the transition to the capacitor by supplying current at a first rate during the first mode, and supplying current at a second rate during the second mode.
  • the driving circuit comprises an inverter having an input connected to receive the boost signal and an output coupled to the capacitor.
  • the inverter has first and second power supply terminals, and a current source coupled to one of the first and second power supply terminals having a first mode supplying current at the first rate, and a second mode supplying current at the second rate. In this way, the rate of increase of the voltage on the capacitor can be controlled in the first and second modes to establish the faster and slower rates of pumping.
  • the voltage boosting circuit comprises a first stage and a second stage.
  • the first stage includes a capacitor having a first and second terminals, a diode having an anode coupled to the second terminal capacitor and a cathode coupled to the node on the integrated circuit.
  • a driver is coupled to the first terminal of the capacitor and supplies a first transition signal to the first capacitor.
  • the second stage includes a second capacitor having a first terminal coupled to the node on the integrated circuit.
  • a second driver is coupled to a second terminal of the second capacitor and supplies the transition of the boost signal to the second terminal of the capacitor according to the two modes of operation as discussed above.
  • the circuit also includes a first pre-charge circuit coupled to the anode of the diode in the first stage, and a second pre-charge circuit coupled to the cathode of the diode.
  • circuit includes logic on the chip which is adapted to produce the first transition signal and the transition of the boost signal.
  • Embodiments of the present invention are particularly suited for implementation on integrated circuit memory including an array of memory cells a plurality of wordlines and a plurality of bitlines.
  • a set of wordline drivers is coupled to the plurality of wordlines and utilizes a wordline voltage higher than the pre-specified range of the supply voltage input.
  • Logic detects an event on the integrated circuit, such as an address signal transition, and produces a transition of a boost signal.
  • a voltage boost circuit and detection circuit as described above are included on the chip to manage the boosting of the wordline voltage.
  • the integrated circuit memory comprises an array of ROM cells.
  • the array of memory cells comprises floating gate memory cells, such as flash memory.
  • Fig. 1 provides an overview of a flash memory device incorporating the on chip voltage supply circuit for generating read mode wordline voltages.
  • Fig. 1 illustrates an integrated circuit.
  • the integrated circuit includes a supply voltage input 10 adapted to receive a supply voltage VDD.
  • the supply voltage in one example embodiment is 2.7 to 3.6 volts.
  • a ground input 11 is provided.
  • Other input and output pins are included on the integrated circuit including address inputs 12, control signal inputs such as a chip enable input 13 and an output enable input 14, and data input/output pins 15.
  • the integrated circuit includes a flash memory array 16 including floating gate transistors, an array of ROM cells, such as mask ROM cells, or other memory cells.
  • the array 16 includes a plurality of wordlines represented for example by the arrows 17.
  • the wordlines are driven by a wordline decoder that includes a plurality of sections, including wordline decoder section 0, wordline decoder section 1, wordline decoder section 2, wordline decoder section 3, wordline decoder section 4, wordline decoder section 5, wordline decoder section 6, and wordline decoder section 7 in this example.
  • a column decoder and data input/output circuit 18 is coupled to a plurality of bitlines represented by arrows 19 in the array 16.
  • the column decoder 18 and the wordline decoder 20 are controlled by addresses received from the address inputs 12.
  • the address can be characterized as including row addresses on line 21 and column addresses on line 22 which drive the wordline decoder 20 and the column decoder 18 respectively.
  • a wordline predecoder 23 is included which is coupled to the address line 12.
  • the wordline predecoder generates select control signals SEL(0-7) on line 24 which are supplied respectively to the wordline decoder sections 0-7. In this example, three of the more significant bits of the row address portion of the address on line 12 are used to control the wordline predecoder 23 and select a particular wordline decoder section from the wordline decoder 20.
  • Mode logic 26 is included on the chip.
  • the mode logic 26 receives the chip enable and chip select signals on lines 13 and 14, as well as other signals in order to control the mode of operation of the flash memory.
  • Flash memory devices include a read mode, a program mode, an erase mode, and other modes as suits a particular implementation for program and erase operations.
  • a READ control signal on line 40 is generated by the mode control logic 26.
  • Program and erase mode wordline voltage pumps 28 are included on the chip.
  • a read mode wordline voltage boost circuit 29 is included for the read mode.
  • the read mode wordline voltage boost circuit 29 includes a rapid, multi-stage boost circuit.
  • the output of the read mode wordline boost circuit 29 includes a wordline voltages AVX(0-7) on line 30 for the respective wordline decoder sections.
  • the read mode wordline voltage boost circuit 29 is responsive to the level of AVX 30. Also, the read mode wordline voltage boost circuit 29 is responsive to address transition detection circuit 33. The address transition detection circuit 33 generates a signal on line 35 which indicates the transition of the address.
  • the present invention is applied as shown in Fig. 1 for wordline voltage generation for the read mode of a flash memory device.
  • the invention is particularly suited for flash memory with low power supply voltage in the range for example of 2.7 to 3.6 volts.
  • the invention is also suitable for ROM arrays and for other devices requiring a boosted voltage on a node, such as node 30, on the integrated circuit.
  • Fig. 2 provides a schematic block diagram of a wordline voltage boost circuit according to the present invention.
  • the circuit includes an address transition detection circuit 200 which receives as input the addresses on the integrated circuit, and produces as output an address transition detection signal ATD on line 201, a first address transition detection pulse ATD1ST on line 202, and a second address transition detection pulse ATD2ND on line 203.
  • the second pulse ATD2ND on line 203 is connected to a first stage boost driver and logic block 204 which includes a pump capacitor C1.
  • the pump capacitor is connected to the anode of diode 205.
  • the cathode of diode 205 is connected to the node 206 at which the voltage AVX is generated.
  • a second stage boost driver and logic block 207 is also connected to receive the pulse ATD2ND on line 203 and the address transition detection signal ATD on line 201.
  • the output of the second stage block 207 provides a boost signal on line 208 to a capacitor C2.
  • a second terminal of the capacitor is coupled to the node 206.
  • a first level detector 209 and a second level detector 210 are coupled to the node 206, and generate a first control signal CT1 on line 211 and a second control signal CR1SP on line 212, respectively. These signals are supplied to the second stage block 207 and control the rate of charging of the capacitor C2 in response to the transition of the boost signal on line 208.
  • the wordline voltage generator in Fig. 2 also includes a first pre-charge circuit 215 and a second pre-charge circuit 216.
  • the first and second pre-charge circuits 215, 216 pre-charge the anode of diode 205 and the node 206 to a level near the supply potential in order to facilitate the boosting process.
  • Control signals including the chip enable CEL signal on line 217, an enable ready signal ENRDYB on line 218, and an enable address transition detection signal ENATD on line 219 are supplied to the pre-charge circuits.
  • the pre-charge circuits are responsive to the first address transition pulse ATD I ST on line 202.
  • Fig. 3 is a timing diagram for the address transition detection signals and the level of the AVX signal on node 206.
  • the addresses input to the address transition detection signal are indicated at trace 300.
  • the address transition detection signal on line 201 is indicated on trace 301
  • the first address transition detection pulse ATD1ST is indicated on trace 302
  • the second address transition detection pulse ATD2ND is indicated on trace 303.
  • the level of the voltage AVX at node 206 is indicated at trace 304.
  • the level of the AVX signal on line 304 starts at about the supply potential level of VDD as indicated at point 310.
  • the addresses change at the input of the integrated circuit. This causes an address transition detection signal to transition to the high state at time 311, and to transition to the low state at time 312.
  • the interval of the ATD signal on line 301 between times 311 and 312 is about 20 nanoseconds in this example.
  • the address transition detection circuit 200 produces a first pulse beginning at time 311 and ending at time 313 as indicated by the ATD1ST signal on line 302.
  • the ATD2ND signal transitions to the high state at time 313 and transitions to the low state at time 314 which is close to time 312.
  • the boosting of the node AVX begins with the pre-charging caused by the ATD1ST pulse at time 311. In the trace 304 of Fig. 3, this pre-charging does not reflect any change in the level of the AVX signal. However, if the AVX signal had not been pre-charged to the VDD level prior to the ATD signal, then its level would have been brought up to near VDD.
  • the pre-charge circuit also pre-conditions the capacitor C1 for boosting above the VDD level.
  • the first stage boost pump causes a transition on capacitor C1. This boosts the anode of diode 205, above the level of node 206, and induces an increase in the AVX signal as indicated by the region 315 between times 313 and 312.
  • the second stage boost pump begins a high speed transition of the boost signal 208 in the steep region 316 of the trace 304 just after time 312.
  • voltage level detector B 210 detects that the AVX signal has crossed a first threshold. This causes the second stage boost pump to switch to a slower rate of boosting as indicated by the region 319 in the trace 304 just after time 317.
  • level detector A 209 detects that the voltage level AVX has reached a final threshold and produces the control signal CT1 on line 211. This causes the boosting speed of the second stage pump 207 to stop.
  • the interval between time 312 and 317 of the rapid boosting in this example is less than about 2 nanoseconds, or less than about 5 nanoseconds.
  • the interval for the slower boosting during trace 319 between time 317 and 318 is less than about 10 nanoseconds, or less than about 20 nanoseconds.
  • Figs. 4, 5, 6, 7, 8 and 9 provide a detailed circuit diagram of the voltage boosting circuit in a preferred embodiment of the present invention.
  • Fig. 4 illustrates the first stage pump and the second stage pump.
  • the first stage pump receives the second pulse ATD2ND on line 400.
  • This signal is supplied through inverter 401, inverter 402, inverter 403, and inverter 404 to a first terminal of capacitor C1.
  • the signal on the first terminal of capacitor C1 transitions from a low value to a high value.
  • the second terminal of capacitor C1 is connected to the anode of diode 405.
  • the cathode of diode 405 is connected to node 406 at which the AVX voltage is generated.
  • the second stage of the pump includes the second pulse ATD2ND on line 400 as well as the address transition detection signal ATD on line 410. These signals are supplied as inputs to a NOR gate 411 which supplies the input to an inverter 412. The output of inverter 412 is supplied to the reset input of a set-reset SR latch 413, and as one input to a NOR gate 414. An active low chip enable signal CEB 415 is supplied to the set input of the SR latch 413. The output of the SR latch is a second input of the NOR gate 414. The output of NOR gate 414 drives inverter 416 which in turn drives inverter 417. Inverter 417 supplies inputs to inverter 418 and to inverter 419.
  • the output of inverter 419 is coupled to a first terminal of capacitor 420.
  • the second terminal capacitor 420 is connected to the source of n-channel transistor 421.
  • the drain of n-channel transistor 421 is connected to the supply potential VDD.
  • the gate of transitor 421 receives a control signal ENATD on line 422.
  • the capacitor 420 is connected to the anode of a diode 423.
  • the cathode of diode 423 is connected to the node 406.
  • the control signal on line 422 pulls up the anode of diode 423 to the supply potential level during operation of the pump circuit.
  • the circuit including the inverter 419, the capacitor 420 and the transistor 421 coupled through diode 423 to node 406 operates in a pre-charge capacity.
  • the two mode driver 425 has a power supply terminal which is connected to the current source circuit including transistors 428, 429, 430 and 431.
  • transistors 428 and 429 consist of p-channel transistors having a width of 3 microns and a length of 5 microns.
  • the gate and drain of transistors 428 and 429 are coupled together in respective diode configurations.
  • the n-wells of the transistors are coupled to their respective sources. These transistors provide a weak pull-up to the power supply terminal of driver 425 to prevent it from floating.
  • Transistors 430 and 431 establish the two rates of boosting of the boost signal on line 426.
  • transitor 430 has a width of about one-fifth the width of transistor 431 (e.g. 50 microns) and a length of about 0.5 microns.
  • Transistor 430 is a p-channel transistor having the control signal CT1 coupled to its gate.
  • Transistor 431 is a p-channel transistor having the control signal CT1SP coupled to its gate.
  • Transistor 431 has a width of about five times the width of transistor 430 (e.g. 250 microns) and a length of about 0.5 microns.
  • transistor 431 controlled by CT1SP is much stronger than transistor 430 controlled by CT1.
  • the drains of transistors 430 and 431 are both coupled to the power supply terminal of the driving inverter 425.
  • CT1 and CT1SP are low, a very fast rate of boosting is produced in the boost signal 426 as reflected by the interval 316 between times 312 and 317 in trace 304 of Fig. 3.
  • CT1SP goes high, transistor 431 is turned off and the rate of boosting is reduced substantially, driven only by transistor 430. This is reflected in the slower rate of boosting during the interval 319 between times 317 and 318 in the trace 304 of Fig. 3.
  • the rate of boosting on the signal at node 426 is directly reflected across capacitor C2 on node 406 in a way which is illustrated in Fig. 3 at trace 304.
  • the CT1 and CT1SP control signals at the gates of transistors 430 and 431 are produced by the level detectors illustrated in Figs. 6 and 7.
  • the ATD1ST pulse and the ATD2ND pulse are generated by the circuit illustrated in Fig. 5.
  • Pre-charge circuits shown in Figs. 8 and 9 used for setting up the boosting operation in the circuit are coupled to the boost circuit.
  • the first pre-charge circuit 490 is coupled to the anode of diode 405.
  • a second pre-charge circuit 491 is coupled to node 406 at the cathode of diode 405.
  • the ENRDYB, CEL, CEB, and ENATD control signals are control signal produced with logic of standard design.
  • the ATD1ST and the ATD2ND signals are generated in response to an address transition detect ATD signal on line 500.
  • the ATD signal is produced for example as illustrated in our co-pending United States Patent Application No. 08/751,513 entitled AN ADDRESS TRANSITION DETECTION CIRCUIT filed November 15, 1996, invented by Yin Liu, et al., which was owned at the time of invention and is currently owned by the same assignee.
  • an ATD pulse of about 20 nanoseconds is generated in the preferred system, as shown in Fig. 3. This signal is applied to an one shot circuit consisting of NAND gate 501 and inverter 502.
  • the input the ATD signal line 500 is connected to the input of the inverter 502 and to one input of NAND gate 501.
  • the output of the inverter 502 is connected to the second input of NAND gate 501.
  • the output of the NAND gate 501 is supplied to an inverter 503.
  • the output of the inverter 503 supplies the ATD1ST signal on line 436.
  • the ATD1ST signal is supplied to a second one shot circuit including inverter 504 and NOR gate 505.
  • the ATD1ST signal is connected to the input of inverter 504 which has its output connected to an input of NOR gate 505.
  • the ATD1ST signal is connected to the second input of NOR gate 505.
  • the output of the NOR gate 505 is connected to the set input of an SR latch 506.
  • the output of the NOR gate 505 is connected as one input to NOR gate 507.
  • the second input to NOR gate 507 is the ATD signal on line 500.
  • the output of NOR gate 507 is connected to the reset input of the SR latch 506.
  • the Q output of SR latch 506 is connected to inverter 508, which in turn drives inverter 509.
  • the output of inverter 509 is the ATD2ND signal on line 400.
  • the first level detector illustrated in Fig. 6 generates the CT1SP signal.
  • the second level detector illustrated in Fig. 7 generates the CT1 signal.
  • the CT1SP signal triggers at a lower level of AVX than does the CT1 signal.
  • the detector in Fig. 6 is enabled by the output of the NOR gate 600 which receives as inputs the CEB signal on line 601, the ATD1ST signal on line 436, and the CT1 signal on line 700.
  • the output of the NOR gate 600 is connected through inverter 602 to the gate of transistor 603. Also, the output of inverter 600 is connected to the gate of transistor 604. When the output of NOR gate 600 is high, transistor 604 is turned on and transistor 603 is turned off enabling operation of the level detector circuit.
  • the level detector circuit includes a first current leg which receives as input the AVX signal from node 406. This node is connected to the source and n-well of p-channel transistor 605. The gate and drain of p-channel transistor 605 are connected to the source and n-well of p-channel transistor 606. The gate and drain of transistor 606 are connected to the drain of transistor 604. The source of transistor 604 is connected to the drain and gate of n-channel transistor 607. The source of n-channel transistor 607 is connected to ground.
  • the second current leg of the level detector includes a first node connected to the supply potential VDD.
  • a p-channel transistor 610 and a p-channel transistor 611 have their sources connected to the supply potential.
  • the gate and drain of transistor 610 are connected to the drain of transistor 612.
  • the gate of transistor 611 is connected to the output of inverter 613 which receives as input the SBCTL1 signal on line 614, which is supplied from the output of inverter 602.
  • the source of transistor 612 is connected to ground.
  • the gate of transistor 612 is connected to the gate of transistor 607 in a current mirror fashion.
  • the gate of transistor 612 and the gate of transistor 607 are connected to the drain of transistor 603.
  • the node NISP on the drain of transistor 612 is connected as input to an inverter 615.
  • the output of inverter 615 is connected to the S input of an SR latch 616.
  • the reset input of the SR latch 616 is connected to receive the ATD1ST signal on line 43 6.
  • the Q output of SR latch 616 is connected to inverter 617 which drives inverter 618.
  • the output of inverter 618 is the control signal CT1SP on line 620.
  • Fig. 7 illustrates the level detector for generation of the CT1 signal.
  • This level detector is enabled by the output of a NOR gate 701 which receives the CEB signal on line 601, and the ATD1ST signal on line 436.
  • the output of the NOR gate 701 is connected to the gate of n-channel transistor 702 and to the input of inverter 703.
  • the output of the inverter 703 is connected to the gate of n-channel transistor 704.
  • the drain of transistor 704 is connected to the node 705.
  • the source of transistor 704 is connected to ground.
  • the output of the NOR gate 701 goes high, the circuit is enabled by turning off transistor 704 and turning on transistor 702.
  • the output of the inverter 703 generates the control signal SBCTL which is supplied to the input of inverter 706.
  • a high level on the input of inverter 706 turns on transistor 707.
  • the level detector includes a first current leg connected to the voltage AVX on node 406.
  • Node 406 is connected to the source and n-well of p-channel transistor 708.
  • the gate and drain of transistor 708 are coupled to the source and n-well of p-channel transistor 709.
  • the gate and drain of transistor 709 are connected to the source and n-well of transistor 710 and to the source and n-well of transistor 711.
  • the gate of transistor 710 is connected to receive the control signal CT1 on line 700.
  • the gate and drain of transistor 711 and the drain of transistor 710 are connected to the gate and drain of n-channel transistor 712.
  • the source of transistor 712 is coupled to the gate and drain of a triple well n-channel transistor 713.
  • the isolation well of transistor 713 is connected to the AVX node 406.
  • the p-well and source of transistor 713 are connected to the drain of transistor 702.
  • the source of transistor 702 is connected to the drain and gate of transistor 714 at node 705.
  • the source of transistor 714 is connected to ground.
  • the second current leg of the level detector includes transistor 707 which has its source connected to the supply potential and its drain connected to the drain of transistor 715.
  • the source of transistor 715 is connected to ground.
  • the gate of transistor 715 is connected to node 705 in common with transistor 714.
  • transistor 716 has its source connected to the supply potential and its gate and drain connected to the drain of transistor 715.
  • the circuit works in a manner described above with respect to Fig. 6, except at a higher threshold.
  • the voltage level AVX increases, the current through the current mirror legs increases.
  • the voltage on node NI at the input of inverter 717 reaches the trip point of the inverter.
  • the output of the inverter 717 is connected to the set input of an SR latch 718.
  • the Q output of the SR latch 718 is connected to inverter 719 which in turn drives inverter 720.
  • the output of inverter 720 is the CT1 signal on line 700.
  • the reset input of the SR latch 718 receives the ATD1ST signal on line 436.
  • the transistor 710 operates to turn off when the CT1 signal goes high. This reduces the current flow through the level detector and conserves power for the circuit.
  • the level detection circuits illustrated here consist of the preferred embodiment. There are a variety of level detection circuit approaches which could be utilized according to the present invention. It can be appreciated that as the voltage level of AVX increases rapidly during the first stage of pumping according to the present invention, and that the delay on the order of a fraction of a nanosecond involved in detecting the level shift of AVX using the circuits of Fig. 6 and 7, or other types of level detectors, is significant in accurate cutoff.
  • the ability to tune the timing of these detectors within a nanosecond or less in order to cutoff the boosting level of the AVX signal at a preferred predetermined level is overcome according to the present invention by slowing down the boosting rate as the level reaches the desired cutoff. This way, the relative timing of the CT1SP signal and the reaching of the final level of the boosting is less critical. An overshoot condition is avoided according to the present invention while rapid boosting is allowed.
  • Fig. 8 illustrates the first pre-charge circuit 490. It receives as input signals an enable ATD signal on line 435 and the first ATD pulse ATD1ST on line 436. These signals are supplied as inputs to a NAND gate 437 the output of which drives inverter 438. The output of the inverter 438 is connected to the source and drain of a capacitor-connected transistor 439. The gate of transistor 439 is connected to the gate of n-channel transistor 440. The source of n-channel transistor 440 is connected to line 432 which is coupled to the anode of diode 405, and the drain of transistor 440 is connected to the supply potential VDD.
  • the gate of transistor 440 is biased by a circuit including p-channel transistor 441 which has its source connected to the supply potential VDD, its gate connected to the control signal ENRDYB on line 442, and its drain connected to the anode of a diode 443.
  • the cathode of diode 443 is connected to the gate of transistor 440.
  • a transistor 444 has its drain connected to the gate of transistor 440 and its source connected to ground.
  • the gate of transistor 444 is connected to the control signal CEL on line 445.
  • a transistor 446 has its drain connected to the gate of transistor 440 and its source connected to ground.
  • the gate of transistor 446 is connected to the control signal ENRDYB on line 442.
  • the gate of transistor 440 in response to a low signal at the ENRDYB terminal on line 442 is coupled to a level which is determined by the voltage drop across transistor 441 and diode 443 below the supply potential.
  • the control signal CEL on line 445 goes high, the node is connected to ground.
  • the control signal ENRDYB goes high, the node is connected to ground through transistor 446.
  • the pre-charge circuit includes transistor 450 which has its gate and drain coupled to the supply potential and its source connected across line 430 to the anode of diode 405.
  • This diode connected transistor 450 maintains the level of the node at a threshold drop below VDD as a starting point.
  • the gate of transistor 440 is boosted to compensate for the threshold drop across transistor 440 and 450 to pull the anode of diode 405 up to the VDD level.
  • the second pre-charge circuit is shown in Fig. 9, and is similar to the first. It receives its inputs ENATD signal on line 435 and the ATD1ST signal on line 436. These signals are supplied as inputs to a NAND gate 457 which drives inverter 458.
  • the inverter 458 is connected to the source and drain of a capacitor connected transistor 459.
  • the gate transistor 459 is connected to the gate of transistor 460.
  • the gate of transistor 460 is also biased by the circuit including the p-channel transistor 461 having its source connected to the supply potential VDD and its drain connected through diode 462 to the gate transistor 460.
  • Transistors 463 and 464 are n-channel transistors having their drains connected to the gate of transistor 460 and their sources connected to ground.
  • the gate of transistor 463 receives the CEL control signal on line 445.
  • the gate of transistor 461 and the gate of transistor 464 receive as input the control signal ENRDYB on line 442.
  • the second pre-charge circuit also includes transistor 470 which has its gate and drain connected to the supply potential VDD and its source connected on line 431 to node 406.
  • transistor sizes and capacitor parameters set forth above are representative of a particular implementation designed according to the needs of a specific semiconductor device. Obviously variations in the components and relative sizes of these transistors may be appropriate for any given circumstance. However they are given as a basis for understanding the operation of the example circuit in more detail.
  • a two mode voltage boosting circuit suitable for use in read operations for flash memory and other memory devices has been disclosed.
  • the circuit is also suitable for other environments where a rapid boosting with a precise cutoff level is desired.
  • the precise cutoff level is particularly important for multi-level cells which rely on very tight margin on the wordline voltages for reading the various levels of the cell.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Read Only Memory (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)

Claims (14)

  1. Integrierter Schaltkreis mit einem Eingang (10) für eine Versorgungsspannung, welcher dafür ausgelegt ist, eine Versorgungsspannung (VDD) innerhalb eines vorher spezifizierten Spannungsbereiches anzunehmen, und mit Bauteilen (16) auf dem integrierten Schaltkreis, welche eine On-Chip-Spannung (AVX) verwenden, die höher liegt als der vorher spezifizierte Bereich, wobei der integrierte Schaltkreis aufweist:
    einen Spannungsverstärkungsschaltkreis, der mit dem Eingang der Versorgungsspannung verbunden und derart betreibbar ist, daß er ein Verstärkungssignal empfängt, welches die On-Chip-Spannung an einem Knoten (206) auf dem integrierten Schaltkreis in Reaktion auf einen Übergang des Verstärkungssignals erhöht, wobei der Spannungsverstärkungsschaltkreis aufweist:
    eine oder mehrere Verstärkungsstufen, wobei jede Verstärkungsstufe einen Kondensator (C1; C2) hat, der mit einem ersten Anschluß mit dem Knoten auf dem integrierten Schaltkreis verbunden ist, und der einen zweiten Anschluß aufweist sowie einen Treiberschaltkreis (204; 207), welcher mit dem zweiten Anschluß des Kondensators verbunden ist, wobei der Spannungsverstärkungsschaltkreis in zumindest einer der Verstärkungsstufen aufweist:
    eine erste Betriebsart, welche es dem Treiberschaltkreis (207) in der zumindest einen Verstärkungsstufe ermöglicht, in Reaktion auf den Übergang die On-Chip-Spannung mit einer ersten Steigerungsrate bis auf einen Schwellwert zu verstärken, indem ein Strom mit einer ersten Steigerungsrate dem zweiten Anschluß des Kondensators (C2) zugeführt wird, und
    eine zweite Betriebsart, welche es dem Treiberschaltkreis (207) in der zumindest einen Verstärkungsstufe ermöglicht die On-Chip-Spannung mit einer zweiten Steigerungsrate über den ersten Schwellwert bis zu einem zweiten Schwellwert zu verstärken, indem ein Strom mit einer zweiten Steigerungsrate dem zweiten Anschluß des Kondensators (C2) zugeführt wird, wobei die zweite Steigerungsrate geringer ist als die erste Steigerungsrate, und
    wobei zumindest eine Verstärkungsstufe derart ausgelegt ist, daß sie die Verstärkung nach dem zweiten Schwellwert stoppt, und
    einen Erfassungsschaltkreis (209, 210), der mit dem Knoten auf dem integrierten Schaltkreis und dem Spannungsverstärkungsschaltkreis verbunden ist, welcher dem Spannungsverstärkungsschaltkreis anzeigt (CT1SP), wenn der Knoten den ersten Schwellwert erreicht und dem Spannungsverstärkungsschaltkreis anzeigt (CT1), wenn der Knoten den zweiten Schwellwert erreicht.
  2. Integrierter Schaltkreis nach Anspruch 1, wobei der Erfassungsschaltkreis aufweist:
    einen ersten Detektor (209), der mit dem Knoten verbunden ist, welcher dem Spannungsverstärkungsschaltkreis innerhalb eines ersten Zeitintervalls, innerhalb dessen der Knoten den ersten Schwellwert erreicht, ein erstes Steuersignal zuführt, wobei der Spannungsverstärkungsschaltkreis während dieses ersten Zeitintervalls mit der Verstärkung um die erste Steigerungsrate fortfährt, und
    einen zweiten Detektor (210), der mit dem Knoten verbunden ist und welcher dem Spannungsverstärkungsschaltkreis innerhalb eines zweiten Zeitintervalls, während dessen der Knoten den zweiten Schwellwert erreicht, ein zweites Steuersignal zuführt, wobei während des zweiten Zeitintervalls der Spannungsverstärkungsschaltkreis mit der zweiten Steigerungsrate weiter verstärkt, so daß die On-Chip-Spannung an dem Knoten während des zweiten Zeitintervalls langsamer ansteigt als während des ersten Zeitintervalls.
  3. Integrierter Schaltkreis nach Anspruch 1, wobei der Treiberschaltkreis in der zumindest einen Verstärkungsstufe aufweist:
    einen Invertierer (425), der einen Eingang hat, welcher so angeschlossen ist, daß er das Verstärkungssignal empfängt, und einen Ausgang hat, der mit dem zweiten Anschluß des Kondensators verbunden ist, und der erste und zweite Stromversorgungsanschlüsse hat, und
    eine Stromquelle (428-431), die mit einem der ersten und zweiten Stromversorgungsanschlüssen verbunden ist und die einen Versorgungsstrom mit der ersten Steigerungsrate in einem ersten Betriebszustand und einen Zufuhrstrom mit der zweiten Steigerungsrate in einem zweiten Betriebszustand hat.
  4. Integrierter Schaltkreis nach Anspruch 1, wobei der Spannungsverstärkungsschaltkreis aufweist:
    eine erste Verstärkungsstufe einschließlich eines ersten Kondensators (C1), der einen ersten Anschluß und einen zweiten Anschluß hat, sowie eine Diode (205), welche eine Anode hat, die mit dem zweiten Anschluß des Kondensators verbunden ist und eine Kathode hat, die mit dem Knoten auf dem integrierten Schaltkreis verbunden ist, und mit einem Treiberschaltkreis (204), welcher mit dem ersten Anschluß des Kondensators verbunden ist und welcher dem ersten Kondensator ein erstes Übergangssignal zuführt, und
    wobei die zumindest eine Verstärkungsstufe eine zweite Verstärkungsstufe mit einem zweiten Kondensator (C2) aufweist, welcher einen ersten Anschluß hat, der mit dem Knoten auf dem integrierten Schaltkreis verbunden ist und einen zweiten Anschluß hat, wobei ein zweiter Treiberschaltkreis (207) mit dem zweiten Anschluß des zweiten Kondensators verbunden ist, und wobei der zweite Treiberschaltkreis den Übergang des Verstärkungssignals dem zweiten Anschluß des zweiten Kondensators zuführt, indem während des ersten Betriebszustandes ein Strom mit einer ersten Steigerungsrate zugeführt wird und während des zweiten Betriebszustandes ein Strom mit einer zweiten Steigerungsrate zugeführt wird.
  5. Integrierter Schaltkreis nach Anspruch 4, mit einem ersten Vorladeschaltkreis (215), der mit der Anode der Diode verbunden ist und einem zweiten Vorladeschaltkreis (216), der mit dem Knoten verbunden ist, welcher den ersten Anschluß des zweiten Kondensators und den Knoten vor dem ersten Übergangssignal auf eine Anfangsspannung vorlädt.
  6. Integrierter Schaltkreis nach Anspruch 4, einschließlich einer Logik (200), welche auf ein Ereignis reagiert, um das erste Übergangssignal und den Übergang des Verstärkungssignals zu erzeugen.
  7. Integrierter Schaltkreis nach Anspruch 1, wobei der Spannungsverstärkungsschaltkreis in weniger als 5 Nanosekunden nach dem Übergang des Verstärkungssignals den ersten Schwellwert erreicht.
  8. Integrierter Schaltkreis nach Anspruch 1, wobei der Spannungsverstärkungsschaltkreis in etwa 2 Nanosekunden oder weniger nach dem Übergang des Verstärkungssignals den ersten Schwellwert erreicht.
  9. Integrierter Schaltkreis nach Anspruch 1, mit:
    einem Array (16) von Speicherzellen,
    einer Mehrzahl von Wortleitungen (17), die mit Reihen von Speicherzellen in dem Array verbunden sind,
    einer Mehrzahl von Bitleitungen (19), die mit Spalten von Speicherzellen in dem Array verbunden sind, einem Satz von Wortleitungstreibern (20), die mit der Mehrzahl von Wortleitungen verbunden sind, wobei die Wortleitungstreiber auf ausgewählte Wortleitungen aus dem Knoten des integrierten Schaltkreises eine Wortleitungsspannung anlegen, wobei die Wortleitungsspannung höher als der zuvor spezifizierte Bereich der Versorgungsspannung ist, und
    einer Logik (33), welche ein Ereignis auf dem integrierten Schaltkreis erfaßt und den Übergang des Verstärkungssignals erzeugt.
  10. Integrierter Schaltkreis nach Anspruch 9, einschließlich zumindest eines Adreßeingangs (12), und wobei die Logik einen Schaltkreis aufweist, welcher den Übergang in dem Verstärkungssignal in Reaktion auf einen Übergang an dem zumindest einen Adreßeingang erzeugt.
  11. Integrierter Schaltkreis nach Anspruch 9, einschließlich zumindest eines Adreßeingangs (12), und wobei die Logik einen Schaltkreis aufweist, welcher den Übergang des ersten Übergangssignals in Reaktion auf einen Übergang an zumindest einem Adreßeingang erzeugt und den Übergang in dem Verstärkungssignal nach dem ersten Übergangssignal.
  12. Integrierter Schaltkreis nach Anspruch 9, einschließlich zumindest eines Adreßeingangs (12), und wobei die Logik einen Schaltkreis aufweist, welcher ein Vorladesignal, das erste Übergangssignal nach dem Vorladesignal und den Übergang in dem Verstärkungssignal nach dem ersten Übergangssignal in Reaktion auf einen Übergang an dem zumindest einen Adreßeingang erzeugt, und wobei die ersten und zweiten Voriadeschaltkreise auf das Vorladesignal ansprechen.
  13. Integrierter Schaltkreis nach Anspruch 9, wobei das Array von Speicherzellen ROM-Zellen aufweist.
  14. Integrierter Schaltkreis nach Anspruch 9, wobei das Array von Speicherzellen Speicherzellen mit erdfreiem Gate aufweist.
EP98960305A 1998-11-18 1998-11-18 Schnelle spannungserzeugung auf dem chip für integrierte schaltungen niedriger leistung Expired - Lifetime EP1151365B1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1998/024766 WO2000029919A1 (en) 1998-11-18 1998-11-18 Rapid on chip voltage generation for low power integrated circuits

Publications (3)

Publication Number Publication Date
EP1151365A1 EP1151365A1 (de) 2001-11-07
EP1151365A4 EP1151365A4 (de) 2002-01-30
EP1151365B1 true EP1151365B1 (de) 2004-05-12

Family

ID=22268334

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98960305A Expired - Lifetime EP1151365B1 (de) 1998-11-18 1998-11-18 Schnelle spannungserzeugung auf dem chip für integrierte schaltungen niedriger leistung

Country Status (6)

Country Link
EP (1) EP1151365B1 (de)
JP (1) JP4394835B2 (de)
CN (1) CN1148621C (de)
DE (1) DE69823888T2 (de)
HK (1) HK1042954A1 (de)
WO (1) WO2000029919A1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6646950B2 (en) * 2001-04-30 2003-11-11 Fujitsu Limited High speed decoder for flash memory
WO2004109711A1 (ja) * 2003-06-05 2004-12-16 Fujitsu Limited 冗長メモリのブースタ回路を有する半導体メモリ
CN1323434C (zh) * 2003-09-02 2007-06-27 台湾积体电路制造股份有限公司 整合闪存与高电压组件的制造方法
US7466620B2 (en) * 2006-01-04 2008-12-16 Baker Mohammad System and method for low power wordline logic for a memory
US7529117B2 (en) * 2007-03-07 2009-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Design solutions for integrated circuits with triple gate oxides
CN101620886B (zh) * 2008-07-02 2012-01-25 中芯国际集成电路制造(上海)有限公司 用于闪存器件的字线增压器
JP5808937B2 (ja) * 2011-04-20 2015-11-10 ラピスセミコンダクタ株式会社 半導体メモリの内部電源電圧生成回路及び内部電源電圧生成方法
CN108958639B (zh) * 2017-05-19 2021-07-06 华邦电子股份有限公司 快闪存储器存储装置
JP2021149999A (ja) 2020-03-23 2021-09-27 キオクシア株式会社 半導体記憶装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR910004737B1 (ko) * 1988-12-19 1991-07-10 삼성전자 주식회사 백바이어스전압 발생회로
KR0172337B1 (ko) * 1995-11-13 1999-03-30 김광호 반도체 메모리장치의 내부승압전원 발생회로
US5708387A (en) * 1995-11-17 1998-01-13 Advanced Micro Devices, Inc. Fast 3-state booster-circuit
JPH09320267A (ja) * 1996-05-28 1997-12-12 Oki Micro Design Miyazaki:Kk 昇圧回路の駆動方法および昇圧回路

Also Published As

Publication number Publication date
HK1042954A1 (en) 2002-08-30
DE69823888D1 (de) 2004-06-17
JP4394835B2 (ja) 2010-01-06
WO2000029919A1 (en) 2000-05-25
JP2003517719A (ja) 2003-05-27
CN1327552A (zh) 2001-12-19
EP1151365A4 (de) 2002-01-30
EP1151365A1 (de) 2001-11-07
CN1148621C (zh) 2004-05-05
DE69823888T2 (de) 2004-10-21

Similar Documents

Publication Publication Date Title
US6753720B2 (en) Internal high voltage generation circuit capable of stably generating internal high voltage and circuit element therefor
US6255900B1 (en) Rapid on chip voltage generation for low power integrated circuits
US7088620B2 (en) Nonvolatile semiconductor memory device
JP3346273B2 (ja) ブースト回路および半導体記憶装置
US5699303A (en) Semiconductor memory device having controllable supplying capability of internal voltage
KR100471185B1 (ko) 내부 공급 전압의 파워-업 기울기를 제어하기 위한 내부전압 변환기 구조
US5696731A (en) Semiconductor memory device using internal voltage obtained by boosting supply voltage
JPH07122998B2 (ja) 半導体メモリ素子の高電圧発生回路
US6002630A (en) On chip voltage generation for low power integrated circuits
US20060077745A1 (en) Semiconductor device and method for boosting word line
EP1151365B1 (de) Schnelle spannungserzeugung auf dem chip für integrierte schaltungen niedriger leistung
KR100309602B1 (ko) 전위검출회로에서의전력소비를감소시키는반도체장치
KR100296005B1 (ko) 반도체장치
US5631867A (en) Semiconductor storage device requiring short time for program voltage to rise
US5642313A (en) Voltage booster circuit for a memory device
US6469942B1 (en) System for word line boosting
US5703814A (en) Semiconductor memory device having dual boosting circuits to reduce energy required to supply boosting voltages
JPH06208794A (ja) 立上げ時に定状態であるメモリセル
JP4808988B2 (ja) チャージポンピング効率を維持する高電圧発生回路
US5696461A (en) Power-on reset circuit
US6215332B1 (en) Semiconductor integrated circuit having power supply voltage detecting function
WO1999027537A1 (en) On chip voltage generation for low power integrated circuits
JP2001160295A (ja) 半導体集積回路
KR100585144B1 (ko) 차아지 펌핑 효율을 유지하는 승압 전압 발생 회로
US6515932B1 (en) Memory circuit

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20010601

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB IT

A4 Supplementary search report drawn up and despatched

Effective date: 20011217

AK Designated contracting states

Kind code of ref document: A4

Designated state(s): DE FR GB IT

RIC1 Information provided on ipc code assigned before grant

Free format text: 7G 05F 1/10 A, 7G 05F 3/02 B, 7H 01L 27/02 B, 7G 11C 5/14 B, 7G 05F 3/20 B, 7G 05F 1/46 B

17Q First examination report despatched

Effective date: 20020423

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: MACRONIX INTERNATIONAL CO., LTD.

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB IT

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REF Corresponds to:

Ref document number: 69823888

Country of ref document: DE

Date of ref document: 20040617

Kind code of ref document: P

ET Fr: translation filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20050215

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 18

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 19

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 20

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20171003

Year of fee payment: 20

Ref country code: FR

Payment date: 20171002

Year of fee payment: 20

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: IT

Payment date: 20171122

Year of fee payment: 20

Ref country code: GB

Payment date: 20171002

Year of fee payment: 20

REG Reference to a national code

Ref country code: DE

Ref legal event code: R071

Ref document number: 69823888

Country of ref document: DE

REG Reference to a national code

Ref country code: GB

Ref legal event code: PE20

Expiry date: 20181117

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF EXPIRATION OF PROTECTION

Effective date: 20181117