EP1030311B1 - Decoder-Anschlussanordnung für Speicherchips mit langen Bitleitungen - Google Patents
Decoder-Anschlussanordnung für Speicherchips mit langen Bitleitungen Download PDFInfo
- Publication number
- EP1030311B1 EP1030311B1 EP00103532A EP00103532A EP1030311B1 EP 1030311 B1 EP1030311 B1 EP 1030311B1 EP 00103532 A EP00103532 A EP 00103532A EP 00103532 A EP00103532 A EP 00103532A EP 1030311 B1 EP1030311 B1 EP 1030311B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- decoder
- region
- memory cell
- cell array
- bit lines
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000015654 memory Effects 0.000 title claims description 22
- 238000001465 metallisation Methods 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
-
- A—HUMAN NECESSITIES
- A63—SPORTS; GAMES; AMUSEMENTS
- A63G—MERRY-GO-ROUNDS; SWINGS; ROCKING-HORSES; CHUTES; SWITCHBACKS; SIMILAR DEVICES FOR PUBLIC AMUSEMENT
- A63G9/00—Swings
- A63G9/04—Swings with moving supporting-points
-
- A—HUMAN NECESSITIES
- A63—SPORTS; GAMES; AMUSEMENTS
- A63G—MERRY-GO-ROUNDS; SWINGS; ROCKING-HORSES; CHUTES; SWITCHBACKS; SIMILAR DEVICES FOR PUBLIC AMUSEMENT
- A63G9/00—Swings
- A63G9/02—Swings with two suspensory axles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
Definitions
- the line decoders is, parallel to the bit lines at the edge of a memory cell array provided and only at their respective Ends via vias to a power grid connected.
- FIG. 2 shows that word lines extend in a memory cell array 1 WL in the y direction, while bit lines BL in the x direction are arranged. To simplify the drawing only one word line WL or two bit lines BL are shown.
- Parallel to the bit lines BL is at the edge of the memory cell array 1 in the x-direction, a decoder 2 provided in which the individual word lines WL and their Decoders are extremely close to each other.
- a first metallization level forming decoder is isolated through a silicon dioxide layer, in a second metallization plane a series of parallel ones Power supply lines 3 provided. These power supply lines 3 are with the decoders only at the edge of the Decoder area 3 via vias 4, 5 by the silicon dioxide layer extend, electrically connected. It is not possible, such vias 4, 5 also in Course of the power supply lines 3, approximately in the middle, which is based on the fact that Metalltechnischsebene the individual decoder or their word lines close together.
- Existing decoder terminal arrangements So have vias 4, 5 only at the edges of the decoder areas 2, which are connected to a Memory cell array 1 adjacent.
- the two Metallmaschinesebenen not as before only at both ends of the decoder area, but at least one another time, for example, connected to each other in the middle.
- this additional Connection of the two metallization levels is in advantageously uses the zone of the decoder area, which corresponds to the bit line twist area in the memory cell array.
- bit line twist for the bit lines whose coupling capacity is practically halved due to the twist so the bitlines run longer than without a twist can be.
- the power supply lines it is possible, the power supply lines to reduce to about a quarter of its previous thickness or the length of the decoder area practically too double, without a reduction in switching speed through higher capacities or RC constants to accept have to.
- FIG. 2 has already been explained at the beginning.
- Fig. 1 will be for corresponding parts, the same reference numerals as used in Fig. 2.
- bit lines extending in the x direction BL (not shown in detail) in a bit line twist area 8 each through a twist. That's hot, two neighbors Bit lines BL cross each other here, so that in the Memory cell array 1 to the left of the bit line twist area 8 a first bit line, which in Fig. 1 in the y direction above from a second bitline, this first bitline in the part to the right of the bit line twist area of the memory cell array 1 below the second bit line is guided here now in the y direction above the first Bit line is.
- This bit line twist is known practically due to the electrical symmetry Halving the coupling capacity achieved. By this halving The coupling capacity makes it possible to virtually anyone omit second sense amplifier.
- decoder area 2 it now exists below the bitline twist area 8, a dummy area 7, in which Due to the bit line twist in area 8 no decoder needed become. According to the invention this area 7 is now for additional vias 6 between the power supply lines 3 having upper metallization level and the lower metallization level of the decoder exploited.
- the width of the bit line twist area 8 is, for example about 2.4 microns, while the memory cell array 1 left and right of this bit line twist area 8 a Width of about 200 microns has. That is, the entire memory cell array 1 has a width of just over 400 microns.
- a Width of about 200 microns has. That is, the entire memory cell array 1 has a width of just over 400 microns.
- the dummy area 7 is thus like the bit line twist area 8 also about 2.4 microns wide. This width is perfect sufficient for the desired vias between the two metallization levels. Through this additional Vias 6 in the dummy area 7 becomes a low-resistance connection between the power supply lines 3 and the decoder in the decoder 2 created.
- the two metallization levels not as before only at the two ends of the Area 2 contacted each other. Rather, such will be one Contacting via the plated-through holes 6 also in the Center of the area 2 made.
- additional vias provide, if appropriate further dummy areas 7 are used.
- the invention is not based on line decoders, that is, in the row direction limited, as shown in FIG. 1. Much more is an application of the invention also in the column direction possible.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
Description
- in einer ersten Richtung verlaufenden langen Bitleitungen,
- die Bitleitungen in einem Speicherzellenfeld kreuzenden und in einer zweiten Richtung verlaufenden Wortleitungen,
- Wortleitungs-Decodern, die in einem Decoderbereich liegen und eine erste Metallisierungsebene bilden, wobei der Decoderbereich an einen in der ersten Richtung verlaufenden Rand des Speicherzellenfeldes angrenzt, und
- Versorgungsleitungen für die Decoder, die im Decoderbereich in einer über der ersten Metallisierungsebene liegenden zweiten Metallisierungsebene geführt sind, wobei zwischen den beiden Metallisierungsebenen jeweils durch Kontaktierungen an Seitenrändern des Decoderbereiches vorgesehen sind, wobei im Speicherzellenfeld die Bitleitungen in einem Twist-Bereich einen Twist bilden. Eine solche Anordnung ist z.B. aus US-A-5 091 887 bekannt.
- Fig. 1
- eine schematische Draufsicht auf eine Decoder-Anschlußanordnung nach einem Ausführungsbeispiel der Erfindung und
- Fig. 2
- eine schematische Draufsicht auf eine bestehende Decoder-Anschlußanordnung.
Claims (4)
- Decoder-Anschlußanordnung für Speicherchips mit:in einer ersten Richtung (x) verlaufenden langen Bitleitungen (BL),die Bitleitungen (BL) in einem Speicherzellenfeld (1) kreuzenden und in einer zweiten Richtung (y) verlaufenden Wortleitungen (WL),Wortleitungs-Decodern, die in einem Decoderbereich (2) liegen und eine erste Metallisierungsebene bilden, wobei der Decoderbereich (2) an einem in der ersten Richtung (x) verlaufenden Rand des Speicherzellenfeldes (1) angrenzt, undVersorgungsleitungen (3) für die Decoder, die im Decoderbereich (2) in einer über der ersten Metallisierungsebene liegenden zweiten Metallisierungsebene geführt sind, wobei zwischen den beiden Metallisierungsebenen jeweils Durchkontaktierungen (4, 5) an Seitenrändern des Decoderbereiches (2) vorgesehen sind, wobei im Speicherzellenfeld (1) die Bitleitungen (BL) in einem Bitleitung-Twist-Bereich (8) einen Twist bilden,in der an den Bitleitung-Twist-Bereich (8) angrenzenden Zone des Decoderbereiches (2) zusätzliche Durchkontaktierungen (6) zwischen den beiden Metallisierungsebenen vorgesehen sind.
- Decoder-Anschlußanordnung nach Anspruch 1,
dadurch gekennzeichnet, daß die zusätzlichen Durchkontaktierungen (6) in einem Dummy-Bereich (7) des Decoderbereiches (2) liegen. - Decoder-Anschlußanordnung nach Anspruch 1 oder 2,
dadurch gekennzeichnet, daß der Bitleitung-Twist-Bereich eine Breite von etwa 2,4 µm hat. - Decoder-Anschlußanordnung nach einem der Ansprüche 1 bis 3,
dadurch gekennzeichnet, daß die Breite des Speicherzellenfeldes (1) in der ersten Richtung etwa 400 µm beträgt.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19907176A DE19907176A1 (de) | 1999-02-19 | 1999-02-19 | Decoder-Anschlußanordnung für Speicherchips mit langen Bitleitungen |
DE19907176 | 1999-02-19 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1030311A1 EP1030311A1 (de) | 2000-08-23 |
EP1030311B1 true EP1030311B1 (de) | 2005-02-02 |
Family
ID=7898172
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP00103532A Expired - Lifetime EP1030311B1 (de) | 1999-02-19 | 2000-02-18 | Decoder-Anschlussanordnung für Speicherchips mit langen Bitleitungen |
Country Status (6)
Country | Link |
---|---|
US (1) | US6205044B1 (de) |
EP (1) | EP1030311B1 (de) |
JP (1) | JP3663329B2 (de) |
KR (1) | KR100366273B1 (de) |
DE (2) | DE19907176A1 (de) |
TW (1) | TW459243B (de) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6947324B1 (en) | 2000-06-28 | 2005-09-20 | Marvell International Ltd. | Logic process DRAM |
US7184290B1 (en) | 2000-06-28 | 2007-02-27 | Marvell International Ltd. | Logic process DRAM |
US6570781B1 (en) | 2000-06-28 | 2003-05-27 | Marvell International Ltd. | Logic process DRAM |
US6717839B1 (en) | 2003-03-31 | 2004-04-06 | Ramtron International Corporation | Bit-line shielding method for ferroelectric memories |
KR100541818B1 (ko) * | 2003-12-18 | 2006-01-10 | 삼성전자주식회사 | 반도체 메모리 장치의 라인 배치구조 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0713858B2 (ja) * | 1988-08-30 | 1995-02-15 | 三菱電機株式会社 | 半導体記憶装置 |
JPH02302986A (ja) * | 1989-05-16 | 1990-12-14 | Mitsubishi Electric Corp | ダイナミック型半導体記憶装置 |
US5311477A (en) * | 1991-07-17 | 1994-05-10 | Sgs-Thomson Microelectronics, Inc. | Integrated circuit memory device having flash clear |
US5251168A (en) * | 1991-07-31 | 1993-10-05 | Texas Instruments Incorporated | Boundary cells for improving retention time in memory devices |
JP3440335B2 (ja) * | 1993-08-18 | 2003-08-25 | 日本テキサス・インスツルメンツ株式会社 | 半導体メモリ装置 |
DE69526006T2 (de) * | 1994-08-15 | 2003-01-02 | International Business Machines Corp., Armonk | Anordnung mit einem einzigen Verdrillungsgebiet und Verfahren für gepaarte linienförmige Leiter in integrierten Schaltungen |
US5821592A (en) * | 1997-06-30 | 1998-10-13 | Siemens Aktiengesellschaft | Dynamic random access memory arrays and methods therefor |
US5864496A (en) * | 1997-09-29 | 1999-01-26 | Siemens Aktiengesellschaft | High density semiconductor memory having diagonal bit lines and dual word lines |
US6069815A (en) * | 1997-12-18 | 2000-05-30 | Siemens Aktiengesellschaft | Semiconductor memory having hierarchical bit line and/or word line architecture |
US6034879A (en) * | 1998-02-19 | 2000-03-07 | University Of Pittsburgh | Twisted line techniques for multi-gigabit dynamic random access memories |
-
1999
- 1999-02-19 DE DE19907176A patent/DE19907176A1/de not_active Ceased
-
2000
- 2000-02-16 JP JP2000038344A patent/JP3663329B2/ja not_active Expired - Fee Related
- 2000-02-18 EP EP00103532A patent/EP1030311B1/de not_active Expired - Lifetime
- 2000-02-18 DE DE50009385T patent/DE50009385D1/de not_active Expired - Fee Related
- 2000-02-18 TW TW089102846A patent/TW459243B/zh active
- 2000-02-18 KR KR1020000007782A patent/KR100366273B1/ko not_active IP Right Cessation
- 2000-02-22 US US09/510,641 patent/US6205044B1/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR20000062568A (ko) | 2000-10-25 |
TW459243B (en) | 2001-10-11 |
JP3663329B2 (ja) | 2005-06-22 |
DE19907176A1 (de) | 2000-08-31 |
JP2000243933A (ja) | 2000-09-08 |
KR100366273B1 (ko) | 2002-12-31 |
DE50009385D1 (de) | 2005-03-10 |
EP1030311A1 (de) | 2000-08-23 |
US6205044B1 (en) | 2001-03-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE69526006T2 (de) | Anordnung mit einem einzigen Verdrillungsgebiet und Verfahren für gepaarte linienförmige Leiter in integrierten Schaltungen | |
DE4433695C2 (de) | Dynamische Halbleiterspeichervorrichtung | |
EP1184871B1 (de) | MRAM-Anordnung | |
DE602005002546T2 (de) | Verbessertes layout einer sram-speicherzelle | |
DE3937068C2 (de) | Dynamische Halbleiterspeicheranordnung | |
DE19625169A1 (de) | Hierarchische Wortleitungsstruktur für Halbleiterspeichervorrichtung | |
DE102005056427A1 (de) | Speicherzellenfeld | |
DE10065703A1 (de) | Säulentransistor in einer Halbleitervorrichtung | |
DE10255203B3 (de) | Dynamische Speicherzelle mit zwei vertikalen Auswahltransistoren | |
DE69024167T2 (de) | Halbleiterspeicheranordnung | |
EP1030311B1 (de) | Decoder-Anschlussanordnung für Speicherchips mit langen Bitleitungen | |
DE69614947T2 (de) | Halbleiterspeicheranordnung mit einer Schaltungsanordnungstruktur für hohe Geschwindigkeit | |
DE4126050C2 (de) | Anordnung von Wortleitungstreiberstufen in einer Halbleiterspeicheranordnung | |
DE19907921C1 (de) | Halbleiterspeicheranordnung mit Dummy-Bauelementen auf durchgehenden Diffusionsgebieten | |
DE102006035076B4 (de) | Integrierter Halbleiterspeicher und Verfahren zum Betreiben eines integrierten Halbleiterspeichers | |
DE102004062451A1 (de) | Halbleiterspeicherbauelement mit verschränkten Leitungen, Leitungsentwurfsstruktur und Leitungsentwurfsverfahren | |
EP1032043A2 (de) | Halbleiterspeicheranordnung mit Bitleitungs-Twist | |
DE69020237T2 (de) | Halbleiterspeicheranordnung mit einer Bitleitungsstruktur mit niedrigem Geräusch. | |
DE60118833T2 (de) | Halbleiter-Speicher mit unterteilter Wortleitungstruktur | |
DE10101630B4 (de) | Halbleiterspeicherbauelement mit Eingabe-/Ausgabeleitungsstruktur | |
DE10304626A1 (de) | Halbleiter-Speichervorrichtung | |
EP0199231B1 (de) | In CMOS-Technik aufgebaute Zelle | |
DE10231206A1 (de) | Halbleitervorrichtung | |
DE19918932A1 (de) | Halbleiterspeichervorrichtung | |
DE69119252T2 (de) | Halbleiterspeicheranordnung |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE |
|
AX | Request for extension of the european patent |
Free format text: AL;LT;LV;MK;RO;SI |
|
17P | Request for examination filed |
Effective date: 20000918 |
|
AKX | Designation fees paid | ||
RBV | Designated contracting states (corrected) |
Designated state(s): DE FR GB IE IT |
|
GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: INFINEON TECHNOLOGIES AG |
|
GRAS | Grant fee paid |
Free format text: ORIGINAL CODE: EPIDOSNIGR3 |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): DE FR GB IE IT |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: FG4D Free format text: NOT ENGLISH |
|
REG | Reference to a national code |
Ref country code: IE Ref legal event code: FG4D Free format text: GERMAN |
|
REF | Corresponds to: |
Ref document number: 50009385 Country of ref document: DE Date of ref document: 20050310 Kind code of ref document: P |
|
GBT | Gb: translation of ep patent filed (gb section 77(6)(a)/1977) |
Effective date: 20050418 |
|
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
ET | Fr: translation filed | ||
26N | No opposition filed |
Effective date: 20051103 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 20080220 Year of fee payment: 9 Ref country code: IE Payment date: 20080220 Year of fee payment: 9 Ref country code: IT Payment date: 20080223 Year of fee payment: 9 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 20080415 Year of fee payment: 9 Ref country code: FR Payment date: 20080214 Year of fee payment: 9 |
|
GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 20090218 |
|
REG | Reference to a national code |
Ref country code: IE Ref legal event code: MM4A |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: ST Effective date: 20091030 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20090218 Ref country code: DE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20090901 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: FR Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20090302 Ref country code: GB Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20090218 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IT Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20090218 |