EP1016106A1 - Plaquettes de circuits imprimes en ceramique multicouche a composants passifs encastres - Google Patents

Plaquettes de circuits imprimes en ceramique multicouche a composants passifs encastres

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Publication number
EP1016106A1
EP1016106A1 EP98910019A EP98910019A EP1016106A1 EP 1016106 A1 EP1016106 A1 EP 1016106A1 EP 98910019 A EP98910019 A EP 98910019A EP 98910019 A EP98910019 A EP 98910019A EP 1016106 A1 EP1016106 A1 EP 1016106A1
Authority
EP
European Patent Office
Prior art keywords
green tape
layers
glass
capacitor
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98910019A
Other languages
German (de)
English (en)
Other versions
EP1016106A4 (fr
Inventor
Ellen Schwartz Tormey
Ashok Narayan Prabhu
Attiganal Narayanaswamy Sreeram
Michael James Liberatore
Ponnusamy Palanisamy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Lamina Ceramics Inc
Original Assignee
Sharp Corp
Sarnoff Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/812,151 external-priority patent/US5953203A/en
Priority claimed from US08/812,172 external-priority patent/US5866240A/en
Priority claimed from US09/031,745 external-priority patent/US6055151A/en
Application filed by Sharp Corp, Sarnoff Corp filed Critical Sharp Corp
Publication of EP1016106A1 publication Critical patent/EP1016106A1/fr
Publication of EP1016106A4 publication Critical patent/EP1016106A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/167—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C8/00—Enamels; Glazes; Fusion seal compositions being frit compositions having non-frit additions
    • C03C8/14—Glass frit mixtures having non-frit additions, e.g. opacifiers, colorants, mill-additions
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C8/00—Enamels; Glazes; Fusion seal compositions being frit compositions having non-frit additions
    • C03C8/22—Enamels; Glazes; Fusion seal compositions being frit compositions having non-frit additions containing two or more distinct frits having different compositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C13/00—Resistors not provided for elsewhere
    • H01C13/02—Structural combinations of resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
    • H01C17/30—Apparatus or processes specially adapted for manufacturing resistors adapted for baking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/003—Thick film resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01012—Magnesium [Mg]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • H05K3/0061—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a metallic substrate, e.g. a heat sink
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties

Definitions

  • This invention relates to multilayer, ceramic, supported printed circuit boards that have low shrinkage in two dimensions on firing. More particularly this invention relates to metal supported, multilayer, ceramic printed circuit boards that incorporate co-fired passive components.
  • Ceramic compositions of crystallizing glasses are known which, when mixed with non-crystallizing glasses, form green tape compositions which can be adhered to metal core support substrates, such as copper/nickel clad or plated kovar plates.
  • Kovar is a Fe/Co/Ni alloy commercially available from Carpenter Technology. One such alloy includes 53.8 weight percent of iron, 29 weight percent of nickel, 17 weight percent of cobalt and 0.2 weight percent of manganese. These alloys display a sharp change in their coefficient of expansion at certain temperatures. They are available with a 1 mil thick coating of copper and a 1 mil thick coating of nickel on both sides of the kovar core. They have a thermal coefficient of expansion (TCE) of 5.8 ppm/°C (RT to 300°C) and a thermal conductivity (z or thickness direction) of 21.8 Watt/m°K.
  • TCE thermal coefficient of expansion
  • a bonding glass generally a CaO-Al 2 0 3 -ZnO-B 2 0 3 glass.
  • the bonding glasses can be screen printed onto the support substrate by making a printable ink of the bonding glass powder mixed with an organic binder and a solvent.
  • the bonding glass is generally applied to a thickness of 40-70 microns on the support substrate.
  • the bonding glass is then dried and densified by heating at 700-800°C.
  • about 6% by weight of copper powder can be added to the bonding glass.
  • Low firing temperature green tapes adhered to a metal core support board having a bonding glass thereon as dexcribed above are made from a mixture of crystallizing and non-crystallizing glasses.
  • Suitable crystallizing glasses for example contain 20-
  • these glasses have a TCE matched to kovar, and they have low dielectric loss properties; however, they have a low crystallization temperature which inhibits densification of the glass on firing.
  • these glasses can be mixed with a lead-based, non-crystallizing glass.
  • these non-crystallizing glasses contain from 30-80% by weight of PbO; 15-50% by weight of Si0 2 ; up to 10% by weight of Al 2 0 3 ; up to 15% by weight of B 2 0 3 ; and up to 10% by weight of ZnO.
  • the TCE is lowered and the dielectric loss properties are increased.
  • the lateral shrinkage (x and y) is still higher than desirable as well.
  • oxide fillers such as quartz, alumina, forsterite and the like, reduces the lateral shrinkage on firing, and thus these filler- modified ceramics have desirable dielectric properties, low shrinkage during firing and a TCE matched to kovar.
  • Green tape compositions useful herein are formed by mixing suitable glass powders, including crystallizing glasses, generally of the ZnO-MgO-B 2 0 3 -Si0 2 type, with non- crystallizing glasses and oxide fillers with an organic vehicle, generally including resin, solvent, dispersants and the like, and casting the resultant slurry into a thin tape, known as green tape .
  • suitable glass powders including crystallizing glasses, generally of the ZnO-MgO-B 2 0 3 -Si0 2 type, with non- crystallizing glasses and oxide fillers with an organic vehicle, generally including resin, solvent, dispersants and the like, and casting the resultant slurry into a thin tape, known as green tape .
  • Conductive inks can be screen printed onto the green tapes to form circuit patterns.
  • Several of the green tapes can be aligned and stacked and laminated under pressure. Via holes punched in the green tapes and filled with conductive inks, e.g., mixtures of a conductive metal powder, an organic vehicle and a glass, generally the same glass as that used to make the green tape, provide a conductive path between the circuit patterns on different green tape layers.
  • conductive inks e.g., mixtures of a conductive metal powder, an organic vehicle and a glass, generally the same glass as that used to make the green tape, provide a conductive path between the circuit patterns on different green tape layers.
  • These laminated green tape stacks are then aligned with a support substrate coated with a bonding glass, and co- laminated, also under pressure. Since shrinkage occurs mainly in the thickness (z) dimension during firing, the circuitry is not disturbed during firing and close tolerances can be maintained.
  • Ceramics are compatible with low melt temperature conductive inks, such as silver- based inks, used to form the electrically connected circuits on the various layers and to form bond pads and the like.
  • conductive inks such as silver- based inks
  • the ceramic circuit boards as described hereinabove have low dielectric loss properties and are useful for use with microwave/digital packaging.
  • multilayer ceramic circuit boards are to include passive components, such as resistors or capacitors
  • passive components such as resistors or capacitors
  • solder or epoxy type adhesives to adhere the components to the multilayer ceramic.
  • the addition of these components increases the number of steps needed to make these circuit boards, i.e., the components must be aligned and adhered to the ceramic multilayer board, and connected to a source of power.
  • the multilayer boards have to be large. Thus the costs of making such boards is high.
  • passive components such as capacitors, resistors and RF components
  • passive components can be embedded in green tape stacks made of suitable glasses on a support substrate that prevents shrinkage in the x and y dimensions.
  • Suitable capacitor or resistor inks and conductive layers can be screen printed onto green tapes, embedded between other green tapes, laminated and fired at fairly low temperatures, i.e., 850-900°C, without de-laminating from the support and without shrinkage in the x and y dimensions so as to produce printed circuit boards with close tolerances that have embedded components therein.
  • Capacitor inks can be made from barium titanate, titanium oxide and lead magnesium niobate dielectrics, which, when combined with appropriate glasses, sinter at low temperatures.
  • the capacitor inks can be screen printed onto ceramic green tapes and connected to a silver conductor layer ' by means of vias in the green tape that are filled with appropriate conductive inks. After printing the passive component precursor inks and other circuitry on the green tapes, multiple green tapes are aligned, laminated together and co-fired in air at a temperature of about 850-900°C.
  • Capacitors can be made in a wide range of dielectric constants .
  • Shunt capacitors can also be made by using a ground plane metal as the bottom capacitor plate.
  • the capacitors are located one or more layers from the top of the stack.
  • Capacitors can be terminated by screen printing a conductive layer over and under the printed capacitor dielectric ink.
  • Thick film resistor inks can be made based on ruthenium oxide (Ru0 2 ) and appropriate glasses that sinter at low temperatures, together with suitable organic vehicles.
  • the resistor inks are screen printed onto green tapes that are aligned and stacked on a support, and fired to produce embedded resistors having a wide range of resistor values and thermal coefficient of resistance (TCR) values.
  • TCR thermal coefficient of resistance
  • a small amount of barium titanate can be added.
  • the resistors are connected to a source of power with a conductive layer screen printed on top of the green tape stack.
  • the multiple green tape layers are aligned, laminated together, applied to a metal support substrate via a bonding glass, and co-fired in air at temperatures of from about 780-900°C to form printed circuit boards having embedded resistors therein that are stable and reliable.
  • Fig. 1 is a graph of dielectric constant versus capacitor size for low dielectric constant inks.
  • Fig. 2 is a cross sectional view of one embodiment of a buried capacitor of the invention.
  • Fig. 3 is a graph of dielectric constant versus capacitor size for capacitors of the invention.
  • Fig. 4 is a graph of temperature coefficient of capacitance versus capacitor size for capacitors of the invention.
  • Fig. 5 is a graph of dielectric constant versus capacitor size for capacitors of the invention.
  • Fig. 6 is a graph of resistor area versus resistance and TCR for resistors having a first size.
  • Fig. 7 is a graph of resistor area versus resistance and TCR for resistors having a second size.
  • Fig. 8 is a cross sectional view of a multilayer ceramic circuit board of the invention having buried silver layers.
  • Fig. 9 is a cross sectional view of a multilayer ceramic circuit board of the invention having RF filters embedded in the layers.
  • capacitor inks based on barium titanate and titanium oxide powders. These powders sinter at high temperatures, about 1100-1300°C, and thus they must be modified by combining them with low melting glasses so that the barium titanate/glass or titanium oxide/glass compositions will sinter at lower temperatures of about 850- 900°C, and to adjust the dielectric constant (K) and to minimize the temperature coefficient of capacitance (TCC) .
  • Barium titanate is commercially available from the Degussa Company under the trade name AD302L, (designated below as D) and a mixture of barium titanate and barium tin oxide from the Ferro Corporation under the trade name YL12000 (designated below as F) .
  • the properties of these powders are set forth below in Table I, wherein K is the dielectric constant, the dielectric loss is Tan ⁇ and the temperature is in degrees Centigrade. Particle size is given as average particle size in microns ( ⁇ m) .
  • a suitable titanium oxide, #4162-01, is available from
  • the barium titanate or titanium oxide powder was mixed with various low firing temperature glasses.
  • the compositions of suitable glasses, in weight percent, is given below in Table II.
  • the capacitor inks can be screen printed onto green tapes formulated for co-firing onto metal, particularly kovar, support substrates.
  • the primary crystallizing glass used is made from a mixture of the following oxides: 29.4% of ZnO, 24.5% of MgO, 19.6% of B 2 0 3 , 24.5% of Si0 2 and 2.0% of Co 3 0 4 , all % by weight.
  • Typical green tape compositions are given below in Table IV. TABLE IV
  • the capacitor inks were screen printed onto the above green tapes in square capacitor patterns 1.27, 2.54 and 5.08 mm in size. Three four-layer green tapes were made with the capacitor ink layer one layer from the top of the stack. The green tapes were laminated at 278 psi and co-laminated to a kovar substrate at 347 psi. A silver-based powder or silver flake-based conductor ink was buried to make a buried co- fired capacitor. Suitable conductor ink compositions are set forth in Table V.
  • the resultant laminated stack was fired at 850°C.
  • the capacitance and dielectric loss (tan ⁇ ) were measured at lOKHz.
  • the dielectric constant for each capacitor was calculated from the measurement of capacitance (C) in pF, the area (A) of the capacitor in square centimeters and the thickness (t) in centimeters in accordance with the equation
  • BaTi0 3 -based capacitor inks using a silver powder conductor layer. Green tape and capacitor layers were laminated at 280 psi and fired at 850°C. The glass is given in volume %.
  • the above capacitor compositions were tailored to promote sintering at low temperatures with a minimum dilution of the dielectric constant and to contain less than
  • a barium titanate-based capacitor formulation also includes a substantial amount of a TCC modifier, SrZr0 3 .
  • Table X illustrates compositions of two such suitable capacitor inks, given in % by weight.
  • a silver-based ink made from 83.78% silver powder
  • the green tape stacks were laminated at 1670 psi and co-laminated to a kovar substrate at 1100 psi and the whole fired at 865°C.
  • the dielectric constant (K) and TCC at two temperatures are given below in Table XI .
  • a capacitor ink having a low TCC and a low dielectric constant can also be made using titanium oxide (Ti0 2 ) as the dielectric.
  • Ti0 2 titanium oxide
  • a dielectric ink was made using 42.1% of Ti0 2 powder, 29.6% of glass 2, 1.4% of Hypermer PS2 dispersant and 26.9% of a mixture of 20% of Elvacite resin in terpineol solvent .
  • the dielectric ink was applied to a green tape at least one layer below the top of the stack, and a termination layer applied thereunder using a conductor ink, and the stack laminated and fired as above.
  • the TCC and dielectric constant K are given in Table XII below.
  • a barrier layer can be used to block the diffusion of the ceramics into the capacitors during co-firing. This barrier layer can be of a more effective silver metal composition, or of a different dielectric material.
  • a BaTi0 3 based capacitor ink can be used as a barrier material when a very low melting glass, lower melting than the glass used in the green tape layers, is used.
  • This barrier glass densifies and crystallizes at a lower temperature than that required for the green tape glasses to soften significantly.
  • the barrier glass blocks the diffusion of the green tape glasses into the capacitor.
  • the barrier is printed as a pad larger than the capacitor, both below the bottom conductor pad and above the top conductor pad, as shown in Fig. 2.
  • a three layer capacitor 12 having a two layer top and bottom conductor layers 14 and 15 respectively is sandwiched between two top and bottom two-layer barrier layers 16 and 17 respectively.
  • the buried capacitor is in turn laminated to top and bottom green tape layers 18 and 19 respectively .
  • a barrier layer was printed as a pad 19x19mm, centered about a capacitor 5.08 x 5.08mm made from a PMN ink including 74.16% of PMN. Silver powder was used to make the conductor ink.
  • Various layers were employed to determine how many barium titanate barrier layers were required to obtain a high dielectric constant capacitor on a kovar supported multilayer circuit board. Controls without the barrier layers were also tested. The test results are given below in Table XIV wherein the number of prints refers to the number of screen prints used for each layer. TABLE XIV
  • Capacitor 3 36 751.6 3058 0.038 -19.6
  • the top green tape layer is subject to tearing and care must be taken to prevent that. Further, the large number of screen printing steps required (up to eleven as described above) adds to the costs of the process.
  • the silver flake while it results in a high dielectric constant capacitor, forms a structure that becomes too dense during firing, and leads to tears in the overlying green tapes.
  • the use of a mixture of silver powder and silver flake although a compromise in terms of dielectric constant, does not tear the top green tape layer nor do these structures have outgassing or bubbling problems.
  • a plurality of buried PMN-based capacitors on kovar substrates were made using silver powder, silver flake and a mixed silver powder and silver flake conductor layer. The layers were laminated at 1670 psi and fired at 865°C. The test results are summarized below in Table XV.
  • Insulation Resistance (IR) of the first capacitor of 5.08mm size was 3.8xl0 10 ohms.
  • IR of the second capacitor of 5.08mm size using silver flake was 6.0xl0 10 ohms.
  • the IR of the first capacitor using the mixed silver and the same size was l.OxlO 10 ohms.
  • the dielectric constant of the PMN capacitors exhibit a large size dependence; i.e., the dielectric constant increases with increasing capacitor size, and TCC also increases (becomes more negative) with increasing capacitor size. It is believed this is a result of dilution of the capacitor dielectric by the surrounding low dielectric constant ceramic. Large capacitors have less dilution effect than small capacitors. This is shown in Table XVI below, and schematically in Figs 3 and 4, graphs of dielectric constant and TCC versus capacitor size, respectively. In Table XV the capacitors are based on PMN with mixed silver powder-silver flake inks.
  • Fig. 5 is a graph of dielectric constant versus capacitor size using a mixed silver conductor, illustrates the differences in the size dependence of barium titanate- based capacitors and PMN-based capacitors.
  • barium titanate-based buried capacitors will be more consistent and have lower TCC as compared to PMN-based capacitors .
  • the buried capacitors of the invention have been subject to the HHBT reliability test (85°C/85%RH/50VDC) for over 1000 hours with no degradation of the capacitance, dielectric loss or insulation resistance (IR) of the buried capacitors.
  • the above co-fired multilayer ceramic circuit boards having buried capacitors of the invention are useful in various applications, such as cellular telephones.
  • Resistor inks with resistor values of from 300 ohm/sq to 100 Kohms/sq and a TCR of ⁇ +200 ppm/°C over a temperature range of room temperature to 125°C also can be made in accordance with the invention.
  • the target properties for a particular cellular telephone application are 1 Kohm/sq and a TCR less than or equal to 200 ppm/°C over the room temperature to 125°C range.
  • the resistor inks are made from a fine particle size, high surface area Ru0 2 powder having the characteristics as summarized in Table XVII.
  • the Ru0 2 is mixed with one or more glasses to reduce the firing temperature of the conductor powder. Glasses 1 and 3 as set forth above are suitable. A TCR modifier such as BaTi0 3 can also be added.
  • the above glasses are mixed with the Ru0 2 powder, optional modifier and a suitable organic vehicle to form a screen printable composition that can be fired at low temperatures, similar to the firing temperature of the green tape stacks they will be applied to.
  • the resistor ink powder generally contains 17.33 to 24.8% by weight of Ru0 2 , 74.3- 81.7% by weight of glass 1 and 0.99 to 1.10% by weight of barium titanate.
  • the preferred compositions contain 19.8 to 23.14% by weight of Ru0 2 , 75.87 to 79.21% by weight of glass 1 and 0.99 to 1.1% by weight of BaTi0 2 .
  • Resistor inks were screen printed onto a green tape incorporated into a laminated green tape stack in various patterns (1/2 squares and squares) in sizes from 0.508 x 0.508 to 2.032 x 4.064 mm.
  • Green tape compositions suitable for use herein include the following ingredients, summarized in Table XVIII. The median particle size of the glass and filler materials are given in microns.
  • Material Function Com . 1 Comp . 2 Glass 2 Crystallizing 57.34 57.29 glass
  • a suitable silver ink composition includes 83.78% by weight of silver powder, 0.65 weight % of glass 3, 1.22 weight% of a dispersant, 0.88 weight % of ethyl cellulose resin, 0.80 of Elvacite 2045 resin (available from Monsanto Company) , and a mixed solvent of 3.32 weight % of texanol, 6.81 weight % of terpineol and 2.54 weight % of butyl carbitol .
  • the green tape stacks were laminated together and placed on a kovar support substrate and co-fired in air at 850-900°C.
  • the resistors were printed and buried one layer below the top surface of the ceramic stack. After co-firing, the resistors were then connected to the outside by printing with a silver-palladium or gold conductor ink and post-fired at 700-750°C in air.
  • Table XIX below summarizes the Ru0 2 -glass compositions and the properties of the fired resistors.
  • Table XIX summarizes the Ru0 2 -glass compositions and the properties of the fired resistors.
  • the compositions are given in weight %, and TCR was measured from room temperature to 125°C.
  • a short term overload test (STOL) was also performed.
  • the above resistor compositions were admixed with an organic vehicle to form an ink composition, using a dispersant (1.44% by weight), ethyl cellulose Resin N300
  • the resistor ink was adjusted to about 38 volume % solids. In order to maximize circuit density, it is desirable to print small size resistors such as patterns of 0.508 x
  • Suitable resistor ink compositions made from the above powder mixtures are shown below in Table XXI . TABLE XXI
  • resistor ink compositions 1 and 2 are given below in Tables XXIII and XXIV respectively. TCR was measured at room temperature and at 125°C. TABLE XXIII
  • the print thickness of the 1/2 sq 1.02x2.03 mm resistor was 18.6 microns.
  • Figs. 6 and 7 are graphs of resistance versus resistor area for (1) square resistors and for (1/2) resistors respectively.
  • Test 1 was for 1000 hours at 85°C/85%RH
  • Test 2 consisted of cycling over 200 times between -55 and 125°C.
  • Test 3 applied 15.5 Watts/cm 2 of power to the resistor at 70°C for 1000 hours.
  • the resistors passed these tests.
  • Resistor ink 1 was used to make a 510 ohm buried resistor 1.016 x 2.032 mm in size in a receiver board designed for operation at 1 GHz.
  • a resistance value of 510 ohms ⁇ 10% was obtained after post firing, providing the dried ink thickness was maintained at between 18 and 25 microns .
  • the ceramic printed circuit boards of the invention are also useful for incorporating or embedding other components, such as RF filters.
  • other components such as RF filters.
  • thick multilayer stacks that are over 2 mm in thickness after firing are made.
  • the large number of green tape layers after firing preclude close control of the shrinkage in the x and y dimensions, and, in addition, the multilayer stack tends to de-laminate from the metal support substrate when fired.
  • Useful prior art glasses used to make one type of green tape are made from zinc-magnesium-borosilicate crystallizing glasses as described above.
  • a suitable crystallizing glass is glass 3 above to which 2.0% by weight of Co 3 0 4 coloring agent is added.
  • This glass is mixed with 9.6% by weight of a non- crystallizing lead-based glass of the lead- zinc-aluminum silicate system.
  • An exemplary glass contains 42.0% by weight of PbO; 10.0% by weight of Al 2 0 3 , 38.8% by weight of Si0 2 and 10.0% by weight of ZnO.
  • oxide fillers such as alumina, cordierite, quartz, cristoballite, forsterite and willemite, which serve to control the shrinkage and to further modify the TCE.
  • oxide fillers such as alumina, cordierite, quartz, cristoballite, forsterite and willemite
  • the desired dielectric properties, shrinkage characteristics and TCE matched to kovar can all be achieved.
  • minor amounts of filler oxides e.g., 1.5-2% by weight of cordierite and 9.5-10.0% by weight of forsterite, produce excellent ceramics for the present applications.
  • these glasses have major amounts of glass and minor amounts of oxide fillers ( ⁇ 15%) . These glasses have excellent dielectric properties at microwave frequencies, such as 1 GHz. These ceramics are referred to hereinafter as Type I glass-ceramics.
  • a second type of glass-ceramic is made from the same zinc-magnesium-borosilicate glasses but they include increased amounts, over about 25% by weight, of oxide fillers. These glasses have lower shrinkage than the Type 1 glass-ceramics, and are referred to hereinafter as Type 2 glass-ceramics .
  • Type 2 glass-ceramics The following Table XXV sets forth examples of different ceramic compositions useful to make the second type of green tape layers.
  • Green tapes are made by formulating the Type 1 and
  • Type 2 glass-ceramics with a resin binder together with plasticizer, dispersants and solvents in known manner, to form a thick slurry A typical glass-ceramic composition for use herein has a crystallizing glass particle size of about
  • the resultant slurry is cast to form a green tape about 0.15-0.20 mm thick, and the green tape is dried.
  • the two types of green tape using minor and major amounts of amounts of oxide fillers respectively, are then interleaved.
  • Silver or other metal patterns are screen printed on the green tapes to form circuit patterns.
  • circuit patterns are printed between two green tapes of Type 1, to form a hermetic ceramic, since the Type 2 (high filler content) glass-ceramics tend to become more porous on firing than the Type 1 glass-ceramics.
  • a co-firable conductive metal-based thick film conductor ink based on the glass compositions of the invention can be made with a conductive metal powder, such as silver powder, mixed with a small amount of the glasses disclosed above, together with known dispersants, resins and solvents to form a screen printable conductor ink.
  • Top conductor inks can be made in like fashion using silver- palladium powder, or a gold powder. Via fill inks to connect circuit patterns on various green tape layers together can also be made with silver powder, in known manner.
  • the green tape stack is then suitably laminated at a pressure of about 1.174 kg/mm 2 at about 93°C for four minutes, and co-laminated with the prepared metal support substrate at a pressure of about 1.3-1.4kg/mm 2 .
  • the multilayer stack on the kovar support is fired in a belt furnace at a belt speed of 0.4 inch/min to a peak temperature of 850-900°C.
  • the organic materials are vaporized, and the low melting glazing glass softens, adhering the multilayer ceramic stack to the metal core.
  • the metal core aids in limiting the shrinkage of the overlying green tapes in the x and y directions.
  • a conductive ink may be applied to the top of the fired multilayer stack, as to form bond pads, inductors, microstrip interconnects and the like, in known manner .
  • Example 1 The invention will be further described in the following Examples, but the invention is not meant to be limited to the details described therein. In the Examples, percent is by weight. Example 1
  • Type 1 green tape A
  • C,D a silver-based ink applied thereto
  • B Type 2 green tape
  • Type I green tape Eleven layers of Type I green tape, having metallized planes on three of the layers, were interleaved with Type 2 green tapes, as shown in Fig. 8.
  • Fig. 8 illustrates the Type 1 green tapes as A, Type 2 green tapes as B, C designates embedded RF filters, and D illustrates silver patterning.
  • the green tapes were interleaved and stacked, laminated, co- laminated to a kovar support and fired. The fired stack was 2.40 mm thick.
  • Type 2 green tape were interleaved and stacked, laminated and fired.
  • the resultant stack was 2.20 mm thick.
  • Type 1 (A) green tape having embedded filters (C) on one layer and ground planes (D) on two layers, as shown in Fig. 9, and 8 layers of Type 2 green tape (B) were interleaved and stacked, laminated and fired to form a stack 2.52 mm in thickness.
  • Example 4 23 layers, of Example 4 5.39 0.0018 11.6 GHz
  • interleaved layers 5.24 0.0019 12.2 GHz
  • interleaved green tape layers can be stacked to produce thick fired metal supported multilayer circuit boards that shrink in only one dimension.

Abstract

Les composants passifs tels que les condensateurs, les résistances et les filtres à fréquence radioélectrique peuvent être réalisés par sérigraphie en utilisant des encres appropriées sur les bandes vertes, complétées par des couches conductrices (14, 15) au-dessous et au-dessus des couches d'encre des composants. On met ensuite le feu à la pile de bandes vertes ainsi constituée pour avoir des composants encastrés. En lamellant les piles de bandes vertes sur les subtrats des plaques de support en métal, on limite le retrait dans les dimensions x et y, et les composants peuvent conserver des tolérances serrées. Si de nombreuses couches de bandes vertes doivent être empilées, on obtient un meilleur coefficient de retrait lorsque les bandes ayant une charge d'oxyde modérée, soit moins de 15 % environ du poids de la composition des bandes vertes, sont imbriquées avec des bandes vertes ayant une charge d'oxyde supérieure, soit 25 % en poids.
EP98910019A 1997-03-06 1998-03-03 Plaquettes de circuits imprimes en ceramique multicouche a composants passifs encastres Withdrawn EP1016106A4 (fr)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US812172 1991-12-20
US81283297A 1997-03-06 1997-03-06
US08/812,151 US5953203A (en) 1997-03-06 1997-03-06 Multilayer ceramic circuit boards including embedded capacitors
US812832 1997-03-06
US08/812,172 US5866240A (en) 1997-03-06 1997-03-06 Thick ceramic on metal multilayer circuit board
US812151 1997-03-06
US31745 1998-02-27
US09/031,745 US6055151A (en) 1997-03-06 1998-02-27 Multilayer ceramic circuit boards including embedded components
PCT/US1998/003270 WO1998039784A1 (fr) 1997-03-06 1998-03-03 Plaquettes de circuits imprimes en ceramique multicouche a composants passifs encastres

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EP1016106A1 true EP1016106A1 (fr) 2000-07-05
EP1016106A4 EP1016106A4 (fr) 2007-12-12

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JP (2) JP3944791B2 (fr)
KR (2) KR100516043B1 (fr)
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US6455930B1 (en) * 1999-12-13 2002-09-24 Lamina Ceramics, Inc. Integrated heat sinking packages using low temperature co-fired ceramic metal circuit board technology
US6970362B1 (en) 2000-07-31 2005-11-29 Intel Corporation Electronic assemblies and systems comprising interposer with embedded capacitors
US6775150B1 (en) 2000-08-30 2004-08-10 Intel Corporation Electronic assembly comprising ceramic/organic hybrid substrate with embedded capacitors and methods of manufacture
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US6893710B2 (en) 2003-04-18 2005-05-17 Yageo Corporation Multilayer ceramic composition
KR20050019214A (ko) 2003-08-18 2005-03-03 한국과학기술원 내장형 커패시터용 폴리머/세라믹 복합 페이스트 및 이를이용한 커패시터 제조방법
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KR100516043B1 (ko) 2005-09-26
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JP3944791B2 (ja) 2007-07-18
KR20050043991A (ko) 2005-05-11
JP2002505805A (ja) 2002-02-19
KR100546471B1 (ko) 2006-01-26
JP2006165585A (ja) 2006-06-22
WO1998039784A1 (fr) 1998-09-11
TW405330B (en) 2000-09-11

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