EP0964521B1 - Module logique composé de blocs configurables combinatoires et séquentiels - Google Patents

Module logique composé de blocs configurables combinatoires et séquentiels Download PDF

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Publication number
EP0964521B1
EP0964521B1 EP99117182A EP99117182A EP0964521B1 EP 0964521 B1 EP0964521 B1 EP 0964521B1 EP 99117182 A EP99117182 A EP 99117182A EP 99117182 A EP99117182 A EP 99117182A EP 0964521 B1 EP0964521 B1 EP 0964521B1
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EP
European Patent Office
Prior art keywords
input
output
multiplexer
data
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP99117182A
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German (de)
English (en)
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EP0964521A2 (fr
EP0964521A3 (fr
Inventor
Douglas C Galbraith
Jonathan W Greene
Abbas A El Gamal
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Microsemi SoC Corp
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Actel Corp
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Publication of EP0964521A3 publication Critical patent/EP0964521A3/fr
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Publication of EP0964521B1 publication Critical patent/EP0964521B1/fr
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits

Definitions

  • the present invention relates to digital electronic circuits.
  • the present invention relates to circuits for performing logic functions in user-programmable integrated circuits, and to circuits for implementing a wide variety of user-selectable sequential logic functions.
  • JP-A-1,093,918 discloses a latching device having the features of the preamble of appended claim 1.
  • the present invention is defined in appended ciaim 1 .
  • a logic module having a wide variety of user-configurable sequentiel logic functions.
  • the output of the third two-input multiplexer is connected to a first data input of a fourth two-input multiplexer having a HOLD1 input coupled to its select input. Its output and a low active CLEAR input are presented to an AND gate whose output is connected to the second data input of the fourth two-input multiplexer and to the first data input of a fifth two-input multiplexer in a second stage of the sequential section of the logic module of the present invention.
  • the select input of the fifth two-input multiplexer is connected to a HOLD2 input.
  • the CLEAR, HOLD1 and HOLD2 inputs are defined by combinations of signals from a data signal of a third group which may contain a data signal of one of the other groups.
  • a first section of the logic module 10 of the present invention includes first and second two-input multiplexers 12 and 14.
  • First two-input multiplexer includes first and second data inputs 16 and 18, select input 20 and output 22.
  • Second two-input multiplexer has first and second data inputs 24 and 26, select input 28 and output 30. Select inputs 20 and 28 of first and second two-input multiplexers 12 and 14 are connected to the output 32 of a two-input logic gate of a first type 34 having first and second data inputs 50 and 54.
  • Outputs 22 and 30 of first and second two-input multiplexers 12 and 14 are connected to data inputs 36 and 38 of third two-input multiplexer 40, in a second section of logic module 10.
  • Third two-input multiplexer 40 also includes select input 42 and output 44. Select input 42 of third two-input multiplexer 40 is connected to output 46 of a two-input logic gate of a second type 48 having first and second data inputs 52 and 56.
  • the data inputs 16, 18, 24 and 26 to the first and second two-input multiplexers are sourced with data signals from a first group of data input nodes shown in FIG. 1 as data inputs D00, D01, D10, and D11.
  • One input of each of logic gates 34 and 48 (reference numerals 50 and 52, respectively) is sourced from a data signal of a second group shown in FIG. 1 as data input nodes A0 and A1, respectively, and the other input of each of the logic gates (reference numerals 54 and 56, respectively) is sourced from a data signal of a third group shown in FIG. 1 as data input nodes B0 and B1, respectively.
  • the logic module 10 of the present invention offers a plurality of combinatorial functions having up to eight inputs.
  • the sequential portion of logic module 10 also has two stages.
  • the output 44 of the third two-input multiplexer 40 is connected to a first data input 58 of a fourth two-input multiplexer 60 having its select input 62 driven by a HOLD1 signal from a HOLD1 control node.
  • Its output 64 and a CLEAR signal from a CLEAR control node are presented to inputs 66 and 68 of an AND gate 70 whose output 72 is connected to the second data input 74 of the fourth two-input multiplexer and to the first data input 76 of a fifth two-input multiplexer 78, which forms the input to the second sequential stage.
  • the select input 80 of the fifth two-input multiplexer 78 is connected to a HOLD2 signal from a HOLD2 control node.
  • Output 82 of fifth two-input multiplexer 78 and the CLEAR signal are presented to inputs 84 and 86 of an AND gate 88 whose output 90 is connected to the second data input 92 of the fifth two-input multiplexer and to an output node 94.
  • the CLEAR, HOLD1 and HOLD2 signals are derived by combinatorial logic from a set of data input signals. As is shown in FIG. 2a, data signals from data input nodes C1, C2 and B0 are presented to inputs 96, 98, and 100, respectively of logic combining circuit 102, which has control node outputs upon which the HOLD1, HOLD2, and CLEAR signals appear, respectively.
  • the logic combining circuit 102 of FIG. 2a may be any logic circuit for combining the three inputs in a manner which produces outputs for the HOLD1, HOLD2, and CLEAR signals as set forth in the truth table in TABLE II.
  • FIG. 2b is a logic diagram of a presently preferred embodiment of such a circuit.
  • logic combining circuit 102 includes AND gate 104 with inverting input 106 and non-inverting input 108, and output 110, AND gate 112 with inverting input 114 and noninverting input 116 and output 118, EXNOR gate 120 with inputs 122 and 124 and output 126 and OR gate 128 with inputs 130 and 132 and output 134.
  • C1 input 96 is connected to inputs 106 and 116 of AND gates 104 and 112, respectively and to input 122 of EXNOR gate 120.
  • C2 input 98 is connected to inputs 108 and 114 of AND gates 104 and 112, respectively, and to input 124 of EXNOR gate 120.
  • B0 input 100 is connected to input 132 of OR gate 128.
  • the output 112 of AND gate 112 is connected to input 130 of OR gate 128.
  • the output 110 of AND gate 104 is the HOLD1 signal
  • the output 126 of EXNOR gate 120 is the HOLD2 signal
  • the output 134 of OR gate 128 is the clear signal.
  • the sequential portion of the logic module of the present invention disclosed herein is configurable as a rising or falling edge flip flop with asynchronous low active clear, a transparent low or high latch with asynchronous low active clear, or as a transparent flow-through element which allows only the combinatorial section of the module to be used. All latches and flip flops are non-inverting.
  • TABLE III illustrates the sequential functions available from the logic module of the present invention. From TABLE III, it can be seen that the sequential functions which may be performed include a negative triggered latch with low active clear, a positive triggered latch with low active clear, a negative triggered flip flop with low active clear, a positive triggered flip flop with low active clear and a flow through mode.
  • the states of inputs A0, D00 and D10 are restricted for positive and negative triggered latches.
  • A0 must equal 1 and both D00 and D10 must equal 0 in order for the output to be low when the latch is in transparent node and the clear input is active.
  • the two-input multiplexers and other logic components of the logic module of the present invention may be fabricated using conventional MOS and CMOS technology.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
  • Complex Calculations (AREA)

Claims (1)

  1. Module logique séquentiel universel comprenant :
    un premier multiplexeur (60) ayant une première entrée de données (58) connectée à un premier noeud d'entrée de données, une seconde entrée de données (74), une entrée de sélection (62) connectée à un premier noeud de contrôle (HOLD 1), et une sortie (64), et
    une première porte ET (70) ayant une première entrée de données (68) connectée à la sortie dudit premier multiplexeur (60), une seconde entrée de données (66) connectée à un deuxième noeud de contrôle (CLEAR) et une sortie (72) connectée à la seconde entrée de données (74) dudit premier multiplexeur (60), caractérisé par :
    un second multiplexeur (78) ayant une première entrée de données (76) connectée à la sortie de ladite première porte ET (70), une seconde entrée de données (92), une entrée de sélection (80) connectée à un troisième noeud de contrôle (HOLD 2), et une sortie (82),
    une seconde porte ET (88) ayant une première entrée (86) connectée à la sortie (82) dudit second multiplexeur (78), une seconde entrée (84) connectée audit deuxième noeud de contrôle (CLEAR), et une sortie (90) connectée à la seconde entrée (92) dudit second multiplexeur et à un noeud de sortie (Z),
    un premier moyen combinatoire (112, 118) pour placer soit un zéro logique soit un un logique sur ledit deuxième noeud de contrôle (CLEAR) en réponse à des combinaisons présélectionnées des états d'un deuxième (BO), d'un troisième (C1) et d'un quatrième (C2) noeud d'entrée de données, et
    un second moyen combinatoire (104, 120) pour placer, en réponse à des combinaisons présélectionnées des états desdits troisième (C1) et quatrième (C2) noeuds d'entrée de données, soit un zéro logique soit un un logique sur ledit premier noeud de contrôle (HOLD 1) et soit un zéro logique soit un un logique sur ledit troisième noeud de contrôle (HOLD 2), dans lequel
    la fonction logique séquentielle de ladite première entrée de données (58) dudit premier multiplexeur (60) vers ledit noeud de sortie (Z) est déterminée par lesdits états dudit deuxième (BO), dudit troisième (C1) et dudit quatrième (C2) noeuds d'entrée de données.
EP99117182A 1990-05-11 1991-04-30 Module logique composé de blocs configurables combinatoires et séquentiels Expired - Lifetime EP0964521B1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US522232 1990-05-11
US07/522,232 US5055718A (en) 1990-05-11 1990-05-11 Logic module with configurable combinational and sequential blocks
EP96116903A EP0756382A3 (fr) 1990-05-11 1991-04-30 Module logique avec blocs combinatoires et séquentiels configurables
EP91303916A EP0456399B1 (fr) 1990-05-11 1991-04-30 Module logique composé de blocs configurables combinatoires et séquentiels

Related Parent Applications (1)

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EP96116903A Division EP0756382A3 (fr) 1990-05-11 1991-04-30 Module logique avec blocs combinatoires et séquentiels configurables

Publications (3)

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EP0964521A2 EP0964521A2 (fr) 1999-12-15
EP0964521A3 EP0964521A3 (fr) 1999-12-22
EP0964521B1 true EP0964521B1 (fr) 2005-01-12

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EP91303916A Expired - Lifetime EP0456399B1 (fr) 1990-05-11 1991-04-30 Module logique composé de blocs configurables combinatoires et séquentiels
EP96116903A Withdrawn EP0756382A3 (fr) 1990-05-11 1991-04-30 Module logique avec blocs combinatoires et séquentiels configurables
EP99117182A Expired - Lifetime EP0964521B1 (fr) 1990-05-11 1991-04-30 Module logique composé de blocs configurables combinatoires et séquentiels

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EP91303916A Expired - Lifetime EP0456399B1 (fr) 1990-05-11 1991-04-30 Module logique composé de blocs configurables combinatoires et séquentiels
EP96116903A Withdrawn EP0756382A3 (fr) 1990-05-11 1991-04-30 Module logique avec blocs combinatoires et séquentiels configurables

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US (1) US5055718A (fr)
EP (3) EP0456399B1 (fr)
JP (1) JPH07106949A (fr)
AT (2) ATE155298T1 (fr)
DE (2) DE69133438T2 (fr)

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Also Published As

Publication number Publication date
EP0456399A3 (en) 1992-03-04
EP0456399A2 (fr) 1991-11-13
JPH07106949A (ja) 1995-04-21
EP0756382A3 (fr) 1997-03-19
EP0456399B1 (fr) 1997-07-09
EP0756382A2 (fr) 1997-01-29
US5055718A (en) 1991-10-08
DE69133438T2 (de) 2006-01-05
DE69133438D1 (de) 2005-02-17
EP0964521A2 (fr) 1999-12-15
ATE155298T1 (de) 1997-07-15
DE69126741D1 (de) 1997-08-14
DE69126741T2 (de) 1997-10-23
EP0964521A3 (fr) 1999-12-22
ATE287143T1 (de) 2005-01-15

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