EP0964517A3 - Verzögerungsregelschleife - Google Patents

Verzögerungsregelschleife Download PDF

Info

Publication number
EP0964517A3
EP0964517A3 EP99304488A EP99304488A EP0964517A3 EP 0964517 A3 EP0964517 A3 EP 0964517A3 EP 99304488 A EP99304488 A EP 99304488A EP 99304488 A EP99304488 A EP 99304488A EP 0964517 A3 EP0964517 A3 EP 0964517A3
Authority
EP
European Patent Office
Prior art keywords
locked loop
delay locked
clock
synchronization
rising
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP99304488A
Other languages
English (en)
French (fr)
Other versions
EP0964517A2 (de
EP0964517B1 (de
Inventor
Jean-Marc Dortu
Albert M. Chu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
International Business Machines Corp
Original Assignee
Siemens AG
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, International Business Machines Corp filed Critical Siemens AG
Publication of EP0964517A2 publication Critical patent/EP0964517A2/de
Publication of EP0964517A3 publication Critical patent/EP0964517A3/de
Application granted granted Critical
Publication of EP0964517B1 publication Critical patent/EP0964517B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input

Landscapes

  • Dram (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
EP99304488A 1998-06-09 1999-06-09 Verzögerungsregelschleife Expired - Lifetime EP0964517B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US93802 1987-09-04
US09/093,802 US6100733A (en) 1998-06-09 1998-06-09 Clock latency compensation circuit for DDR timing

Publications (3)

Publication Number Publication Date
EP0964517A2 EP0964517A2 (de) 1999-12-15
EP0964517A3 true EP0964517A3 (de) 2000-04-05
EP0964517B1 EP0964517B1 (de) 2003-08-27

Family

ID=22240811

Family Applications (1)

Application Number Title Priority Date Filing Date
EP99304488A Expired - Lifetime EP0964517B1 (de) 1998-06-09 1999-06-09 Verzögerungsregelschleife

Country Status (7)

Country Link
US (1) US6100733A (de)
EP (1) EP0964517B1 (de)
JP (1) JP2000187522A (de)
KR (1) KR100624871B1 (de)
CN (1) CN1139016C (de)
DE (1) DE69910674T2 (de)
TW (1) TW483256B (de)

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US7865154B2 (en) * 2000-07-20 2011-01-04 Paratek Microwave, Inc. Tunable microwave devices with auto-adjusting matching circuit
US8064188B2 (en) 2000-07-20 2011-11-22 Paratek Microwave, Inc. Optimized thin film capacitors
JP4592179B2 (ja) 2000-12-19 2010-12-01 ルネサスエレクトロニクス株式会社 ディレイロックドループ、当該ディレイロックドループを含む半導体装置およびクロック同期により動作するシステムのための制御方法
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US6570791B2 (en) 2001-08-30 2003-05-27 Micron Technology, Inc. Flash memory with DDRAM interface
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US6774686B2 (en) * 2001-09-28 2004-08-10 Intel Corporation Method for minimizing jitter using matched, controlled-delay elements slaved to a closed-loop timing reference
US6731147B2 (en) 2001-10-29 2004-05-04 Cypress Semiconductor Corp. Method and architecture for self-clocking digital delay locked loop
KR100477809B1 (ko) 2002-05-21 2005-03-21 주식회사 하이닉스반도체 듀티 사이클 교정이 가능한 디지털 디엘엘 장치 및 듀티사이클 교정 방법
US7085905B2 (en) * 2002-07-18 2006-08-01 Sun Microsystems, Inc. Memory data stretcher
US6807125B2 (en) * 2002-08-22 2004-10-19 International Business Machines Corporation Circuit and method for reading data transfers that are sent with a source synchronous clock signal
DE60200289T2 (de) * 2002-09-24 2005-02-17 Agilent Technologies Inc., A Delaware Corp., Palo Alto Übergangsanpassung
US6710636B1 (en) * 2002-10-03 2004-03-23 Cypress Semiconductor Corporation Method and system for high resolution delay lock loop
US7282962B1 (en) 2003-02-19 2007-10-16 Marvell Semiconductor Israel, Ltd. Inverted-phase detector
DE10320792B3 (de) * 2003-04-30 2004-10-07 Infineon Technologies Ag Vorrichtung zur Synchronisation von Taktsignalen
DE10345489B3 (de) * 2003-09-30 2005-04-14 Infineon Technologies Ag Vorrichtung zur Verwendung bei der Synchronisation von Taktsignalen, sowie Taktsignal-Synchronisationsverfahren
US20050086424A1 (en) * 2003-10-21 2005-04-21 Infineon Technologies North America Corp. Well-matched echo clock in memory system
DE10349466B4 (de) * 2003-10-23 2009-08-27 Qimonda Ag Taktsignal-Synchronisations-Vorrichtung, sowie Taktsignal-Synchronisationsverfahren
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DE10354818B3 (de) * 2003-11-24 2005-02-17 Infineon Technologies Ag Taktsignsal-Ein-/Ausgabevorrichtung, insbesondere zur Korrektur von Taktsignalen
KR100590514B1 (ko) * 2003-12-30 2006-06-15 동부일렉트로닉스 주식회사 반도체 제조 장비 자동 선택 방법
DE102004041896B4 (de) * 2004-08-30 2006-05-18 Infineon Technologies Ag Taktsignal-Synchronisations-Vorrichtung, sowie Taktsignal-Synchronisationsverfahren
US7466783B2 (en) * 2004-12-13 2008-12-16 Lexmark International, Inc. Method and system to implement a double data rate (DDR) interface
KR100713082B1 (ko) * 2005-03-02 2007-05-02 주식회사 하이닉스반도체 클럭의 듀티 비율을 조정할 수 있는 지연 고정 루프
US7555089B2 (en) * 2005-05-20 2009-06-30 Honeywell International Inc. Data edge-to-clock edge phase detector for high speed circuits
US7254505B2 (en) * 2005-06-29 2007-08-07 Avago Technologies General Ip (Singapore) Pte. Ltd. Method and apparatus for calibrating delay lines
DE102005036559B3 (de) 2005-08-03 2007-01-04 Infineon Technologies Ag Vorrichtung und Verfahren zur Synchronisation von Taktsignalen und Regelung des duty cycles des Taktsignals
US9406444B2 (en) 2005-11-14 2016-08-02 Blackberry Limited Thin film capacitors
US7711337B2 (en) 2006-01-14 2010-05-04 Paratek Microwave, Inc. Adaptive impedance matching module (AIMM) control architectures
US8325097B2 (en) 2006-01-14 2012-12-04 Research In Motion Rf, Inc. Adaptively tunable antennas and method of operation therefore
US8125399B2 (en) 2006-01-14 2012-02-28 Paratek Microwave, Inc. Adaptively tunable antennas incorporating an external probe to monitor radiated power
US7535312B2 (en) * 2006-11-08 2009-05-19 Paratek Microwave, Inc. Adaptive impedance matching apparatus, system and method with improved dynamic range
US8299867B2 (en) 2006-11-08 2012-10-30 Research In Motion Rf, Inc. Adaptive impedance matching module
US7714676B2 (en) 2006-11-08 2010-05-11 Paratek Microwave, Inc. Adaptive impedance matching apparatus, system and method
US7813777B2 (en) * 2006-12-12 2010-10-12 Paratek Microwave, Inc. Antenna tuner with zero volts impedance fold back
EP2140454A2 (de) 2007-04-19 2010-01-06 Rambus, Inc. Taktsynchronisierung in einem speichersystem
US7917104B2 (en) 2007-04-23 2011-03-29 Paratek Microwave, Inc. Techniques for improved adaptive impedance matching
US8213886B2 (en) 2007-05-07 2012-07-03 Paratek Microwave, Inc. Hybrid techniques for antenna retuning utilizing transmit and receive power information
US7861105B2 (en) * 2007-06-25 2010-12-28 Analogix Semiconductor, Inc. Clock data recovery (CDR) system using interpolator and timing loop module
US20090068314A1 (en) * 2007-09-12 2009-03-12 Robert Chatel Granulation Method And Additives With Narrow Particle Size Distribution Produced From Granulation Method
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US7667507B2 (en) * 2008-06-26 2010-02-23 Intel Corporation Edge-timing adjustment circuit
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KR101018690B1 (ko) * 2008-10-31 2011-03-04 주식회사 하이닉스반도체 반도체 장치
US8472888B2 (en) 2009-08-25 2013-06-25 Research In Motion Rf, Inc. Method and apparatus for calibrating a communication device
US9026062B2 (en) 2009-10-10 2015-05-05 Blackberry Limited Method and apparatus for managing operations of a communication device
US8803631B2 (en) 2010-03-22 2014-08-12 Blackberry Limited Method and apparatus for adapting a variable impedance network
JP5901612B2 (ja) 2010-04-20 2016-04-13 ブラックベリー リミテッド 通信デバイスにおける干渉を管理するための方法および装置
US9379454B2 (en) 2010-11-08 2016-06-28 Blackberry Limited Method and apparatus for tuning antennas in a communication device
US8712340B2 (en) 2011-02-18 2014-04-29 Blackberry Limited Method and apparatus for radio antenna frequency tuning
US8655286B2 (en) 2011-02-25 2014-02-18 Blackberry Limited Method and apparatus for tuning a communication device
US8594584B2 (en) 2011-05-16 2013-11-26 Blackberry Limited Method and apparatus for tuning a communication device
US8626083B2 (en) 2011-05-16 2014-01-07 Blackberry Limited Method and apparatus for tuning a communication device
US9769826B2 (en) 2011-08-05 2017-09-19 Blackberry Limited Method and apparatus for band tuning in a communication device
US8638145B2 (en) 2011-12-30 2014-01-28 Advanced Micro Devices, Inc. Method for locking a delay locked loop
US8948889B2 (en) 2012-06-01 2015-02-03 Blackberry Limited Methods and apparatus for tuning circuit components of a communication device
US9853363B2 (en) 2012-07-06 2017-12-26 Blackberry Limited Methods and apparatus to control mutual coupling between antennas
US9246223B2 (en) 2012-07-17 2016-01-26 Blackberry Limited Antenna tuning for multiband operation
US9350405B2 (en) 2012-07-19 2016-05-24 Blackberry Limited Method and apparatus for antenna tuning and power consumption management in a communication device
US9413066B2 (en) 2012-07-19 2016-08-09 Blackberry Limited Method and apparatus for beam forming and antenna tuning in a communication device
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US9374113B2 (en) 2012-12-21 2016-06-21 Blackberry Limited Method and apparatus for adjusting the timing of radio antenna tuning
US10404295B2 (en) 2012-12-21 2019-09-03 Blackberry Limited Method and apparatus for adjusting the timing of radio antenna tuning
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CN105553449B (zh) * 2015-12-31 2018-09-07 苏州芯动科技有限公司 摆率自校准驱动电路、驱动器摆率校准电路及其校准方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0476585A2 (de) * 1990-09-18 1992-03-25 Fujitsu Limited Bezugsverzögerungsgenerator und elektronische Anordnung mit solch einem Generator
US5146121A (en) * 1991-10-24 1992-09-08 Northern Telecom Limited Signal delay apparatus employing a phase locked loop
US5486783A (en) * 1994-10-31 1996-01-23 At&T Corp. Method and apparatus for providing clock de-skewing on an integrated circuit board
US5719514A (en) * 1995-03-31 1998-02-17 Ando Electric Co., Ltd. Delay circuit compensating for variations in delay time
GB2316247A (en) * 1996-08-13 1998-02-18 Fujitsu Ltd An arrangement for supplying phase locked clock signals to semiconductor circuits

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Patent Citations (5)

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Publication number Priority date Publication date Assignee Title
EP0476585A2 (de) * 1990-09-18 1992-03-25 Fujitsu Limited Bezugsverzögerungsgenerator und elektronische Anordnung mit solch einem Generator
US5146121A (en) * 1991-10-24 1992-09-08 Northern Telecom Limited Signal delay apparatus employing a phase locked loop
US5486783A (en) * 1994-10-31 1996-01-23 At&T Corp. Method and apparatus for providing clock de-skewing on an integrated circuit board
US5719514A (en) * 1995-03-31 1998-02-17 Ando Electric Co., Ltd. Delay circuit compensating for variations in delay time
GB2316247A (en) * 1996-08-13 1998-02-18 Fujitsu Ltd An arrangement for supplying phase locked clock signals to semiconductor circuits

Also Published As

Publication number Publication date
DE69910674D1 (de) 2003-10-02
TW483256B (en) 2002-04-11
EP0964517A2 (de) 1999-12-15
KR100624871B1 (ko) 2006-09-18
DE69910674T2 (de) 2004-07-08
EP0964517B1 (de) 2003-08-27
US6100733A (en) 2000-08-08
KR20000006028A (ko) 2000-01-25
CN1139016C (zh) 2004-02-18
CN1238485A (zh) 1999-12-15
JP2000187522A (ja) 2000-07-04

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