EP0960421A4 - Structure de precharge et de charge de ligne de bits pour memoire ram statique - Google Patents

Structure de precharge et de charge de ligne de bits pour memoire ram statique

Info

Publication number
EP0960421A4
EP0960421A4 EP98903387A EP98903387A EP0960421A4 EP 0960421 A4 EP0960421 A4 EP 0960421A4 EP 98903387 A EP98903387 A EP 98903387A EP 98903387 A EP98903387 A EP 98903387A EP 0960421 A4 EP0960421 A4 EP 0960421A4
Authority
EP
European Patent Office
Prior art keywords
sram memory
bitline load
precharge structure
precharge
bitline
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP98903387A
Other languages
German (de)
English (en)
Other versions
EP0960421B1 (fr
EP0960421A1 (fr
Inventor
Saroj Pathak
James E Payne
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atmel Corp
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Publication of EP0960421A1 publication Critical patent/EP0960421A1/fr
Publication of EP0960421A4 publication Critical patent/EP0960421A4/fr
Application granted granted Critical
Publication of EP0960421B1 publication Critical patent/EP0960421B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
EP98903387A 1997-01-24 1998-01-06 Structure de precharge et de charge de ligne de bits pour memoire ram statique Expired - Lifetime EP0960421B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US788523 1997-01-24
US08/788,523 US5781469A (en) 1997-01-24 1997-01-24 Bitline load and precharge structure for an SRAM memory
PCT/US1998/000238 WO1998033183A1 (fr) 1997-01-24 1998-01-06 Structure de precharge et de charge de ligne de bits pour memoire ram statique

Publications (3)

Publication Number Publication Date
EP0960421A1 EP0960421A1 (fr) 1999-12-01
EP0960421A4 true EP0960421A4 (fr) 2003-07-09
EP0960421B1 EP0960421B1 (fr) 2004-03-31

Family

ID=25144750

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98903387A Expired - Lifetime EP0960421B1 (fr) 1997-01-24 1998-01-06 Structure de precharge et de charge de ligne de bits pour memoire ram statique

Country Status (8)

Country Link
US (1) US5781469A (fr)
EP (1) EP0960421B1 (fr)
JP (1) JP2001509299A (fr)
KR (1) KR100483759B1 (fr)
CN (1) CN100390896C (fr)
DE (1) DE69822800T2 (fr)
TW (1) TW374173B (fr)
WO (1) WO1998033183A1 (fr)

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JP2974252B2 (ja) * 1989-08-19 1999-11-10 富士通株式会社 半導体記憶装置
US6075729A (en) * 1997-09-05 2000-06-13 Hitachi, Ltd. High-speed static random access memory
US6181641B1 (en) * 1999-05-26 2001-01-30 Lockheed Martin Corporation Memory device having reduced power requirements and associated methods
US6166946A (en) * 2000-01-21 2000-12-26 Hewlett-Packard Company System and method for writing to and reading from a memory cell
US6631093B2 (en) * 2001-06-29 2003-10-07 Intel Corporation Low power precharge scheme for memory bit lines
JP2003157689A (ja) * 2001-11-20 2003-05-30 Hitachi Ltd 半導体装置及びデータプロセッサ
US6873538B2 (en) * 2001-12-20 2005-03-29 Micron Technology, Inc. Programmable conductor random access memory and a method for writing thereto
CN100345217C (zh) * 2003-04-07 2007-10-24 联发科技股份有限公司 单一位线半导体存储元件的感测电路
US6870398B2 (en) * 2003-04-24 2005-03-22 Ami Semiconductor, Inc. Distributed memory and logic circuits
JP4186768B2 (ja) * 2003-09-16 2008-11-26 沖電気工業株式会社 マルチポート半導体メモリ
US7349271B2 (en) * 2005-10-13 2008-03-25 International Business Machines Corporation Cascaded test circuit with inter-bitline drive devices for evaluating memory cell performance
US7376001B2 (en) * 2005-10-13 2008-05-20 International Business Machines Corporation Row circuit ring oscillator method for evaluating memory cell performance
JP4965844B2 (ja) * 2005-10-20 2012-07-04 株式会社東芝 半導体メモリ装置
US7342832B2 (en) * 2005-11-16 2008-03-11 Actel Corporation Bit line pre-settlement circuit and method for flash memory sensing scheme
US7414904B2 (en) * 2006-12-12 2008-08-19 International Business Machines Corporation Method for evaluating storage cell design using a wordline timing and cell access detection circuit
US7409305B1 (en) 2007-03-06 2008-08-05 International Business Machines Corporation Pulsed ring oscillator circuit for storage cell read timing evaluation
US7768850B2 (en) * 2007-05-04 2010-08-03 Texas Instruments Incorporated System for bitcell and column testing in SRAM
US7649779B2 (en) * 2007-05-15 2010-01-19 Qimonda Ag Integrated circuits; methods for manufacturing an integrated circuit; memory modules; computing systems
US7760565B2 (en) * 2007-07-24 2010-07-20 International Business Machines Corporation Wordline-to-bitline output timing ring oscillator circuit for evaluating storage array performance
US7545176B2 (en) * 2007-10-25 2009-06-09 International Business Machines Corporation Energy-saving circuit and method using charge equalization across complementary nodes
WO2010042820A1 (fr) * 2008-10-10 2010-04-15 Arizona Board Of Regents, For And On Behalf Of Arizona State University Mémoire non-volatile à tension de seuil différentielle et procédés associés
WO2012020488A1 (fr) * 2010-08-11 2012-02-16 富士通株式会社 Dispositif de stockage à semiconducteurs
US8817562B2 (en) * 2012-07-31 2014-08-26 Freescale Semiconductor, Inc. Devices and methods for controlling memory cell pre-charge operations
US8929120B2 (en) 2012-08-29 2015-01-06 Micron Technology, Inc. Diode segmentation in memory
US9030893B2 (en) * 2013-02-06 2015-05-12 Qualcomm Incorporated Write driver for write assistance in memory device
CN103187093B (zh) * 2013-03-18 2016-03-23 西安华芯半导体有限公司 静态随机存储器及其存取控制方法及其位线预充电电路
US9508405B2 (en) * 2013-10-03 2016-11-29 Stmicroelectronics International N.V. Method and circuit to enable wide supply voltage difference in multi-supply memory
CN105632544B (zh) * 2014-10-27 2018-05-04 华为技术有限公司 一种磁性存储器
US9384826B2 (en) 2014-12-05 2016-07-05 Texas Instruments Incorporated Circuits and methods for performance optimization of SRAM memory
KR102637709B1 (ko) 2015-07-27 2024-02-19 파워 다운 세미컨덕터 아이엔씨 공진 구동 회로를 이용한 저전력 sram 비트셀
US10607692B2 (en) * 2017-06-29 2020-03-31 SK Hynix Inc. Serializer and memory device including the same
US10878892B2 (en) 2018-04-23 2020-12-29 Arm Limited Integrated circuit using discharging circuitries for bit lines
TWI802703B (zh) 2019-05-31 2023-05-21 聯華電子股份有限公司 靜態隨機存取記憶體裝置
US11676656B2 (en) * 2021-02-05 2023-06-13 Arm Limited Memory architecture with DC biasing
US11784648B2 (en) 2021-06-02 2023-10-10 Power Down Semiconductor, Inc. Low power interconnect using resonant drive circuitry

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0336319A2 (fr) * 1988-03-31 1989-10-11 Kabushiki Kaisha Toshiba MOS SRAM du type à synchronisation interne avec circuit de détection pour transition d'adresse
US5305259A (en) * 1989-05-02 1994-04-19 Samsung Electronics Co. Ltd. Power source voltage tracking circuit for stabilization of bit lines
JPH06282989A (ja) * 1993-03-29 1994-10-07 Nippon Telegr & Teleph Corp <Ntt> 半導体メモリ

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JPH0831278B2 (ja) * 1981-03-09 1996-03-27 富士通株式会社 メモリ回路
JPH0775343B2 (ja) * 1986-02-14 1995-08-09 株式会社日立製作所 同期検出回路及び方法
JP2615011B2 (ja) * 1986-06-13 1997-05-28 株式会社日立製作所 半導体記憶回路
KR880008330A (ko) * 1986-12-30 1988-08-30 강진구 스테이틱 램의 프리차아지 시스템
JPH01119984A (ja) * 1987-10-31 1989-05-12 Toshiba Corp ダイナミック型半導体メモリ
US4802129A (en) * 1987-12-03 1989-01-31 Motorola, Inc. RAM with dual precharge circuit and write recovery circuitry
FR2644886B1 (fr) * 1989-03-24 1993-12-10 Celette Sa Dispositif de controle de la position de differents points d'un vehicule
US4964083A (en) * 1989-04-27 1990-10-16 Motorola, Inc. Non-address transition detection memory with improved access time
KR940005785B1 (ko) * 1991-12-31 1994-06-23 현대전자산업 주식회사 어드레스 전이 검출회로
US5359555A (en) * 1992-03-06 1994-10-25 National Semiconductor Corporation Column selector circuit for shared column CMOS EPROM
US5301157A (en) * 1992-06-01 1994-04-05 Micron Technology, Inc. Coupling circuit and method for discharging a non-selected bit line during accessing of a memory storage cell
US5276650A (en) 1992-07-29 1994-01-04 Intel Corporation Memory array size reduction
JPH0660665A (ja) * 1992-08-10 1994-03-04 Nec Corp 半導体スタティックｒａｍのビット線負荷回路
JPH07230691A (ja) * 1994-02-16 1995-08-29 Fujitsu Ltd 半導体記憶装置
US5416744A (en) * 1994-03-08 1995-05-16 Motorola Inc. Memory having bit line load with automatic bit line precharge and equalization
US5499211A (en) * 1995-03-13 1996-03-12 International Business Machines Corporation Bit-line precharge current limiter for CMOS dynamic memories

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0336319A2 (fr) * 1988-03-31 1989-10-11 Kabushiki Kaisha Toshiba MOS SRAM du type à synchronisation interne avec circuit de détection pour transition d'adresse
US5305259A (en) * 1989-05-02 1994-04-19 Samsung Electronics Co. Ltd. Power source voltage tracking circuit for stabilization of bit lines
JPH06282989A (ja) * 1993-03-29 1994-10-07 Nippon Telegr & Teleph Corp <Ntt> 半導体メモリ

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1995, no. 01 28 February 1995 (1995-02-28) *
See also references of WO9833183A1 *

Also Published As

Publication number Publication date
TW374173B (en) 1999-11-11
DE69822800D1 (de) 2004-05-06
CN1244281A (zh) 2000-02-09
WO1998033183A1 (fr) 1998-07-30
CN100390896C (zh) 2008-05-28
EP0960421B1 (fr) 2004-03-31
US5781469A (en) 1998-07-14
EP0960421A1 (fr) 1999-12-01
KR20000070411A (ko) 2000-11-25
JP2001509299A (ja) 2001-07-10
KR100483759B1 (ko) 2005-04-19
DE69822800T2 (de) 2004-12-30

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