Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/57—Protection from inspection, reverse engineering or tampering
  • H01L23/576—Protection from inspection, reverse engineering or tampering using active circuits
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
  • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
  • G06F21/86—Secure or tamper-resistant housings
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
  • Y10S257/922—Active solid-state devices, e.g. transistors, solid-state diodes with means to prevent inspection of or tampering with an integrated circuit, e.g. "smart card", anti-tamper

Definitions

• the invention relates to an analysis protection for a semiconductor chip with an electrically insulating cover.
• semiconductor chip The development costs of an integrated circuit, hereinafter referred to as semiconductor chip, are known to be very high, while the production costs, in particular in the case of very large quantities, can be comparatively low.
• a known analysis protection consists in mechanically firmly connecting a cover to the chip. As long as the cover is in place, the semiconductor chip is adequately protected. The fixed connection is intended to prevent the cover from detaching or at least to destroy the chip surface during this process. In principle, good protection can already be obtained. With a correspondingly great effort, however, it is possible under certain circumstances to remove the cover and to make the surface freely accessible in such a way that the function and structure of the semiconductor chip can be understood. This fuse therefore does not reliably fulfill its purpose in every case.
• the invention is based on the specification to provide copy protection for a semiconductor chip with improved security function.
• This object is achieved in that the semiconductor chip has at least one resonant resonant circuit with a coil and capacitor, the cover forming a dielectric of the capacitor, and also has an evaluation circuit which deactivates the semiconductor chip when the resonant circuit is out of resonance by changing the cover brought.
• a basic idea of the invention is therefore to produce an electrical coupling with the cover that is necessary for the function of the semiconductor chip.
• This coupling is achieved in that the cover forms a necessary element of an oscillating circuit with coil and capacitor, by influencing the dielectric constant of the oscillating circuit capacitor. If the cover is tampered with or removed, the semiconductor chip can no longer be operated due to detuning of the resonance circuit. However, since operation is a prerequisite for a detailed analysis, reliable protection against analysis and copying of the semiconductor chip is obtained.
• the vibration behavior of the resonant circuit also changes.
• the resonance frequency is either shifted or the ability to vibrate is destroyed.
• the resonant circuit is brought out of resonance and the evaluation circuit permanently deactivates the semiconductor chip.
• the security is further increased by the fact that there are several resonant circuits which are coupled to one another. An attempt to install an equivalent circuit with a reconstruction of the vote after removing the cover is doomed to fail by this measure.
• the evaluation circuit is designed in such a way that, after the cover has been applied, the resonance frequency of the oscillating or the oscillating circles automatically determined and operates them in resonance during the operation of the semiconductor chip.
• the resonance frequency is only determined once before the semiconductor chip is put into operation. After removing the cover, it is impossible to remove the resonant circuit or the
• Tuning resonant circuits again as originally.
• manufacturing tolerances with regard to the tuning of the resonant circuit or the resonant circuits are neutralized, since the evaluation circuit according to the invention determines the tuning in the fully assembled state of the semiconductor chip and the cover.
• the evaluation circuit is designed in such a way that it operates the resonant circuit or the resonant circuits at a fixed frequency.
• the determination of the specific resonance frequency or the adjustment to a normal value by the evaluation circuit is carried out automatically and is not comprehensible from the outside.
• the coil and the capacitor of the resonant circuit or of the resonant circuits can be designed as metallic structures below a hermetically sealing surface layer of the semiconductor chip.
• a particularly simple manufacture can, however, be achieved in that the coil (s) and capacitor (s) are applied directly to the surface layer of the chip as metallic conductor tracks.
• a capacitor is preferably formed by parallel conductor track sections of a coil. This has the advantage that the coil and capacitor can be designed as a simple geometric structure.
• the sensitivity of the resonant circuit is preferably increased in that the coil and / or the capacitor span or occupy the entire chip surface.
• FIG. 1 a perspective partial sectional view of a semiconductor chip in a transparent housing.
• a semiconductor chip 1 is located approximately centrally in a cuboid housing 2 made of electrically insulating plastic material which, with its upper region, forms a cover layer for the upper side of the semiconductor chip 1.
• a cover 4 made of dielectric material is accordingly above the chip surface 3.
• a metallic structure 5, which forms a coil and a capacitor of an oscillating circuit, is applied directly to the chip surface 3.
• the coil is formed by a spiral-shaped conductor track 6 with two end-side connection points 7 and, if possible, spans the entire circumferential area of the chip surface 3.
• the capacitor is formed by parallel blind conductor track sections 8 of the coil.
• the coil and the capacitor are electrically connected to further components of the resonant circuit, which are integrated in the semiconductor chip 1.
• an electronic evaluation circuit (not shown) which is connected to the resonant circuit and which deactivates the semiconductor chip 1 if the resonant circuit does not oscillate properly.
• the dielectric plastic material of the cover 4 defines the value of the capacitance of the capacitor of the resonant circuit. If the cover 4 is removed, the capacitance value of the capacitor also changes, since the geometric arrangement of the dielectric material and the capacitor is changed relative to one another. The associated resonant circuit is out of resonance, which is determined by the evaluation circuit and irreversible leads to the inoperability of the semiconductor chip 1.

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• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Theoretical Computer Science (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Computer Security & Cryptography (AREA)
• Software Systems (AREA)
• General Engineering & Computer Science (AREA)
• Semiconductor Integrated Circuits (AREA)

Applications Claiming Priority (3)

Publications (1)

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ID=7806632

Family Applications (1)

Country Status (5)

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Family Cites Families (11)

• 1996
  • 1996-09-23 DE DE19639033A patent/DE19639033C1/de not_active Expired - Fee Related
• 1997
  • 1997-09-11 WO PCT/DE1997/002039 patent/WO1998013872A1/de not_active Application Discontinuation
  • 1997-09-11 EP EP97943756A patent/EP0931344A1/de not_active Ceased
  • 1997-09-16 IN IN1703CA1997 patent/IN191646B/en unknown
• 1999
  • 1999-03-23 US US09/274,501 patent/US6201296B1/en not_active Expired - Lifetime

Non-Patent Citations (1)

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