EP0926260A3 - Verwendung der Antikörper - Antigen Wechselwirkung zur Herstellung eines Metallfilmmusters - Google Patents

Verwendung der Antikörper - Antigen Wechselwirkung zur Herstellung eines Metallfilmmusters Download PDF

Info

Publication number
EP0926260A3
EP0926260A3 EP98123279A EP98123279A EP0926260A3 EP 0926260 A3 EP0926260 A3 EP 0926260A3 EP 98123279 A EP98123279 A EP 98123279A EP 98123279 A EP98123279 A EP 98123279A EP 0926260 A3 EP0926260 A3 EP 0926260A3
Authority
EP
European Patent Office
Prior art keywords
rat igg
igg antibody
substrate
antibody film
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98123279A
Other languages
English (en)
French (fr)
Other versions
EP0926260A2 (de
Inventor
Kiyoyuki Morita
Kiyoshi Morimoto
Kiyoshi Araki
Koichiro Yuki
Kazuyasu Adachi
Masayuki Endo
Ichiro Yamashita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of EP0926260A2 publication Critical patent/EP0926260A2/de
Publication of EP0926260A3 publication Critical patent/EP0926260A3/de
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0009RRAM elements whose operation depends upon chemical change
    • G11C13/0014RRAM elements whose operation depends upon chemical change comprising cells based on organic memory material
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5664Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using organic memory material storage elements
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5671Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0009RRAM elements whose operation depends upon chemical change
    • G11C13/0014RRAM elements whose operation depends upon chemical change comprising cells based on organic memory material
    • G11C13/0019RRAM elements whose operation depends upon chemical change comprising cells based on organic memory material comprising bio-molecules
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401Multistep manufacturing processes
    • H01L29/4011Multistep manufacturing processes for data storage electrodes
    • H01L29/40114Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/788Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881Programmable transistors with only two possible levels of programmation
    • H01L29/7883Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2216/00Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/02Structural aspects of erasable programmable read-only memories
    • G11C2216/08Nonvolatile memory wherein data storage is accomplished by storing relatively few electrons in the storage layer, i.e. single electron memory
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/962Quantum dots and lines
EP98123279A 1997-12-12 1998-12-07 Verwendung der Antikörper - Antigen Wechselwirkung zur Herstellung eines Metallfilmmusters Withdrawn EP0926260A3 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP34238697 1997-12-12
JP34238697 1997-12-12

Publications (2)

Publication Number Publication Date
EP0926260A2 EP0926260A2 (de) 1999-06-30
EP0926260A3 true EP0926260A3 (de) 2001-04-11

Family

ID=18353333

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98123279A Withdrawn EP0926260A3 (de) 1997-12-12 1998-12-07 Verwendung der Antikörper - Antigen Wechselwirkung zur Herstellung eines Metallfilmmusters

Country Status (3)

Country Link
US (2) US6303516B1 (de)
EP (1) EP0926260A3 (de)
KR (1) KR100347624B1 (de)

Families Citing this family (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6713309B1 (en) 1999-07-30 2004-03-30 Large Scale Proteomics Corporation Microarrays and their manufacture
US6653151B2 (en) 1999-07-30 2003-11-25 Large Scale Proteomics Corporation Dry deposition of materials for microarrays using matrix displacement
WO2001068513A1 (fr) 2000-03-16 2001-09-20 Matsushita Electric Industrial Co., Ltd. Procede destine a usiner une microstructure avec precision
US6400610B1 (en) * 2000-07-05 2002-06-04 Motorola, Inc. Memory device including isolated storage elements that utilize hole conduction and method therefor
WO2002103753A2 (en) * 2000-11-01 2002-12-27 Myrick James J Nanoelectronic interconnection and addressing
US6534782B1 (en) 2000-11-22 2003-03-18 Battelle Memorial Institute Structure having spatially separated photo-excitable electron-hole pairs and method of manufacturing same
KR100597014B1 (ko) * 2001-01-10 2006-07-06 재단법인서울대학교산학협력재단 물질의 결정 구조를 이용한 패턴 형성 방법 및 그 구조를갖는 기능성 소자
KR100455282B1 (ko) * 2001-01-11 2004-11-08 삼성전자주식회사 램 및 롬 기능을 갖는 단일 트랜지스터를 포함하는 메모리소자와 그 동작 및 제조방법
TW569195B (en) * 2001-01-24 2004-01-01 Matsushita Electric Ind Co Ltd Micro-particle arranged body, its manufacturing method, and device using the same
KR100462055B1 (ko) * 2001-04-03 2004-12-17 재단법인서울대학교산학협력재단 물질의 결정구조를 이용한 패턴 형성 방법 및 장치
EP1262489A1 (de) * 2001-05-14 2002-12-04 Matsushita Electric Industrial Co., Ltd. Komplex aus rekombinantem Ferritin und einem Edelmetall sowie dieses Ferritin kodierende DNA
KR20020091982A (ko) * 2001-06-01 2002-12-11 삼성전자 주식회사 얕은 트렌치 소자분리 구조를 가지는 비휘발성 메모리소자 및 그 제조방법
EP1278234B1 (de) * 2001-07-19 2012-01-11 STMicroelectronics Srl MOS Transistor und Verfahren zu dessen Herstellung
JP2003068891A (ja) * 2001-08-24 2003-03-07 Hitachi Ltd 半導体記憶素子、半導体装置及びその制御方法
US7985590B2 (en) * 2002-09-26 2011-07-26 Science Application International Corporation Method and system for detection using nanodot taggants
US7035308B1 (en) 2002-10-28 2006-04-25 Science Applications International Corporation Method and system for countering laser technology
US7022571B2 (en) * 2003-05-01 2006-04-04 United Microelectronics Corp. Quantum structure and forming method of the same
JP2004349341A (ja) * 2003-05-20 2004-12-09 Sharp Corp 半導体記憶素子、半導体装置およびそれらの製造方法、携帯電子機器並びにicカード
DE10326805B4 (de) * 2003-06-13 2007-02-15 Infineon Technologies Ag Herstellungsverfahren für nichtflüchtige Speicherzellen
US6927136B2 (en) * 2003-08-25 2005-08-09 Macronix International Co., Ltd. Non-volatile memory cell having metal nano-particles for trapping charges and fabrication thereof
US7255912B2 (en) 2003-09-23 2007-08-14 Eastman Kodak Company Antistatic conductive grid pattern with integral logo
US7083885B2 (en) 2003-09-23 2006-08-01 Eastman Kodak Company Transparent invisible conductive grid
US7153620B2 (en) 2003-09-23 2006-12-26 Eastman Kodak Company Transparent invisible conductive grid
US7253104B2 (en) * 2003-12-01 2007-08-07 Micron Technology, Inc. Methods of forming particle-containing materials
JP2005251990A (ja) * 2004-03-04 2005-09-15 Nec Electronics Corp 不揮発性半導体記憶装置
JP3822229B2 (ja) 2004-05-27 2006-09-13 松下電器産業株式会社 基板上への微粒子配列体の形成方法
US7335556B2 (en) * 2004-06-14 2008-02-26 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
WO2006064640A1 (ja) * 2004-12-14 2006-06-22 Matsushita Electric Industrial Co., Ltd. フェリチンの選択的配置方法
JP4585523B2 (ja) * 2004-12-28 2010-11-24 独立行政法人科学技術振興機構 自己組織化材料または微粒子を基板上に固定化する方法、および当該方法を用いて作製した基板
KR100647318B1 (ko) * 2005-02-03 2006-11-23 삼성전자주식회사 비휘발성 메모리 소자 및 그 제조방법
KR100668330B1 (ko) * 2005-02-21 2007-01-12 삼성전자주식회사 비휘발성 메모리 소자 및 그 제조방법
JP5238994B2 (ja) * 2005-04-11 2013-07-17 国立大学法人 奈良先端科学技術大学院大学 薄膜トランジスタ及びその製造方法
WO2006125825A2 (en) * 2005-05-27 2006-11-30 The Provost Fellows And Scholars Of The College Of The Holy And Undivided Trinity Of Queen Elizabeth Near Dublin Method of forming conducting nanowires
US7368370B2 (en) * 2005-06-15 2008-05-06 The University Of Connecticut Site-specific nanoparticle self-assembly
CN100423213C (zh) * 2005-08-05 2008-10-01 旺宏电子股份有限公司 非易失性存储器的操作方法
KR100683854B1 (ko) * 2005-09-06 2007-02-15 삼성전자주식회사 비휘발성 기억 소자의 형성 방법
US20070118861A1 (en) * 2005-11-21 2007-05-24 General Instrument Corporation System and method for delivering graphics received through a cable television system to a digital television
JP2007158176A (ja) * 2005-12-07 2007-06-21 Hitachi Ltd 半導体記憶装置およびその製造方法
WO2007091364A1 (ja) * 2006-02-06 2007-08-16 Matsushita Electric Industrial Co., Ltd. 単電子半導体素子の製造方法
KR100884240B1 (ko) * 2006-10-20 2009-02-17 삼성전자주식회사 반도체 소자 및 그 형성 방법
KR100858085B1 (ko) * 2006-12-18 2008-09-10 삼성전자주식회사 나노닷을 전하 트랩 사이트로 이용하는 전하 트랩형 메모리소자
US7787304B2 (en) * 2007-11-01 2010-08-31 Jonker Llc Method of making integrated circuit embedded with non-volatile one-time-programmable and multiple-time programmable memory
US7787295B2 (en) * 2007-11-14 2010-08-31 Jonker Llc Integrated circuit embedded with non-volatile multiple-time programmable memory having variable coupling
US7876615B2 (en) * 2007-11-14 2011-01-25 Jonker Llc Method of operating integrated circuit embedded with non-volatile programmable memory having variable coupling related application data
US8580622B2 (en) * 2007-11-14 2013-11-12 Invensas Corporation Method of making integrated circuit embedded with non-volatile programmable memory having variable coupling
US8388851B2 (en) 2008-01-08 2013-03-05 Micron Technology, Inc. Capacitor forming methods
US8305805B2 (en) * 2008-11-03 2012-11-06 Invensas Corporation Common drain non-volatile multiple-time programmable memory
US8203861B2 (en) * 2008-12-30 2012-06-19 Invensas Corporation Non-volatile one-time—programmable and multiple-time programmable memory configuration circuit
JP2011071240A (ja) * 2009-09-24 2011-04-07 Toshiba Corp 半導体記憶装置、及びその製造方法
US8808558B2 (en) * 2010-02-04 2014-08-19 National Sun Yat-Sen University System and method for alignment of nanoparticles on substrate
US10629752B1 (en) * 2018-10-11 2020-04-21 Applied Materials, Inc. Gate all-around device
DE102020129558A1 (de) 2020-11-10 2022-05-12 Rheinisch-Westfälische Technische Hochschule (Rwth) Aachen Bauteil zur Messung elektrischer Ladung

Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4852062A (en) * 1987-09-28 1989-07-25 Motorola, Inc. EPROM device using asymmetrical transistor characteristics
US4882707A (en) * 1986-10-27 1989-11-21 Kabushiki Kaisha Toshiba Non-volatile semi-conductor memory device with double gate structure
EP0389721A2 (de) * 1989-03-27 1990-10-03 Ict International Cmos Technology, Inc. Flash-EPROM-Zelle und Verfahren zu ihrer Herstellung
EP0489465A2 (de) * 1990-12-05 1992-06-10 Akzo Nobel N.V. Bindung von Liganden an Gold
JPH05121763A (ja) * 1991-10-30 1993-05-18 Rohm Co Ltd 半導体記憶装置の製造方法
JPH06120481A (ja) * 1991-05-23 1994-04-28 Canon Inc 量子箱半導体素子
JPH07115142A (ja) * 1993-10-19 1995-05-02 Matsushita Electric Ind Co Ltd 不揮発性半導体記憶装置とその製造方法
US5459091A (en) * 1993-10-12 1995-10-17 Goldstar Electron Co., Ltd. Method for fabricating a non-volatile memory device
WO1996007487A1 (en) * 1994-09-10 1996-03-14 The University Of Liverpool Method of synthesising materials having controlled electronic, magnetic and/or optical properties
US5519653A (en) * 1994-03-11 1996-05-21 Thomas; Mammen Channel accelerated carrier tunneling-(CACT) method for programming memories
US5591652A (en) * 1993-11-08 1997-01-07 Sharp Kabushiki Kaisha Method of manufacturing flash memory with inclined channel region
EP0763856A1 (de) * 1995-09-11 1997-03-19 Matsushita Electronics Corporation Halbleiterspeicheranordnung und Verfahren zur Steuerung
EP0788149A1 (de) * 1996-02-05 1997-08-06 Hitachi Europe Limited Verfahren zum Ablegen von nanometrischen Partikeln
US5687113A (en) * 1994-03-30 1997-11-11 Sgs-Thomson Microelectronics S.A. Electrically programmable memory cell
JPH10144877A (ja) * 1996-09-13 1998-05-29 Toshiba Corp メモリセル
EP0881691A2 (de) * 1997-05-30 1998-12-02 Matsushita Electric Industrial Co., Ltd. Anordnung mit Quanten-Schachteln

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5925525A (en) * 1989-06-07 1999-07-20 Affymetrix, Inc. Method of identifying nucleotide differences
US5445679A (en) * 1992-12-23 1995-08-29 Memc Electronic Materials, Inc. Cleaning of polycrystalline silicon for charging into a Czochralski growing process
JP3613594B2 (ja) 1993-08-19 2005-01-26 株式会社ルネサステクノロジ 半導体素子およびこれを用いた半導体記憶装置
US5869127A (en) * 1995-02-22 1999-02-09 Boston Scientific Corporation Method of providing a substrate with a bio-active/biocompatible coating
US5743998A (en) * 1995-04-19 1998-04-28 Park Scientific Instruments Process for transferring microminiature patterns using spin-on glass resist media
JPH09213927A (ja) 1996-02-05 1997-08-15 Toshiba Corp 微小金属ドットの製造方法および微小金属ドット製造装置
JPH10121763A (ja) 1996-10-22 1998-05-12 Fuji Hensokuki Co Ltd 格納システム
US5908608A (en) * 1996-11-08 1999-06-01 Spectra Science Corporation Synthesis of metal chalcogenide quantum
JPH10199813A (ja) * 1997-01-07 1998-07-31 Mitsubishi Electric Corp 半導体装置の製造方法および半導体装置
US5888885A (en) * 1997-05-14 1999-03-30 Lucent Technologies Inc. Method for fabricating three-dimensional quantum dot arrays and resulting products

Patent Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4882707A (en) * 1986-10-27 1989-11-21 Kabushiki Kaisha Toshiba Non-volatile semi-conductor memory device with double gate structure
US4852062A (en) * 1987-09-28 1989-07-25 Motorola, Inc. EPROM device using asymmetrical transistor characteristics
EP0389721A2 (de) * 1989-03-27 1990-10-03 Ict International Cmos Technology, Inc. Flash-EPROM-Zelle und Verfahren zu ihrer Herstellung
EP0489465A2 (de) * 1990-12-05 1992-06-10 Akzo Nobel N.V. Bindung von Liganden an Gold
JPH06120481A (ja) * 1991-05-23 1994-04-28 Canon Inc 量子箱半導体素子
JPH05121763A (ja) * 1991-10-30 1993-05-18 Rohm Co Ltd 半導体記憶装置の製造方法
US5874761A (en) * 1991-10-30 1999-02-23 Rohm Co., Ltd. Semiconductor memory device with three-dimensional cluster distribution
US5459091A (en) * 1993-10-12 1995-10-17 Goldstar Electron Co., Ltd. Method for fabricating a non-volatile memory device
JPH07115142A (ja) * 1993-10-19 1995-05-02 Matsushita Electric Ind Co Ltd 不揮発性半導体記憶装置とその製造方法
US5591652A (en) * 1993-11-08 1997-01-07 Sharp Kabushiki Kaisha Method of manufacturing flash memory with inclined channel region
US5519653A (en) * 1994-03-11 1996-05-21 Thomas; Mammen Channel accelerated carrier tunneling-(CACT) method for programming memories
US5687113A (en) * 1994-03-30 1997-11-11 Sgs-Thomson Microelectronics S.A. Electrically programmable memory cell
WO1996007487A1 (en) * 1994-09-10 1996-03-14 The University Of Liverpool Method of synthesising materials having controlled electronic, magnetic and/or optical properties
EP0763856A1 (de) * 1995-09-11 1997-03-19 Matsushita Electronics Corporation Halbleiterspeicheranordnung und Verfahren zur Steuerung
EP0788149A1 (de) * 1996-02-05 1997-08-06 Hitachi Europe Limited Verfahren zum Ablegen von nanometrischen Partikeln
JPH10144877A (ja) * 1996-09-13 1998-05-29 Toshiba Corp メモリセル
EP0881691A2 (de) * 1997-05-30 1998-12-02 Matsushita Electric Industrial Co., Ltd. Anordnung mit Quanten-Schachteln

Non-Patent Citations (12)

* Cited by examiner, † Cited by third party
Title
ANDRES R P ET AL: "SELF-ASSEMBLY OF A TWO-DIMENSIONAL SUPERLATTICE OF MOLECULARLY LINKED METAL CLUSTERS", SCIENCE,US,AMERICAN ASSOCIATION FOR THE ADVANCEMENT OF SCIENCE,, vol. 273, 20 September 1996 (1996-09-20), pages 1690 - 1693, XP002038007, ISSN: 0036-8075 *
GEOFFREY A OZIN: "NANOSCHEMISTRY: SYNTHESIS IN DIMINISHING DEMENSIONS", ADVANCED MATERIALS,DE,VCH VERLAGSGESELLSCHAFT, WEINHEIM, vol. 4, no. 10, 1 October 1992 (1992-10-01), pages 612 - 649, XP000321600, ISSN: 0935-9648 *
HARTMANN A ET AL: "DIRECT IMMOBILIZATION OF ANTIBODIES ON PHTHALOCYANINATO- POLYSILOXANE PHOTOPOLYMERS", THIN SOLID FILMS,CH,ELSEVIER-SEQUOIA S.A. LAUSANNE, vol. 245, no. 1/02, 1 June 1994 (1994-06-01), pages 206 - 210, XP000453829, ISSN: 0040-6090 *
NAKAJIMA A ET AL: "ROOM TEMPERATURE OPERATION OF SI SINGLE-ELECTRON MEMORY WITH SELF- ALIGNED FLOATING DOT GATE", INTERNATIONAL ELECTRON DEVICES MEETING (IEDM),US,NEW YORK, IEEE, 8 December 1996 (1996-12-08), pages 952 - 954, XP000753863, ISBN: 0-7803-3394-2 *
PATENT ABSTRACTS OF JAPAN vol. 017, no. 484 (E - 1426) 2 September 1993 (1993-09-02) *
PATENT ABSTRACTS OF JAPAN vol. 018, no. 406 (E - 1585) 28 July 1994 (1994-07-28) *
PATENT ABSTRACTS OF JAPAN vol. 1995, no. 08 29 September 1995 (1995-09-29) *
PATENT ABSTRACTS OF JAPAN vol. 1998, no. 10 31 August 1998 (1998-08-31) *
SASABE H ET AL: "TWO-DIMENSIONAL MOLECULAR PACKING OF PROTEINS", THIN SOLID FILMS,CH,ELSEVIER-SEQUOIA S.A. LAUSANNE, vol. 216, no. 1, 28 August 1992 (1992-08-28), pages 99 - 104, XP000327794, ISSN: 0040-6090 *
TIWARI S ET AL: "SINGLE CHARGE AND CONFINEMENT EFFECTS IN NANO-CRYSTAL MEMORIES", APPLIED PHYSICS LETTERS,US,AMERICAN INSTITUTE OF PHYSICS. NEW YORK, vol. 69, no. 9, 26 August 1996 (1996-08-26), pages 1232 - 1234, XP000614461, ISSN: 0003-6951 *
WANG J Y ET AL: "FORMATION OF NANOSCALE SIZE CADMIUM SULFIDE WITHIN A CHANNEL PROTEIN MONOLAYER", THIN SOLID FILMS,CH,ELSEVIER-SEQUOIA S.A. LAUSANNE, vol. 242, no. 1/02, 15 April 1994 (1994-04-15), pages 127 - 131, XP000441311, ISSN: 0040-6090 *
WELSER J J ET AL: "ROOM TEMPERATURE OPERATION OF A QUANTUM-DOT FLASH MEMORY", IEEE ELECTRON DEVICE LETTERS,US,IEEE INC. NEW YORK, vol. 18, no. 6, 1 June 1997 (1997-06-01), pages 278 - 280, XP000689685, ISSN: 0741-3106 *

Also Published As

Publication number Publication date
KR100347624B1 (ko) 2003-01-24
US6342716B1 (en) 2002-01-29
KR19990062988A (ko) 1999-07-26
EP0926260A2 (de) 1999-06-30
US6303516B1 (en) 2001-10-16

Similar Documents

Publication Publication Date Title
EP0926260A3 (de) Verwendung der Antikörper - Antigen Wechselwirkung zur Herstellung eines Metallfilmmusters
EP1026751A3 (de) Halbleiteranordnung und Verfahren zu ihrer Herstellung
EP0459397A3 (de) Halbleiteranordnung mit einem Graben für die Isolationkomponenten und Verfahren zu deren Herstellung
EP0251280A3 (de) Laserverfahren zur Getterung für Halbleiterscheiben
EP0452921A3 (en) Formation of titanium nitride on semiconductor wafer by reaction of titanium with nitrogen-bearing gas in an integrated processing system
EP0926725A3 (de) Defekt bewirktes, vergrabenes Oxid (DIBOX) für Durchsatz-SOI
EP0342796A3 (de) Dünnschichttransistor
EP0782181A3 (de) Verfahren zur Herstellung eines VDMOS mit einer Abschluss-Struktur
EP0395084A3 (de) Herstellungsverfahren einer logischen Halbleiterschaltung mit nichtflüchtigem Speicher
ATE235514T1 (de) Monoklonaler anti-idiotypischer antikörper 3h1 aus maus
EP0373832A3 (de) Halbleitervorrichtung und photoelektrischer Wandler, welcher diese Vorrichtung verwendet
EP0834910A3 (de) Verfahren und Vorrichtung zur Nassbehandlung von Halbleiterwafern
EP0997996A3 (de) Halbleitervorrichtung und Herstellungsverfahren
EP1003227A3 (de) Halbleitervorrichtung
EP0905774A3 (de) Weiche Passivierungsschicht in der Halbleiterfabrikation
EP0942461A3 (de) Veringerung von schwarzem Silizium in der Halbleiterfabrikation
JPS54104783A (en) Manufacture for mos type semiconductor device
JPS5464983A (en) Manufacture of semiconductor device
JPS6450426A (en) Surface treatment
JP2890617B2 (ja) 薄膜の形成方法
EP0884768A3 (de) Feine Struktur und Verfahren zu ihrer Herstellung
EP0911869A3 (de) Nieder-Temperatur Verfahren zur Bildung von einer regelmässigen dünnen Oxydschicht
JPS57198659A (en) Semiconductor device
Nishimura et al. X-ray replication of masks by synchrotron radiation of INS-ES
JPS62265763A (ja) 半導体集積回路装置

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): DE FR GB

AX Request for extension of the european patent

Free format text: AL;LT;LV;MK;RO;SI

RIN1 Information on inventor provided before grant (corrected)

Inventor name: YAMASHITA, ICHIRO

Inventor name: ENDO, MASAYUKI

Inventor name: ADACHI, KAZUYASU

Inventor name: YUKI, KOICHIRO

Inventor name: ARAKI, KIYOSHI

Inventor name: MORIMOTO, KIYOSHI

Inventor name: MORITA, KIYOYUKI

RIC1 Information provided on ipc code assigned before grant

Free format text: 7C 23C 18/00 A, 7H 01L 21/28 B, 7H 01L 21/288 B, 7H 01L 51/20 B

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE

AX Request for extension of the european patent

Free format text: AL;LT;LV;MK;RO;SI

17P Request for examination filed

Effective date: 20010625

AKX Designation fees paid

Free format text: DE FR GB

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN

18W Application withdrawn

Effective date: 20050617