EP0898308A2 - Procédé de fabrication d'une interconnexion métallique dans un dispositif à semiconducteurs - Google Patents
Procédé de fabrication d'une interconnexion métallique dans un dispositif à semiconducteurs Download PDFInfo
- Publication number
- EP0898308A2 EP0898308A2 EP98302581A EP98302581A EP0898308A2 EP 0898308 A2 EP0898308 A2 EP 0898308A2 EP 98302581 A EP98302581 A EP 98302581A EP 98302581 A EP98302581 A EP 98302581A EP 0898308 A2 EP0898308 A2 EP 0898308A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- layer
- metal
- aluminum
- liner
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 311
- 239000002184 metal Substances 0.000 title claims abstract description 311
- 238000000034 method Methods 0.000 title claims abstract description 167
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 230000004888 barrier function Effects 0.000 claims abstract description 70
- 230000002821 anti-nucleating effect Effects 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 229910052782 aluminium Inorganic materials 0.000 claims description 83
- 239000010949 copper Substances 0.000 claims description 80
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 75
- 229910052802 copper Inorganic materials 0.000 claims description 66
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 56
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 20
- 238000005229 chemical vapour deposition Methods 0.000 claims description 15
- 239000007789 gas Substances 0.000 claims description 15
- 229910001092 metal group alloy Inorganic materials 0.000 claims description 15
- 229910052715 tantalum Inorganic materials 0.000 claims description 14
- 239000010936 titanium Substances 0.000 claims description 14
- 229910044991 metal oxide Inorganic materials 0.000 claims description 13
- 150000004706 metal oxides Chemical class 0.000 claims description 13
- 238000005546 reactive sputtering Methods 0.000 claims description 12
- 229910052719 titanium Inorganic materials 0.000 claims description 12
- 239000002243 precursor Substances 0.000 claims description 11
- 238000004544 sputter deposition Methods 0.000 claims description 11
- 229910000838 Al alloy Inorganic materials 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 10
- 229910052786 argon Inorganic materials 0.000 claims description 10
- 229910052721 tungsten Inorganic materials 0.000 claims description 10
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 9
- 229910052737 gold Inorganic materials 0.000 claims description 9
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical compound [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 7
- 239000010937 tungsten Substances 0.000 claims description 7
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- 239000012159 carrier gas Substances 0.000 claims description 6
- 229910052749 magnesium Inorganic materials 0.000 claims description 6
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 6
- 229910052709 silver Inorganic materials 0.000 claims description 6
- 238000006557 surface reaction Methods 0.000 claims description 6
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 6
- 229910000086 alane Inorganic materials 0.000 claims description 5
- 239000012298 atmosphere Substances 0.000 claims description 5
- 229910052732 germanium Inorganic materials 0.000 claims description 5
- 229910052750 molybdenum Inorganic materials 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical group [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- VOITXYVAKOUIBA-UHFFFAOYSA-N triethylaluminium Chemical compound CC[Al](CC)CC VOITXYVAKOUIBA-UHFFFAOYSA-N 0.000 claims description 4
- MCULRUJILOGHCJ-UHFFFAOYSA-N triisobutylaluminium Chemical compound CC(C)C[Al](CC(C)C)CC(C)C MCULRUJILOGHCJ-UHFFFAOYSA-N 0.000 claims description 4
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 claims description 4
- RTAKQLTYPVIOBZ-UHFFFAOYSA-N tritert-butylalumane Chemical compound CC(C)(C)[Al](C(C)(C)C)C(C)(C)C RTAKQLTYPVIOBZ-UHFFFAOYSA-N 0.000 claims description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 3
- -1 di-methyl ethyl Chemical group 0.000 claims description 3
- TUTOKIOKAWTABR-UHFFFAOYSA-N dimethylalumane Chemical compound C[AlH]C TUTOKIOKAWTABR-UHFFFAOYSA-N 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- QUSNBJAOOMFDIB-UHFFFAOYSA-N monoethyl amine Natural products CCN QUSNBJAOOMFDIB-UHFFFAOYSA-N 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 238000007747 plating Methods 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 230000001419 dependent effect Effects 0.000 claims 2
- LIWAQLJGPBVORC-UHFFFAOYSA-N ethylmethylamine Chemical compound CCNC LIWAQLJGPBVORC-UHFFFAOYSA-N 0.000 claims 2
- 238000005121 nitriding Methods 0.000 claims 2
- 229910045601 alloy Inorganic materials 0.000 claims 1
- 239000000956 alloy Substances 0.000 claims 1
- CWEHKOAQFGHCFQ-UHFFFAOYSA-N methylalumane Chemical compound [AlH2]C CWEHKOAQFGHCFQ-UHFFFAOYSA-N 0.000 claims 1
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- 239000000463 material Substances 0.000 description 21
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 17
- 239000012535 impurity Substances 0.000 description 10
- 239000010931 gold Substances 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 4
- 239000012495 reaction gas Substances 0.000 description 4
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 3
- 125000004429 atom Chemical group 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 3
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 229910001882 dioxygen Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 125000004430 oxygen atom Chemical group O* 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- 229910018182 Al—Cu Inorganic materials 0.000 description 1
- 229910018594 Si-Cu Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910008465 Si—Cu Inorganic materials 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- DAZXVJBJRMWXJP-UHFFFAOYSA-N n,n-dimethylethylamine Chemical compound CCN(C)C DAZXVJBJRMWXJP-UHFFFAOYSA-N 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000012421 spiking Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
Definitions
- the present invention relates to a method of manufacturing an integrated semiconductor circuit, and more particularly, to a method for forming a metal interconnection in a semiconductor device.
- a semiconductor device includes transistors, resistors and capacitors.
- a metal interconnection is required for realizing the semiconductor device on a semiconductor substrate.
- the metal interconnection which transmits electric signals is required to have low electric resistance, and be economical and reliable.
- Aluminum has been widely used as a metal interconnection.
- a selective chemical vapor deposition (CVD) process has been proposed as a method for completely filling the contact hole having a high aspect ratio with the metal interconnection.
- the selective CVD process uses the characteristic in which a growth rate of the metal layer on an insulating layer is different from that on a conductive layer.
- a junction depth of a source/drain region of a transistor is reduced.
- an aluminum layer used as the metal interconnection is penetrated to the shallow source/drain region to be diffused to a semiconductor substrate. to thereby cause a junction spiking phenomenon. Therefore, a method for interposing a barrier metal layer between the aluminum layer and the source/drain region has been used to suppress the reaction of aluminum atoms of the aluminum layer with silicon atoms of the source/drain region. At this time, the barrier metal layer is formed on the entire surface of the resultant structure where the contact hole is formed. Therefore. it is impossible to selectively form the metal interconnection only in the contact hole by selective CVD process since a blanket barrier metal layer is present.
- an interdielectric layer is formed on a semiconductor substrate. Then. a predetermined region of the interdielectric layer is etched. to form an interdielectric layer pattern having a recessed region.
- the recessed region may be a contact hole for exposing the predetermined region of the semiconductor substrate or the groove which is thinner than the thickness of the interdielectric layer.
- the metal interconnection is formed through a damascene process.
- a barrier metal layer i.e., a titanium nitride (TiN) layer. is formed on the entire surface of the resultant structure where the interdielectric layer pattern is formed.
- the recessed region is the contact hole for exposing the predetermined region of the semiconductor substrate, i.e., a source/drain region of a transistor.
- an ohmic metal layer must be formed on the entire surface of the resultant structure where the interdielectric layer pattern is formed. before forming the barrier metal layer.
- the barrier metal layer is annealed at a predetermined temperature if necessary, to fill the grain boundary region of the barrier metal layer with oxygen atoms. This is for preventing the diffusion of silicon atoms of the semiconductor substrate through the barrier metal layer.
- an anti-nucleation layer e.g., an insulating layer is selectively formed only on the barrier metal layer formed on the non-recessed region.
- the insulating layer is for selectively forming a metal interconnection only in the recessed region in a process to be performed later. That is, using a characteristic in which the metal layer is not deposited on the insulating layer, the metal layer used for the metal interconnection is formed by the CVD process.
- the insulating layer is one selected from the group consisting of a metal oxide layer. a metal nitride layer. a SiC layer, a BN layer. a SiN layer, a TaSiO layer and a TiSiO layer.
- the metal oxide layer can be formed by selectively forming a layer having excellent oxidation characteristics. i.e, a metal layer only on the barrier metal layer formed on the non-recessed region, and then exposing the metal layer to air or to O 2 plasma. Also. the metal oxide layer can be formed by loading and oxidizing the resultant structure where the metal layer having excellent oxidation characteristics in a furnace.
- the metal nitride layer e.g.. an aluminum nitride layer may be formed by selectively forming an aluminum layer only on the barrier metal layer formed on the non-recessed region, and then exposing the aluminum layer to N 2 or NH 3 plasma or performing RTP in an atmosphere of NH 3 and/or N 2 .
- a metal layer for forming the metal oxide layer is formed of an Al layer, a Cu layer, a Au layer, a Ag layer. a W layer, a Mo layer, a Ta layer or a Ti layer.
- the metal layer may be formed of a metal alloy film containing one selected from the group consisting of Al, Au, Ag, W, Mo and Ta, and at least one selected from the group consisting of Cu. Si. Ge. Ti and Mg.
- the metal layer may be formed through sputtering. a chemical vapor deposition (CVD) or a plating process. At this time. preferably. the CVD process is performed at a temperature range corresponding to a mass transported region instead of a surface reaction limited region and at a pressure of 5 Torr or higher so that the metal layer is not formed in the recessed region. It is preferable that an argon gas and a hydrogen gas are used for a carrier gas and a reducing gas, respectively. The hydrogen gas may be used as a carrier gas. Also, the sputtering process for forming the metal layer is performed such that atoms sputtered from the target lose directionality to prevent the anti-nucleation layer from being formed in the recessed region. That is, it is preferable that the sputtering process for forming the anti-nucleation layer is performed at several mTorr using a DC magnetron sputtering apparatus without a collimator to utilize the poor step-coverage.
- CVD chemical vapor
- the anti-nucleation layer may be formed through a reactive sputtering process.
- the metal oxide layer may be formed through a O 2 reactive sputtering process.
- the metal nitride layer i.e., an aluminum nitride layer may be formed through a N 2 reactive sputtering process.
- the anti-nucleation layer for exposing the barrier metal layer formed in the recessed region has characteristics of the insulating layer. so that a metal layer, i.e., an aluminum layer or a copper layer may be selectively formed in the recessed region. This is because the time required for forming metal nuclei on the anti-nucleation layer being an insulating layer is several tens through several hundreds times longer than the time required for forming metal nuclei on the barrier metal layer being a metal layer. Subsequently, a metal plug for filling a region surrounded by the exposed barrier metal layer, e.g., an aluminum plug, is formed through a selective MOCVD process. The metal plug may be formed of Cu or W instead of Al.
- the aluminum plug is formed through a selective MOCVD process using a precursor containing Al. It is also preferable that the selective MOCVD process for forming the aluminum plug is performed at a temperature corresponding to a surface reaction limited region of aluminum. e.g., at a temperature lower than 300°C. It is preferable that the precursor containing the aluminum is one selected from the group consisting of tri-methyl aluminum. tri-ethyl aluminum. tri-iso butyl aluminum, di-methyl aluminum hydride, di-methyl ethyl amine alane, and tri-tertiary butyl aluminum. Also. the selective MOCVD process uses an argon carrier gas and a hydrogen reducing gas.
- a metal liner may be selectively formed on a surface of the exposed barrier metal layer.
- the metal liner is formed of one selected from the group consisting of Al. Cu, Au, Ag, W, Mo and Ta.
- the metal liner may be formed of a metal alloy film containing one selected from the group consisting of Al. Ag, Au, W. Mo and Ta, and at least one selected from the group consisting of Cu, Si, Ge, Ti and Mg. It is preferable that the metal liner. e.g., a Cu liner is formed by a selective CVD process, e.g., selective MOCVD process.
- the selective MOCVD process for forming the Cu liner is performed using a metal source containing Cu, e.g., Cu +1 (hfac)TMVS.
- a metal source containing Cu e.g., Cu +1 (hfac)TMVS.
- the metal plug and Cu liner are mixed during an annealing process. to thereby form a metal interconnection containing copper. Accordingly. the reliability of the metal interconnection. i.e., an electromigration characteristic thereof is improved.
- the metal plug i.e., the aluminum plug overgrows
- a sharp protrusion may be formed on a surface of the metal plug.
- the metal plug it is preferable that the metal plug is planarized through a sputter etch process or a chemical mechanical polishing (CMP) process.
- CMP chemical mechanical polishing
- the above-described process is of a process of forming a damascene interconnection. If necessary, the metal interconnection may be formed by additionally forming a metal layer for covering the planarized metal plug, i.e., an aluminum layer, a tungsten layer. a copper layer or an aluminum alloy layer.
- an interdielectric layer pattern having a recessed region, a barrier metal layer pattern and an anti-nucleation layer are formed in the same manner as the first embodiment. to thereby expose the barrier metal layer formed on the sidewalls and bottom of the recessed region.
- an ohmic metal layer may be formed on the entire surface of the resultant structure where the interdielectric layer pattern is formed, before forming the barrier metal layer, and the barrier metal layer may be annealed after forming the barrier metal layer. Then, the metal liner is selectively formed on a surface of the exposed barrier metal layer.
- the metal liner may be a single metal liner or a double metal liner obtained by sequentially forming first and second metal liners. It is preferable that the single metal liner is a metal layer formed of one selected from the group consisting of Cu. Al. Ag, Au, W. Mo and Ta. Also. the single metal liner may be a metal alloy layer containing one selected from the group consisting of Al, Au. Ag, W, Mo and Ta, and at least one selected from the group consisting of Cu, Si. Ge, Ti and Mg. It is preferable that the first and second metal liners of the double metal liner are a copper liner and an aluminum liner, respectively. The copper liner is formed through a selective MOCVD process using a precursor containing Cu.
- the aluminum liner is formed through a selective MOCVD using a precursor containing Al as a metal source.
- the copper liner and the aluminum liner are formed at temperature ranges corresponding to surface reaction limited regions of Cu and Al, respectively.
- the precursor containing Al is one selected from the group consisting of tri-methyl aluminum, tri-ethyl aluminum, tri-iso butyl aluminum. di-methyl aluminum hydride. di-methyl ethyl amine alane, and tri-tertiary butyl aluminum.
- a metal layer e.g., an aluminum layer, a W layer, a Cu layer or an Al alloy layer is formed on the resultant structure where the metal liner is formed, through a combination of CVD and sputtering process.
- the metal layer is retlowed at 350 ⁇ 500°C to form a planarized metal layer for completely filling the region surrounded by the metal liner.
- the planarized metal layer is changed to a metal alloy layer in which the metal liner. e.g., the Cu liner and the metal layer are mixed during the reflow process. Accordingly, the reliability of the metal interconnection. i.e., an electromigration characteristic. may be improved.
- the anti-nucleation layer is selectively formed only on the barrier metal layer formed on the non-recessed region, to thereby selectively form the metal plug or the metal liner in the recessed region and further form the metal interconnection for completely filling a contact hole and a groove having a high aspect ratio.
- reference character 'a' indicates a contact hole region
- reference character 'b' indicates a groove region where a damascene metal interconnection is formed.
- the thickness of layers and regions are exaggerated for clarity.
- FIG. 1 is a sectional view for illustrating a step of forming an interdielectric layer pattern 105 having a recessed region and a barrier metal layer 109.
- the recessed region may be a contact hole for exposing a predetermined region of a semiconductor substrate. i.e.. an impurity layer, or a groove having a depth which is less than the thickness of the interdielectric layer.
- an impurity layer 103 doped with an N-type or P-type impurity is formed on a surface of contact hole region 'a' of the semiconductor substrate 101, and an interdielectric layer.
- a borophosphosilicate glass layer or an undoped silicon oxide layer is formed on the entire surface of the resultant structure where the impurity layer 103 is formed.
- the interdielectric layer on the contact hole region 'a' is etched to form a contact hole for exposing the impurity layer 103.
- a groove for forming the damascene interconnection is obtained by etching the interdielectric layer on the groove region 'b' to a predetermined depth. At this time. the depth of the groove is less than the thickness of the interdielectric layer.
- an ohmic metal layer 107 and a barrier metal layer 109 are sequentially formed on the entire surface of the resultant structure where the recessed region is formed.
- the ohmic metal layer 107 and the barrier metal layer 109 are formed of a titanium layer and a titanium nitride layer. respectively.
- the barrier metal layer 109 is treated at a predetermined temperature, to fill a grain boundary region of the barrier metal layer with oxygen atoms. which is a stuffing process.
- metal atoms of the ohmic metal layer 107 react with silicon atoms of the impurity layer 103 to form a metal silicide layer.
- the barrier metal layer 109 is annealed.
- the contact resistance is improved due to a metal silicide layer formed between the impurity layer 103 and the barrier metal layer 109. and a diffusion phenomenon of silicon atoms in the impurity layer 103 and aluminum atoms diffusing in the metal layer to be formed in a subsequent process may be suppressed by the stuffed barrier metal layer 109. Accordingly. in the case of forming only damascene interconnection. a process of forming the ohmic metal layer 107 and a process of annealing the barrier metal layer 109 can be omitted. The process of annealing the barrier metal layer 109 is performed at 400 ⁇ 550°C and N 2 atmosphere for 30 - 60 minutes, or at 650 ⁇ 850°C and NH 3 atmosphere through rapid thermal processing (RTP). At this time, the RTP is, preferably, performed for 30 - 120 seconds.
- RTP rapid thermal processing
- FIG. 2 is a sectional view for illustrating a step of forming a copper layer 110, an anti-nucleation layer 113 and a metal liner 115.
- the copper layer 110 is formed on the entire surface of the annealed barrier metal layer 109 to a thickness of 10 ⁇ 300 ⁇ .
- a material layer 111 of 20 ⁇ 300 ⁇ obtained through a physical vapor deposition process, ( a sputtering process), i.e., an aluminum layer. a titanium layer or a tantalum layer is formed on the resultant structure where the copper layer 110 is formed.
- a sputtering process i.e., an aluminum layer.
- a titanium layer or a tantalum layer is formed on the resultant structure where the copper layer 110 is formed.
- the material layer 111 is formed using a DC magnetron sputtering apparatus without collimator. Also.
- the DC magnetron sputtering process is performed at 10 ⁇ 30°C and at a pressure of 3 ⁇ 10 mTorr.
- the metal layer is formed using the DC magnetron sputtering apparatus having no collimator at 3 ⁇ 10 mTorr, more preferably, 5 ⁇ 10 mTorr, the directionality of the sputtered metal atoms is lost. to thereby prevent formation of the metal layer in the recessed region.
- the material layer 111 i.e., the metal layer is selectively formed only on the interdielectric layer pattern 105. and the copper layer 110 formed in the recessed region is exposed.
- the semiconductor substrate is cooled to a temperature corresponding to that of a surface reaction limited region, i.e., 10 ⁇ 30°C (in the aluminum layer), preferably, 25°C, to thereby form an aluminum layer.
- a surface reaction limited region i.e. 10 ⁇ 30°C (in the aluminum layer), preferably, 25°C
- the metal layer is formed at a low temperature, the metal layer having a uniform thickness may be obtained even as an ultra thin film of 20 ⁇ or less is formed.
- the material layer 111 may be formed through a chemical vapor deposition process. At this time, it is preferable that the material layer 111 is formed of a metal layer having excellent oxidation characteristics. e.g., an aluminum (Al) layer. a titanium (Ti) layer. or a tantalum (Ta) layer.
- the chemical vapor deposition process for forming the material layer 111 is performed at a temperature corresponding to that of a mass transported region instead of the surface reaction limited region and a pressure of 5 Torr or higher. to prevent formation of the material layer 111 in the recessed region.
- the material layer 111 is formed of the aluminum layer through the chemical vapor deposition process.
- the aluminum layer is formed at a temperature range corresponding to that of the mass transported region of aluminum. i.e., approximately 180°C or higher, the aluminum layer may be prevented from being formed in the recessed region.
- argon and hydrogen are used for a carrier gas and a reducing gas, respectively.
- the material layer 111 may be more selectively formed.
- the aluminum layer used as the material layer 111 is formed to a thickness of 25 ⁇ 100 ⁇ .
- the process of forming the copper layer 110 may be omitted as circumstances may require.
- the material layer 111 is selectively formed only on the barrier metal layer 109 on the interdielectric layer pattern 105.
- the barrier metal layer 109 formed in the recessed region is exposed. Then.
- the resultant structure where the material layer 111 is formed is exposed to air or oxygen plasma and thus the material layer 111 is oxidized, to thereby form an anti-nucleation layer 113.
- a titanium oxide (TiO 2 ) layer or a tantalum oxide (Ta 2 O 5 ) layer At this time. when the material is oxidized by exposure to air, as shown in FIG.2, the material layer 111 may be partially changed to the anti-nucleation layer 113.
- the anti-nucleation layer 113 may be formed of an aluminum nitride layer (AIN).
- the aluminum nitride layer may be formed by exposing the resultant structure where the aluminum layer is selectively formed only on the interdielectric layer pattern 105 in N 2 plasma by applying RTP on the resultant structure in an atmosphere of NH3. It is preferable that the rapid thermal processing (RTP) for forming the aluminum nitride layer is performed at 500 ⁇ 850°C for 30 ⁇ 180 seconds.
- RTP rapid thermal processing
- the anti-nucleation layer 113 i.e., an aluminum oxide layer. an aluminum nitride layer. a titanium oxide layer or a tantalum oxide layer. may be formed through an O 2 reactive sputtering process or N 2 reactive sputtering process.
- the anti-nucleation layer 113 of 20 ⁇ 200 ⁇ is formed on the resultant structure where the barrier metal layer 109 is formed or where the barrier metal layer 109 and the copper layer 110 are formed, through the reactive sputtering process using radio frequency power (RF power).
- RF power radio frequency power
- the anti-nucleation layer 113 functions as a polishing stopper.
- the reactive sputtering process is performed at a pressure of 2 ⁇ 8 mTorr.
- argon gas and oxygen gas are used for the reaction gas and aluminum target is used for a metal target when performing the reactive sputtering process. the aluminum oxide layer is formed.
- argon gas and oxygen gas are used for the reaction gas and a titanium target or a tantalum target is used for a metal target
- the titanium oxide layer or the tantalum oxide layer is formed.
- argon gas and nitrogen gas are used for the reaction gas and the aluminum target is used for the metal target. the aluminum nitride layer is formed.
- the anti-nucleation layer 113 may be formed of a SiC layer.
- the SiC layer is formed through the reactive sputtering process using RF power.
- the argon gas and CH4 gas are used for the reaction gas and the silicon target is used for the target.
- a metal liner 115 i.e., a copper liner. is selectively formed only on a surface of the exposed copper layer 110 or the exposed barrier metal layer 109 to a thickness less than 10 ⁇ .
- the metal liner 115 i.e., the copper liner is not required. Also. according to circumstances, both the copper layer 110 and the metal liner 115 may not be formed.
- the copper liner is formed through a selective MOCVD process using Cu +1 (hfac)TMVS as a metal source. At this time, it is preferable that the selective MOCVD process for forming the copper liner is performed at 100 mTorr ⁇ 10 Torr and 150 ⁇ 350°C.
- the copper layer 110 or the copper liner is formed for improving the reliability of the interconnection including a metal plug to be formed, i.e., an electromigration characteristic of the metal interconnection.
- FIG. 3 is a sectional view for illustrating a step of forming a metal plug 117.
- the metal plug 117 for filling a region surrounded with the metal liner 115. i.e., an aluminum plug. is formed through a selective MOCVD process.
- the selective MOCVD process for forming the aluminum plug is performed using a dimethyl ethyl amine alane (DMEAA) as the metal source, at a deposition temperature of 100 ⁇ 200°C, preferably, 120°C and 0.5 ⁇ 5 Torr. preferably. Torr.
- a bubbler which is a means for supplying the DMEAA being the metal source into a process chamber of the MOCVD apparatus is maintained at room temperature.
- argon gas is used as a gas for transmitting a metal source, i.e., a carrier gas
- hydrogen gas is used as a gas for reducing the metal source. Since a metal nucleation time on the surface of the insulating layer, i.e., the anti-nucleation layer 113, is tens to hundreds times longer than that on a surface of an exposed metal liner 115, a copper layer 110 or a barrier metal layer 109. in the recessed region. the metal plug 117 is selectively formed only in a recessed region.
- the thickness of growth of the metal plug 117 it is preferable to control the thickness of growth of the metal plug 117 to a thickness corresponding to 100 ⁇ 110% of the radius of a hole formed by the metal liner 115, to form the metal plug for completely filling a region surrounded by the metal liner 115.
- the metal plug 117 is formed based on a widest recessed region, the metal plug 117 formed on a narrow recessed region is grown to excess. Accordingly. a protrusion is formed on a surface of the metal plug 117.
- the protrusion may be formed sharply. This is because the aluminum layer is formed in a face centered cubic (FCC) structure.
- the metal plug 117 which is formed of the aluminum layer in the embodiment. may be formed of copper, silver or gold. Also. when a process of forming the copper layer 110 or the copper liner is omitted, it is preferable that the metal plug 117 is formed of aluminum alloy containing copper. e.g.. Al-Si-Cu layer or Al-Cu layer.
- FIG. 4 is a sectional view for illustrating a step of forming a planarized metal plug 117a and an interconnection metal layer 119.
- a protrusion is formed on a surface of the excessively grown metal plug 117
- the protrusion of the metal plug 117 is removed, to form a planarized metal plug 117a.
- a sputter etch process or a chemical mechanical polishing process may be used.
- the metal plug 117 may be planarized by reflowing the metal plug 117, i.e., an aluminum plug, at 350 ⁇ 500°C, preferably, 450°C. for 30 ⁇ 180 seconds. preferably. 60 seconds. At this time.
- the metal plug 117 when the metal plug 117 is formed of other metal layers instead of the aluminum layer, the metal plug is, preferably, reflowed at a temperature of 0.6 x Tm or higher.
- Tm denotes the melting temperature of the metal layer for forming metal plug 117.
- a native oxide layer must not exist on the surface of the metal plug 117 to perform the reflow process. Accordingly, in the case of forming the metal plug 117 using a cluster apparatus including an MOCVD chamber and a sputter chamber, it is preferable that the metal plug 117 is planarized through a reflow process. This is because the resultant structure where the metal plug 117 is formed can be transmitted to a sputter chamber in vacuum.
- the planarized metal plug 117a When a copper liner or a copper layer 110 is formed under the metal plug 117, i.e., the aluminum plug is planarized through the reflow process, the planarized metal plug 117a. i.e., the planarized aluminum plug, includes copper by reaction with a copper liner or a copper layer 110. Accordingly, the reliability of the damascene interconnection composed of the barrier metal layer 109 and the planarized metal plug 117a may be increased. When the metal plug 117 is not grown too large. the step of forming the planarized metal plug 117a may be omitted.
- a metal layer 119 i.e., an aluminum layer, an aluminum alloy layer or a copper layer. is formed on the entire surface of the resultant structure where the planarized metal plug 117a is formed. at 200°C or lower. This is for obtaining a smooth surface morphology and a dense film quality.
- FIG. 5 is a sectional view for illustrating a step of forming a metal alloy layer 119a.
- the step of forming the metal alloy layer 119a is useful for the case of planarizing the metal plug 117 through the sputter etch process or the CMP process or the case ot omitting the step of planarizing the metal plug 117.
- the sputter etch process or the CMP process is performed at 300°C or lower. Accordingly. the metal plug 117 does not react with the copper layer 110 or the copper liner.
- the metal alloy layer 119a i.e., an aluminum alloy layer containing copper may be obtained.
- the metal layer 119 i.e., the aluminum layer. may be additionally formed at 350 ⁇ 500°C, instead of annealing the metal layer 119.
- reference characters 'a' and 'b' indicate a contact region and a groove region, respectively. as in FIG. 1.
- FIG. 6 is a sectional view for illustrating a step of forming an interdielectric layer pattern 205 having a recessed region and a barrier metal layer 209.
- the recessed region may be a contact hole for exposing an impurity layer 203 or a groove less than the thickness of the interdielectric layer.
- the step of forming the interdielectric layer pattern 205 having a recessed region and the barrier metal layer 209. is performed in the same manner as that of the first embodiment. Also. steps of annealing the impurity layer 203 of the contact hole region 'a'. an ohmic metal layer 207 and a barrier metal layer 209 are performed in the same manner as that of the first embodiment.
- the steps of forming the ohmic metal layer 207 and annealing the barrier metal layer 209 may be omitted as in the first embodiment.
- FIG. 7 is a sectional view illustrating a step of forming a copper layer 210, an anti-nucleation layer 213 and a metal liner 218.
- the copper layer 210 and the anti-nucleation layer 213 are formed in the same manner as the first embodiment described with reference to FIG. 2.
- the selectively formed material layer 211 may partially remain as in the first embodiment.
- the metal liner 218 may be a single metal liner, i.e., a copper liner, as in the first embodiment, or a double metal liner obtained by sequentially forming a first metal liner 215 and a second metal liner 217.
- the first and second metal liners 215 and 217 are formed of the copper liner and an aluminum liner. respectively.
- the copper liner is formed through the same process as the method described with reference to FIG. 2, i.e., the selective MOCVD process in which Cu +1 (hfac)TMVS is used for a metal source.
- the aluminum liner being the second metal liner 217 is formed through a selective MOCVD process for forming the metal plug 117 of FIG.
- the thickness of growth of the second metal liner 217 is less than the radius of a hole formed by the first metal liner 215 which is different from the aluminum plug of FIG. 3.
- the process of forming the copper layer 210 may be omitted if necessary.
- the process temperature for selectively forming the copper liner is determined according to the material of the lower layer. i.e., exposed film material in the recessed region.
- the deposition temperature of the copper liner is 0 ⁇ 350°C.
- the copper liner is formed at a pressure of 10 Torr, and the temperature of the metal source, i.e., Cu +1 (hfac)TMVS is maintained at 40 ⁇ 50°C.
- FIG. 8 is a sectional view illustrating a step of forming the metal layer 219.
- the metal layer 219 i.e., an aluminum layer or an aluminum alloy layer. is formed on the entire surface of the resultant structure where the metal liner 218 is formed, through a combination of CVD and sputtering process.
- the aluminum layer or the aluminum alloy layer is formed at a temperature below the reflow temperature. This is for preventing formation voids in the metal layer. during planarizing of the metal layer 219 through a reflow process.
- FIG. 9 is a sectional view illustrating a step of forming a planarized metal alloy layer 219a.
- the resultant structure where the metal layer 219 is formed is annealed at a predetermined temperature to reflow the metal layer 219.
- the annealing temperature of the metal layer 219 formed of an aluminum layer or an aluminum alloy layer is 350 ⁇ 500°C.
- the metal liner 218 and the metal layer 219 are mixed to form the metal alloy layer 219a having a planarized surface.
- the planarized metal alloy layer 219a may be formed through a process of additionally forming the metal layer 219 at 350 ⁇ 500°C instead of the reflow process.
- a process of forming the metal plug during formation of the metal interconnection. which is required for the first embodiment. is not required. Accordingly. the process of planarizing the metal plug may be also omitted.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019970040236A KR100269878B1 (ko) | 1997-08-22 | 1997-08-22 | 반도체소자의금속배선형성방법 |
KR9740236 | 1997-08-22 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0898308A2 true EP0898308A2 (fr) | 1999-02-24 |
EP0898308A3 EP0898308A3 (fr) | 2000-06-21 |
Family
ID=19518206
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP98302581A Ceased EP0898308A3 (fr) | 1997-08-22 | 1998-04-02 | Procédé de fabrication d'une interconnexion métallique dans un dispositif à semiconducteurs |
Country Status (5)
Country | Link |
---|---|
US (1) | US6376355B1 (fr) |
EP (1) | EP0898308A3 (fr) |
JP (1) | JPH1174272A (fr) |
KR (1) | KR100269878B1 (fr) |
TW (1) | TW415058B (fr) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2363678A (en) * | 1999-12-22 | 2002-01-02 | Hyundai Electronics Ind | A Method of using a (hfac)Cu(I)(DMB) precursor to form copper wiring |
GB2397947A (en) * | 1999-12-22 | 2004-08-04 | Hyundai Electronics Ind | Method of using a (hfac)Cu(I)(DMB) precursor to form copper wiring |
US6955983B2 (en) * | 2002-05-30 | 2005-10-18 | Samsung Electronics Co., Ltd. | Methods of forming metal interconnections of semiconductor devices by treating a barrier metal layer |
US7193369B2 (en) | 2002-11-11 | 2007-03-20 | Samsung Electronics Co., Ltd. | Method for generating gas plasma |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6344413B1 (en) * | 1997-12-22 | 2002-02-05 | Motorola Inc. | Method for forming a semiconductor device |
US6555455B1 (en) * | 1998-09-03 | 2003-04-29 | Micron Technology, Inc. | Methods of passivating an oxide surface subjected to a conductive material anneal |
US7381638B1 (en) * | 1999-06-09 | 2008-06-03 | National Semiconductor Corporation | Fabrication technique using sputter etch and vacuum transfer |
DE19959711A1 (de) * | 1999-12-10 | 2001-06-21 | Infineon Technologies Ag | Verfahren zur Herstellung einer strukturierten Metallschicht |
US6602782B2 (en) * | 2000-05-31 | 2003-08-05 | Samsung Electronics Co., Ltd. | Methods for forming metal wiring layers and metal interconnects and metal interconnects formed thereby |
KR100604805B1 (ko) * | 2000-06-05 | 2006-07-26 | 삼성전자주식회사 | 반도체 소자의 금속배선 형성방법 |
US7192827B2 (en) * | 2001-01-05 | 2007-03-20 | Micron Technology, Inc. | Methods of forming capacitor structures |
KR100399417B1 (ko) * | 2001-01-08 | 2003-09-26 | 삼성전자주식회사 | 반도체 집적 회로의 제조 방법 |
KR100396891B1 (ko) * | 2001-03-21 | 2003-09-03 | 삼성전자주식회사 | 반도체 소자의 금속 배선 형성 방법 |
KR100400248B1 (ko) * | 2001-04-06 | 2003-10-01 | 주식회사 하이닉스반도체 | 반도체소자의 배선 형성방법 |
US20030104680A1 (en) * | 2001-11-13 | 2003-06-05 | Memc Electronic Materials, Inc. | Process for the removal of copper from polished boron-doped silicon wafers |
KR100420598B1 (ko) * | 2001-11-28 | 2004-03-02 | 동부전자 주식회사 | 알루미늄을 이용한 구리 확산 방지 막 형성방법 |
KR100455382B1 (ko) * | 2002-03-12 | 2004-11-06 | 삼성전자주식회사 | 듀얼 다마신 구조를 가지는 반도체 소자의 금속 배선 형성방법 |
US20080070405A1 (en) * | 2002-05-30 | 2008-03-20 | Park Jae-Hwa | Methods of forming metal wiring layers for semiconductor devices |
KR100564605B1 (ko) * | 2004-01-14 | 2006-03-28 | 삼성전자주식회사 | 반도체 소자의 금속 배선 형성 방법 |
KR100457057B1 (ko) * | 2002-09-14 | 2004-11-10 | 삼성전자주식회사 | 금속막 형성 방법 |
US6673718B1 (en) * | 2002-11-27 | 2004-01-06 | Samsung Electronics Co., Ltd. | Methods for forming aluminum metal wirings |
KR100599434B1 (ko) | 2003-10-20 | 2006-07-14 | 주식회사 하이닉스반도체 | 반도체 소자의 금속배선 형성방법 |
KR100688055B1 (ko) | 2004-05-10 | 2007-02-28 | 주식회사 하이닉스반도체 | 저온 장벽금속층을 이용한 금속배선 제조 방법 |
US7205176B2 (en) * | 2004-05-24 | 2007-04-17 | Taiwan Semiconductor Manufacturing Company | Surface MEMS mirrors with oxide spacers |
US20060110842A1 (en) * | 2004-11-23 | 2006-05-25 | Yuh-Hwa Chang | Method and apparatus for preventing metal/silicon spiking in MEMS devices |
US20080265377A1 (en) * | 2007-04-30 | 2008-10-30 | International Business Machines Corporation | Air gap with selective pinchoff using an anti-nucleation layer |
KR100870271B1 (ko) * | 2007-06-28 | 2008-11-25 | 주식회사 하이닉스반도체 | 반도체 소자의 금속배선 및 그의 형성 방법 |
US8183145B2 (en) * | 2007-10-11 | 2012-05-22 | International Business Machines Corporation | Structure and methods of forming contact structures |
KR101433899B1 (ko) * | 2008-04-03 | 2014-08-29 | 삼성전자주식회사 | 기판 식각부의 금속층 형성방법 및 이를 이용하여 형성된금속층을 갖는 기판 및 구조물 |
CN104347476B (zh) * | 2013-07-23 | 2018-06-08 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制造方法 |
JP7016535B2 (ja) * | 2015-10-26 | 2022-02-07 | オーティーアイ ルミオニクス インコーポレーテッド | パターン化されたコーティングを含む表面およびデバイス上のコーティングをパターン化する方法 |
US10049980B1 (en) | 2017-02-10 | 2018-08-14 | International Business Machines Corporation | Low resistance seed enhancement spacers for voidless interconnect structures |
US10964590B2 (en) * | 2017-11-15 | 2021-03-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Contact metallization process |
KR20220034337A (ko) | 2020-09-11 | 2022-03-18 | 삼성전자주식회사 | 반도체 장치 |
US11424215B2 (en) | 2020-11-10 | 2022-08-23 | Sandisk Technologies Llc | Bonded assembly formed by hybrid wafer bonding using selectively deposited metal liners |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4687552A (en) * | 1985-12-02 | 1987-08-18 | Tektronix, Inc. | Rhodium capped gold IC metallization |
US5055423A (en) * | 1987-12-28 | 1991-10-08 | Texas Instruments Incorporated | Planarized selective tungsten metallization system |
US5151168A (en) * | 1990-09-24 | 1992-09-29 | Micron Technology, Inc. | Process for metallizing integrated circuits with electrolytically-deposited copper |
US5572072A (en) * | 1992-12-30 | 1996-11-05 | Samsung Electronics Co., Ltd. | Semiconductor device having a multi-layer metallization structure |
US5633199A (en) * | 1995-11-02 | 1997-05-27 | Motorola Inc. | Process for fabricating a metallized interconnect structure in a semiconductor device |
DE19713501A1 (de) * | 1996-05-16 | 1997-11-20 | Lg Semicon Co Ltd | Verfahren zum Verbinden leitender Schichten in einem Halbleiterbauteil |
EP0831523A2 (fr) * | 1996-09-23 | 1998-03-25 | Applied Materials, Inc. | DépÔt chimique en phase vapeur, semi-sélectif, d'un matériau conducteur |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US568177A (en) * | 1896-09-22 | Tesla Nikola | Apparatus For Producing Ozone | |
JPH07107565A (ja) * | 1993-10-08 | 1995-04-21 | Sony Corp | Avシステム |
KR970007837B1 (en) * | 1993-12-29 | 1997-05-17 | Hyundai Electronics Ind | Metalizing method of semiconductor device |
KR0179827B1 (ko) * | 1995-05-27 | 1999-04-15 | 문정환 | 반도체 소자의 배선 형성방법 |
US6080665A (en) * | 1997-04-11 | 2000-06-27 | Applied Materials, Inc. | Integrated nitrogen-treated titanium layer to prevent interaction of titanium and aluminum |
-
1997
- 1997-08-22 KR KR1019970040236A patent/KR100269878B1/ko not_active IP Right Cessation
-
1998
- 1998-03-20 TW TW087104169A patent/TW415058B/zh not_active IP Right Cessation
- 1998-04-02 EP EP98302581A patent/EP0898308A3/fr not_active Ceased
- 1998-05-14 JP JP10132253A patent/JPH1174272A/ja active Pending
- 1998-08-19 US US09/136,798 patent/US6376355B1/en not_active Expired - Lifetime
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4687552A (en) * | 1985-12-02 | 1987-08-18 | Tektronix, Inc. | Rhodium capped gold IC metallization |
US5055423A (en) * | 1987-12-28 | 1991-10-08 | Texas Instruments Incorporated | Planarized selective tungsten metallization system |
US5151168A (en) * | 1990-09-24 | 1992-09-29 | Micron Technology, Inc. | Process for metallizing integrated circuits with electrolytically-deposited copper |
US5572072A (en) * | 1992-12-30 | 1996-11-05 | Samsung Electronics Co., Ltd. | Semiconductor device having a multi-layer metallization structure |
US5633199A (en) * | 1995-11-02 | 1997-05-27 | Motorola Inc. | Process for fabricating a metallized interconnect structure in a semiconductor device |
DE19713501A1 (de) * | 1996-05-16 | 1997-11-20 | Lg Semicon Co Ltd | Verfahren zum Verbinden leitender Schichten in einem Halbleiterbauteil |
EP0831523A2 (fr) * | 1996-09-23 | 1998-03-25 | Applied Materials, Inc. | DépÔt chimique en phase vapeur, semi-sélectif, d'un matériau conducteur |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2363678A (en) * | 1999-12-22 | 2002-01-02 | Hyundai Electronics Ind | A Method of using a (hfac)Cu(I)(DMB) precursor to form copper wiring |
GB2363678B (en) * | 1999-12-22 | 2004-07-07 | Hyundai Electronics Ind | Method of forming a copper wiring in a semiconductor device |
GB2397947A (en) * | 1999-12-22 | 2004-08-04 | Hyundai Electronics Ind | Method of using a (hfac)Cu(I)(DMB) precursor to form copper wiring |
GB2397947B (en) * | 1999-12-22 | 2004-10-06 | Hyundai Electronics Ind | Method of forming a copper wiring in a semiconductor device |
US6955983B2 (en) * | 2002-05-30 | 2005-10-18 | Samsung Electronics Co., Ltd. | Methods of forming metal interconnections of semiconductor devices by treating a barrier metal layer |
US7384866B2 (en) | 2002-05-30 | 2008-06-10 | Samsung Electronics Co., Ltd. | Methods of forming metal interconnections of semiconductor devices by treating a barrier metal layer |
US7193369B2 (en) | 2002-11-11 | 2007-03-20 | Samsung Electronics Co., Ltd. | Method for generating gas plasma |
US7578944B2 (en) | 2002-11-11 | 2009-08-25 | Samsung Electronics Co., Ltd. | Apparatus for generating gas plasma, gas composition for generating plasma and method for manufacturing semiconductor device using the same |
US8083892B2 (en) | 2002-11-11 | 2011-12-27 | Samsung Electronics Co., Ltd. | Apparatus for generating gas plasma, gas composition for generating plasma and method for manufacturing semiconductor device using the same |
Also Published As
Publication number | Publication date |
---|---|
TW415058B (en) | 2000-12-11 |
KR19990017335A (ko) | 1999-03-15 |
KR100269878B1 (ko) | 2000-12-01 |
EP0898308A3 (fr) | 2000-06-21 |
US6376355B1 (en) | 2002-04-23 |
JPH1174272A (ja) | 1999-03-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6376355B1 (en) | Method for forming metal interconnection in semiconductor device | |
US6391769B1 (en) | Method for forming metal interconnection in semiconductor device and interconnection structure fabricated thereby | |
US7384866B2 (en) | Methods of forming metal interconnections of semiconductor devices by treating a barrier metal layer | |
US7470612B2 (en) | Method of forming metal wiring layer of semiconductor device | |
US7732331B2 (en) | Copper interconnect structure having stuffed diffusion barrier | |
US7560816B2 (en) | Small grain size, conformal aluminum interconnects and method for their formation | |
US10784157B2 (en) | Doped tantalum nitride for copper barrier applications | |
KR100396891B1 (ko) | 반도체 소자의 금속 배선 형성 방법 | |
JPH11204523A (ja) | 半導体装置の製造方法 | |
KR100455382B1 (ko) | 듀얼 다마신 구조를 가지는 반도체 소자의 금속 배선 형성방법 | |
JPH11217672A (ja) | 金属窒化物膜の化学的気相成長方法およびこれを用いた電子装置の製造方法 | |
US20020132469A1 (en) | Method for forming metal wiring layer | |
KR100363086B1 (ko) | 반도체소자의 금속배선 형성방법 및 그에 의해 제조된콘택 구조체 | |
US6048794A (en) | Selective W CVD plug process with a RTA self-aligned W-silicide barrier layer | |
JPH04290425A (ja) | 耐熱性配線の形成方法 | |
JPH053171A (ja) | タングステンプラグの形成方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): DE FR GB NL |
|
AX | Request for extension of the european patent |
Free format text: AL;LT;LV;MK;RO;SI |
|
PUAL | Search report despatched |
Free format text: ORIGINAL CODE: 0009013 |
|
AK | Designated contracting states |
Kind code of ref document: A3 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE |
|
AX | Request for extension of the european patent |
Free format text: AL;LT;LV;MK;RO;SI |
|
17P | Request for examination filed |
Effective date: 20001219 |
|
AKX | Designation fees paid |
Free format text: DE FR GB NL |
|
17Q | First examination report despatched |
Effective date: 20061215 |
|
APBK | Appeal reference recorded |
Free format text: ORIGINAL CODE: EPIDOSNREFNE |
|
APBN | Date of receipt of notice of appeal recorded |
Free format text: ORIGINAL CODE: EPIDOSNNOA2E |
|
APBR | Date of receipt of statement of grounds of appeal recorded |
Free format text: ORIGINAL CODE: EPIDOSNNOA3E |
|
APAF | Appeal reference modified |
Free format text: ORIGINAL CODE: EPIDOSCREFNE |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: SAMSUNG ELECTRONICS CO., LTD. |
|
APBT | Appeal procedure closed |
Free format text: ORIGINAL CODE: EPIDOSNNOA9E |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION HAS BEEN REFUSED |
|
18R | Application refused |
Effective date: 20150115 |