EP0548652A1 - Verfahren zur Herstellung einer Widerstands-Leitungsstruktur auf einem Substrat aus Aluminiumnitrid - Google Patents

Verfahren zur Herstellung einer Widerstands-Leitungsstruktur auf einem Substrat aus Aluminiumnitrid Download PDF

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Publication number
EP0548652A1
EP0548652A1 EP92120828A EP92120828A EP0548652A1 EP 0548652 A1 EP0548652 A1 EP 0548652A1 EP 92120828 A EP92120828 A EP 92120828A EP 92120828 A EP92120828 A EP 92120828A EP 0548652 A1 EP0548652 A1 EP 0548652A1
Authority
EP
European Patent Office
Prior art keywords
film
forming
resistive
aluminum nitride
metal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP92120828A
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English (en)
French (fr)
Inventor
Jerry L. White
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of EP0548652A1 publication Critical patent/EP0548652A1/de
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/702—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof
    • H01L21/707—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof of thin-film circuits or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/167—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed resistors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.

Definitions

  • This invention relates, in general, to semiconductor devices and more particularly to a method fabricating conductive patterns on aluminum nitride substrates.
  • High frequency semiconductor devices such as RF devices are well known in the art. Many high frequency packages employing such devices commonly include an insulating substrate on which the semiconductor is actually mounted.
  • the insulating substrate often includes a conductive pattern therein to which the semiconductor die is electrically coupled, commonly by wire bonds.
  • Berylium oxide (BeO) is a well known ceramic material often employed as an insulating substrate in RF devices. Berylium oxide is desirable due to its great thermal conductivity properties. However, berylium oxide is very expensive and difficult to use. Further, berylium oxide is toxic in its powdered form and this toxicity has resulted in increased government regulation dealing with its use. RF packages employing ceramics such as berylium oxide are also relatively difficult to frequency match. The problems associated with berylium oxide have led those of skill in the art to look to other insulating materials to employ as substrates in high frequency devices.
  • Aluminum oxide (Al2O3) has been investigated as a substrate material for RF packages. Although aluminum oxide has many good properties, its thermal conductivity properties are poor and therefore it undesirable for various high frequency applications.
  • Aluminum nitride substrates have been used in the past. Historically, aluminum nitride substrates are employed with thick film processes. One such thick film process employs screening on a molybdenum/manganese film and then firing it for adhesion. This film typically has a thickness of greater than one mil. Once the molybdenum/manganese screen has been applied, a metallization scheme such as nickel/gold is formed on the molybdenum/manganese screen. The screen layer is necessary in the thick film process because aluminum nitride typically has very poor adhesion properties to metals. The necessity of this thick screen film is undesirable because it increases the size of the semiconductor package and leads to severe problems in electrical performance. Further, the molybdenum/manganese screen is not resistive and accordingly, no resistive properties can be derived therefrom.
  • Various thin film processes using aluminum nitride substrates have also been investigated.
  • Once such thin film process includes sputtering a titanium or tungsten layer on an aluminum nitride substrate and then firing the film.
  • Reactive sputtering of titanium or tungsten may also be employed.
  • the reactive sputtering is typically performed in a controlled chamber so that the temperature and gases are such that a nitride is formed between the aluminum nitride substrate and the metal film. This nitride allows adhesion between the substrate and the film.
  • a disadvantage with this method is that neither titanium or tungsten are resistive materials and therefore, many desired resistive properties are absent.
  • a method of fabricating a resistive adhesion promoting film on an aluminum nitride substrate includes providing an aluminum nitride substrate and then forming a resistive chromium containing film thereon.
  • a refractory metal layer is then formed on the resistive film. Once the refractory metal layer has been formed, both the refractory metal layer and the resistive film are patterned as desired.
  • One or more conductive layers may then be formed on the patterned refractory metal layer to serve as a conductive pattern to which a semiconductor die may be electrically coupled. Resistors may be formed between the lines of the conductive pattern. The resistors are formed from the resistive film.
  • the single figure is a highly enlarged plan view of a semiconductor die disposed on an aluminum nitride substrate having a conductive pattern thereon.
  • Semiconductor package 10 comprises an aluminum nitride substrate 12 having a semiconductor die 14 disposed thereon. Also depicted are conductive lines 16 patterned on substrate 12 and thin film resistors 18 disposed between various conductive lines 16.
  • the portion of semiconductor package 10 depicted is typically a portion of a high frequency package such as an RF package.
  • Substrate 12 would typically be mounted on a metal header or heat sink having leads extending therefrom.
  • Conductive lines 16 would be electrically coupled to the leads, typically by wire bonds.
  • Conductive lines 16, in turn, would be electrically coupled to semiconductor die 14.
  • a cap would be placed over substrate 12 including semiconductor die 14, conductive lines 16 and resistors 18.
  • Aluminum nitride is a very desirable material to use for substrate 12 in high frequency packages.
  • Aluminum nitride has desireable thermal conductivity properties that are necessary for this type of package.
  • aluminum nitride is relatively inexpensive, easy to work with and is not toxic or hazardous.
  • aluminum nitride generally adheres poorly to metals unless various thick film or reactive sputtering processes were utilized.
  • the fabrication of the portion of semiconductor package 10 depicted by the figure is as follows. Initially, aluminum, nitride substrate 12 is provided. Aluminum nitride substrate 12 is cleaned so that no impurities remain on its surface. A typical cleaning process will include washing substrate 12 in acetone and then performing a spin-rinse dry in DI water. Following the spin-rinse dry, substrate 12 is baked at 300 degrees centigrade for 30 minutes. This bake allows substrate 12 to dry completely.
  • a resistive chromium containing film is formed on aluminum nitride substrate 12 following cleaning.
  • a preferred film is chromium silicon monoxide (CrSiO).
  • a chromium silicon monoxide film may be RF sputtered onto substrate 12 in an argon atmosphere. This is well known in the art
  • the target employed to deposit the chromium silicon monoxide is 90% chromium and 10% silicon monoxide.
  • the chromium silicon monoxide film should have a thickness of less than 1500 angstroms and preferably, a thickness on the order of 300 to 600 angstroms. Even more preferably, a thickness of 400 to 500 angstroms should be obtained.
  • the chromium silicon monoxide film have a sheet resistivity on the order of 100 to 150 ohms/square and optimally, a sheet resistivity of 127 ohms/square. It should be understood that the sheet resistivity of the chromium silicon monoxide film may vary depending upon specific applications.
  • Chromium silicon monoxide has excellent adhesion to aluminum nitride substrate 12.
  • chromium silicon monoxide When chromium silicon monoxide is deposited on aluminum nitride, it deposits as Cr2O3-Si. In other words, the adhesion to the aluminum nitride surface is excellent because an alumina oxy-nitride is formed.
  • the resistive chromium containing film allows the formation of thin film resistors 18 directly on substrate 12. Resistors 18 are highly desirable in high frequency semiconductor packages such as package 10in order to achieve desired electrical performance.
  • a refractory metal layer is formed on the resistive film.
  • the refractory metal layer preferably comprises gold although other refractory metals may be employed.
  • the refractory metal layer preferably has a thickness on the order of 200 to 2000 angstroms and most preferably on the order of 1000 angstroms. It is desireable that the refractory metal layer is deposited on the resistive film without breaking the vacuum under which the resistive film was deposited. This avoids contamination problems which might otherwise be encountered.
  • the refractory metal layer serves as an adhesion promoting layer for conductive layers which will be explained presently. It should, however, be understood that the refractory metal layer disposed on the resistive film may be employed as alone as conductive lines 16.
  • the refractory metal layer and the resistive film are both patterned with photoresist to define the pattern of conductive lines 16.
  • one or more conductive layers are formed on the patterned refractory metal layer.
  • the one or more conductive layers comprise a metal or metal scheme.
  • a copper layer is formed on the refractory metal layer
  • a nickle layer is formed on the copper layer
  • a gold layer is formed on the nickel layer.
  • conductive lines 16 comprise the resistive film, refractory metal layer, and conductive layers as patterned.
  • resistors 18 are defined. After removing the photoresist layer used to pattern conductive lines 16, a second photoresist pattern is utilized to define resistors 18. The portions of the refractory metal and resistive layers not patterned or plated are completely removed so that substrate 12 is exposed where no conductive lines 16 or resistors 18 are to be formed. The second photoresist layer is now removed and the portions of the refractory metal layer disposed on resistor patterns 18 are removed to leave resistors 18 comprising the chromium containing film. Resistors 18 may be fabricated to have desired values depending upon their size and the sheet resistance of the resistive film. Further, resistors 18 may be laser trimmed to specific values.
  • semiconductor die 14 is attached to aluminum nitride substrate 12 and electrically coupled to conductive lines 16.
  • Semiconductor die 14 may be attached by a non-conductive die attach material and then wire bonded to conductive lines 16. Conversely, bond pads or the like disposed on the backside of semiconductor die 14 may be directly coupled to conductive lines 16. Ball bond technology and the like enabling this kind of electrical coupling is well known in the art.
  • the invention described herein allows for conductive lines 16 and resistors 18 to be fabricated on an aluminum nitride substrate 12.
  • the chromium containing resistive film further adheres extremely well to aluminum nitride substrate 12.
  • the refractory metal layer adheres very well to the resistive film and allows additional conductive layers to be formed thereon which will adhere to the refractory metal layer. Further the formation of the refractory metal layer allows plating of additional metal conductive layers thereon.
  • the kind of package disclosed herein is extremely useful for high frequency applications such as RF device packages.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Non-Adjustable Resistors (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Semiconductor Integrated Circuits (AREA)
EP92120828A 1991-10-20 1992-12-07 Verfahren zur Herstellung einer Widerstands-Leitungsstruktur auf einem Substrat aus Aluminiumnitrid Withdrawn EP0548652A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/811,272 US5221639A (en) 1991-10-20 1991-10-20 Method of fabricating resistive conductive patterns on aluminum nitride substrates
US811272 1991-12-20

Publications (1)

Publication Number Publication Date
EP0548652A1 true EP0548652A1 (de) 1993-06-30

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EP92120828A Withdrawn EP0548652A1 (de) 1991-10-20 1992-12-07 Verfahren zur Herstellung einer Widerstands-Leitungsstruktur auf einem Substrat aus Aluminiumnitrid

Country Status (3)

Country Link
US (1) US5221639A (de)
EP (1) EP0548652A1 (de)
JP (1) JPH07249712A (de)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1274125A2 (de) * 2001-07-05 2003-01-08 Sumitomo Electric Industries, Ltd. Leiterplatte, ihre Herstellungsmethode und Modul hoher Ausgangsleistung
EP1274126A2 (de) * 2001-07-05 2003-01-08 Sumitomo Electric Industries, Ltd. Leiterplatte, ihre Herstellungsmethode und Modul hoher Ausgangsleistung
EP1304740A2 (de) * 2001-10-17 2003-04-23 Sumitomo Electric Industries, Ltd. Leiterplatte, ihre Herstellungsmethode und Modul hoher Ausgangsleistung

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5254869A (en) * 1991-06-28 1993-10-19 Linear Technology Corporation Aluminum alloy/silicon chromium sandwich schottky diode
US5494845A (en) * 1993-08-17 1996-02-27 Raytheon Company Method of fabrication of bilayer thin film resistor
JP3845925B2 (ja) * 1996-02-05 2006-11-15 住友電気工業株式会社 窒化アルミニウム基材を用いた半導体装置用部材及びその製造方法
US5976392A (en) * 1997-03-07 1999-11-02 Yageo Corporation Method for fabrication of thin film resistor
US6023086A (en) * 1997-09-02 2000-02-08 Motorola, Inc. Semiconductor transistor with stabilizing gate electrode
US7106167B2 (en) * 2002-06-28 2006-09-12 Heetronix Stable high temperature sensor system with tungsten on AlN

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2532472A1 (fr) * 1982-08-31 1984-03-02 Lignes Telegraph Telephon Procede de fabrication de connexions electriques pour circuit hybride et circuit hybride comportant de telles connexions
EP0326077A2 (de) * 1988-01-25 1989-08-02 Kabushiki Kaisha Toshiba Schaltungsplatte
EP0370478A2 (de) * 1988-11-22 1990-05-30 microtech GmbH electronic Präzisions-Widerstands-Dünnschicht

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61107542U (de) * 1984-12-19 1986-07-08
JPS63317357A (ja) * 1987-06-22 1988-12-26 Hitachi Ltd サ−マルヘツド
JP2772001B2 (ja) * 1988-11-28 1998-07-02 株式会社日立製作所 半導体装置
US4951014A (en) * 1989-05-26 1990-08-21 Raytheon Company High power microwave circuit packages
EP0421680B1 (de) * 1989-09-27 1994-03-16 Kabushiki Kaisha Toshiba Leiterplatte aus Aluminiumnitrid
US5028306A (en) * 1990-09-04 1991-07-02 Motorola, Inc. Process for forming a ceramic-metal adduct

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2532472A1 (fr) * 1982-08-31 1984-03-02 Lignes Telegraph Telephon Procede de fabrication de connexions electriques pour circuit hybride et circuit hybride comportant de telles connexions
EP0326077A2 (de) * 1988-01-25 1989-08-02 Kabushiki Kaisha Toshiba Schaltungsplatte
EP0370478A2 (de) * 1988-11-22 1990-05-30 microtech GmbH electronic Präzisions-Widerstands-Dünnschicht

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ELECTRONIC PACKAGING AND PRODUCTION vol. 29, no. 9, September 1989, MASSACHUSETTS US pages 58 - 63 J. J. LICARI *
PATENT ABSTRACTS OF JAPAN vol. 015, no. 408 (E-1123)17 October 1991 & JP-A-31 67 801 ( TOSHIBA ) 19 July 1991 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1274125A2 (de) * 2001-07-05 2003-01-08 Sumitomo Electric Industries, Ltd. Leiterplatte, ihre Herstellungsmethode und Modul hoher Ausgangsleistung
EP1274126A2 (de) * 2001-07-05 2003-01-08 Sumitomo Electric Industries, Ltd. Leiterplatte, ihre Herstellungsmethode und Modul hoher Ausgangsleistung
EP1274125A3 (de) * 2001-07-05 2004-12-15 Sumitomo Electric Industries, Ltd. Leiterplatte, ihre Herstellungsmethode und Modul hoher Ausgangsleistung
EP1274126A3 (de) * 2001-07-05 2004-12-15 Sumitomo Electric Industries, Ltd. Leiterplatte, ihre Herstellungsmethode und Modul hoher Ausgangsleistung
EP1304740A2 (de) * 2001-10-17 2003-04-23 Sumitomo Electric Industries, Ltd. Leiterplatte, ihre Herstellungsmethode und Modul hoher Ausgangsleistung
EP1304740A3 (de) * 2001-10-17 2005-02-02 Sumitomo Electric Industries, Ltd. Leiterplatte, ihre Herstellungsmethode und Modul hoher Ausgangsleistung

Also Published As

Publication number Publication date
US5221639A (en) 1993-06-22
JPH07249712A (ja) 1995-09-26

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