EP0356465A1 - Verkapselungsbarriere für dickschicht-hybridschaltungen - Google Patents

Verkapselungsbarriere für dickschicht-hybridschaltungen

Info

Publication number
EP0356465A1
EP0356465A1 EP88906412A EP88906412A EP0356465A1 EP 0356465 A1 EP0356465 A1 EP 0356465A1 EP 88906412 A EP88906412 A EP 88906412A EP 88906412 A EP88906412 A EP 88906412A EP 0356465 A1 EP0356465 A1 EP 0356465A1
Authority
EP
European Patent Office
Prior art keywords
encapsulant
barrier
electronic device
substrate
curable material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP88906412A
Other languages
English (en)
French (fr)
Inventor
John David Schmidt
Martin Arthur Maurinus
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Eastman Kodak Co
Original Assignee
Eastman Kodak Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Eastman Kodak Co filed Critical Eastman Kodak Co
Publication of EP0356465A1 publication Critical patent/EP0356465A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.

Definitions

  • the present invention relates generally to encapsulating electronic devices, and more particularly to encapsulating electronic devices with radiatively curable materials BACKGROUND ART
  • U.S. Patent No. 3,381,071 to C. W. Logan et al shows an electronic circuit encapsulated in a thermally cured encapsulant such as an epoxy resin.
  • the encapsulant is formed by first screen-printing a barrier wall comprising a thermally curable material such as glass onto a ceramic substrate.
  • the barrier wall is thermally cured, and the electronic device is mounted on the substrate within the barrier.
  • the epoxy resin is deposited, in liquid form, over the electronic device and is contained within the barrier wall.
  • the encapsulant is then cured through a second application of heat.
  • U.S. Patent No. 4,203,792 to Thompson shows a method for encapsulating electronic devices using a multicomponent polymer material comprising a mixture of a minor amount of a radiation curable material with a major amount of a thermally curable material. After depositing the encapsulant over the electronic device, the encapsulant is radiatively cured for a short period of time to establish its shape. The encapsulant is subsequently heat cured to form the finished device.
  • the process shown in Thompson suffers from the disadvantage of requiring a complex curing process including both a radiation curing stage and a heat curing stage.
  • U.S. Patent No. 4,635,356 to Ohuchi et al shows a method of encapsulating an electronic device wherein a large, preformed spacer is used as a barrier wall to surround electronic components mounted on a radiation-transparent support board.
  • the area within the barrier wall is filled with an encapsulant comprising a radiatively curable material.
  • the encapsulant is cured by exposure to radiation through the support board, and the barrier is removed to form the finished device.
  • Ohuchi et al suffers from the disadvantage that the preformed barrier wall is time consuming to place and remove, and requires a substantial amount of space.
  • a new and improved method of encapsulating an electronic device on a substrate wherein a barrier comprising a radiatively curable material is deposited about a predetermined location on the substrate. Suitable radiation is used to. cure the barrier, and the electronic device is placed within the barrier. An encapsulant is then deposited over the electronic device within the barrier.
  • the barrier is deposited using a thick-film deposition technique.
  • the barrier and encapsulant preferably comprise ultraviolet (UV) curable materials.
  • the encapsulant can comprise an optically clear material when the electronic device comprises a photoelectric device.
  • a method of encapsulating an electronic device on a substrate comprises depositing an encapsulant comprising a majority of radiatively curable material over the electronic device in the absence of a barrier.
  • the encapsulant is then cured using suitable radiation.
  • the encapsulant preferably comprises a UV curable material.
  • FIGS. 1-5 illustrate consecutive steps in manufacturing an encapsulated electronic device in accordance with a first embodiment of the present invention.
  • FIG. 6 illustrates an encapsulated electronic device constructed in accordance with a second embodiment of the invention.
  • FIG. 1 shows a substrate 10 supporting a pattern of two electrical conductors indicated at 12, 13, respectively.
  • Substrate 10 comprises a suitable electrically insulating material such as a glass-epoxy resin, typically used to construct printed-circuit boards, or a ceramic such as alumina, typically used to construct hybrid circuits.
  • Electrical conductors 12, 13 each comprise an electrically conductive metal such as copper or palladium silver.
  • Electrical conductors 12, 13 are formed on substrate 10 using any suitable process, for example by thick-film deposition when substrate 10 comprises a ceramic, or by etching when the substrate comprises a printed circuit board.
  • a circular barrier 14 of radiatively curable material is disposed about a predetermined region 16 of substrate 10.
  • electrical conductors 12 and 13 each include portions, indicated at 12A and 13A, which extend inside of barrier 14 within region 16.
  • Barrier 14 preferably comprises an ultraviolet (UV) curable material such as the dielectric polymer CERMALLOY UV 5270T available from the Hercules Corp., and is preferably deposited on substrate 10 (and over conductor portions 12A, 13A) using a thick- film deposition process such as screen-printing.
  • a thick-film deposition process provides barrier 14 with a height A of approximately 4-5 mils. The exact height of barrier 14 is not, however, critical.
  • the barrier may be formed using any suitable method for depositing a radiatively curable material on a substrate. After barrier 14 is deposited on substrate 10, the barrier is exposed to a source 18 of suitable curing radiation 19. When barrier 14 comprises a UV curable material, source 18 is selected to be a source of UV radiation 19.
  • an electronic device 20 is placed on region 16 of substrate 10 using, for example, a suitable adhesive 22.
  • Electronic device 20 includes a pair of electrical terminals 24, 26, connected to electrical conductor portions 12A, 13A by electrically conductive wires 28, 30, respectively.
  • wires 28, 30 comprise any suitable electrical conductors connected with any suitable bond.
  • conductors 28, 30 can comprise ultrasonically bonded wires, or soldered Tape Automated Bonding (TAB) leads.
  • TAB Tape Automated Bonding
  • Encapsulant 32 being deposited on substrate 10 while in a viscous state, in this embodiment of the invention the flow of the encapsulant is naturally contained within barrier 14.
  • Encapsulant 32 can comprise any curable material which exhibits qualities suitable for encapsulating electronic components, such as: being electrically insulating; moisture resistant; adhesive to substrate 10; and exhibiting a coefficient of thermal expansion substantially matching that of substrate 10.
  • encapsulant 32 comprises a UV curable material. After deposition of encapsulant 32 on substrate 10, the encapsulant is exposed to curing radiation 19 for a time sufficient to cause adequate cross-linking and hence hardening. A top view of the finished hybrid circuit 40 is shown in FIG. 5.
  • barrier 14 can be quickly and economically cured using radiation. This speed of curing permits the shape and extent of the periphery of encapsulant 32, which is essentially the same as the periphery of barrier 14, to be closely controlled. The method can thus be applied to densely packed electronic components such as are found in modern hybrid circuits.
  • encapsulant 32 comprises an optically clear, UV curable material such as the optical polymer NORLAND 63 available from NORLAND Products, Inc.
  • Electronic device 20 comprises a photoelectric device, such as a photodiode, including a light-sensing surface 20A (shown in FIG. 3) facing away from substrate 10 and into the encapsulant.
  • This preferred embodiment of the invention provides encapsulant 32 with a functional, concave lens-like cross-sectional shape. This lens ⁇ like shape, visible in FIG. 4, is believed to provide focusing of light onto surface 20A of photodiode 20 and enhance the operation of the photodiode.
  • the lens-like shape of encapsulant 32 is markedly and unexpectedly uniform amongst the completed devices.
  • the screen-printing process provides the ability to form many such encapsulated devices of uniform characteristics in relatively few and economical steps.
  • Hybrid circuit 40' is identical to hybrid circuit 40 (FIGS. 1-5) with the exception that it does not include a barrier 14, and that encapsulant 32* must comprise a majority of radiately curable material.
  • Hybrid circuit 40' is fabricated identically to hybrid circuit 40, with the exception that the steps of depositing and curing barrier 14 are not performed.
  • encapsulant 32' comprises a material which is substantially entirely radiatively curable such as the optical polymer Norland 63.
  • encapsulant 32* comprises an optically clear, UV curable material.
  • an encapsulant provides excellent operational characteristics, including durability and flexibility.
  • the encapsulant is relatively straightforward and economical to apply and cure. Further, because the encapsulant is optically clear, it is excellent for applications where it is desirable to view or inspect the encapsulated device during or after operation.
EP88906412A 1987-06-29 1988-06-20 Verkapselungsbarriere für dickschicht-hybridschaltungen Withdrawn EP0356465A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/067,743 US4843036A (en) 1987-06-29 1987-06-29 Method for encapsulating electronic devices
US67743 1987-06-29

Publications (1)

Publication Number Publication Date
EP0356465A1 true EP0356465A1 (de) 1990-03-07

Family

ID=22078098

Family Applications (1)

Application Number Title Priority Date Filing Date
EP88906412A Withdrawn EP0356465A1 (de) 1987-06-29 1988-06-20 Verkapselungsbarriere für dickschicht-hybridschaltungen

Country Status (4)

Country Link
US (1) US4843036A (de)
EP (1) EP0356465A1 (de)
JP (1) JPH02501692A (de)
WO (1) WO1989000337A1 (de)

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Also Published As

Publication number Publication date
WO1989000337A1 (en) 1989-01-12
JPH02501692A (ja) 1990-06-07
US4843036A (en) 1989-06-27

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