EP0844665A2 - Halbleiterscheibengrosse Verpackung - Google Patents
Halbleiterscheibengrosse Verpackung Download PDFInfo
- Publication number
- EP0844665A2 EP0844665A2 EP97120173A EP97120173A EP0844665A2 EP 0844665 A2 EP0844665 A2 EP 0844665A2 EP 97120173 A EP97120173 A EP 97120173A EP 97120173 A EP97120173 A EP 97120173A EP 0844665 A2 EP0844665 A2 EP 0844665A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- integrated circuit
- lead
- lead frame
- opposing
- connector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/207—Diameter ranges
- H01L2924/20752—Diameter ranges larger or equal to 20 microns less than 30 microns
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/207—Diameter ranges
- H01L2924/20753—Diameter ranges larger or equal to 30 microns less than 40 microns
Definitions
- This invention relates generally to the field of integrated circuit packaging, and more particularly to wafer level packaging of integrated circuits.
- circuit chips The processes involved in the fabrication and packaging of circuit chips are well known. Typically, an array of identical circuits is patterned onto a circular semiconductor wafer using well known micro-lithographic techniques. The wafer is then sawed into many rectangular pieces to separate the individual circuits from one another, so that each circuit occupies its own circuit chip.
- the chips are individually mounted onto lead frames, where they are held in place by means of an epoxy.
- a wire bonder is then used to establish electrical connections between the die pads on the chip and the respective leads of the lead frame.
- the chip and lead frame are placed into mold equipment, where plastic is transfer molded to surround the assembly.
- This plastic packaging serves to protect the chip from exposure to light, moisture and contamination, which could damage the circuit components, as well as making the entire assembly mechanically rigid and durable.
- the molded plastic is then cured by means of heating in an oven for several hours.
- the leads of the lead frame are then trimmed and formed into the desired shape.
- the leads may be formed into a "gull wing" shape for surface-mounted chips.
- various electrical and mechanical tests are performed to determine whether the chip will function for its intended purpose.
- circuit chip industry is very cost-competitive. It is therefore desirable to shorten, streamline or eliminate packaging steps to shorten production time and reduce production costs for the chips.
- the present invention provides a method of packaging integrated circuits at the wafer level. Additionally, the present invention provides a chip size package.
- an integrated circuit package may include an integrated circuit chip.
- a lead frame may be opposite the circuit side of the integrated circuit chip.
- the lead frame may include at least one lead electrically coupled to the integrated circuit by a connector.
- the lead may be within a periphery of the integrated circuit chip.
- An encapsulate may cover the integrated circuit, the connector and a portion of the lead frame. A remaining portion of the lead frame may be exposed from the encapsulant.
- an integrated circuit may be packaged at the wafer level.
- a sheet of lead frames may be opposite a plurality of integrated circuit chips.
- the encapsulate may cover the integrated circuits and a portion of each lead frame.
- Each encapsulated integrated circuit and opposing lead frame may form a discrete integrated circuit package.
- Important technical advantages of the present invention include providing chip size packages for integrated circuits.
- a lead frame, connectors and encapsulant do not extend beyond a periphery of an opposing integrated circuit chip. Accordingly, package volume is minimized and the chip may be used in devices requiring extremely small chips.
- Another technical advantage of the present invention includes providing a method of packaging integrated circuit chips at the wafer level.
- integrated circuit chips may be packaged concurrently while still part of a wafer.
- the packaging process may be carried out as a continuation of the wafer fabrication process. This serves to streamline and shorten the assembly and packaging process.
- FIGURES 1A-E illustrate a method of packaging integrated circuits at the wafer level. Wafer level packaging may be carried out as a continuation of the wafer fabrication process to streamline and shorten the packaging process.
- FIGURE 1A shows a patterned wafer 10.
- the patterned wafer 10 may comprise a substrate 12 and a plurality of integrated circuits 14 formed in a surface 16 of the substrate 12.
- the substrate 12 may include one or more layers of semiconductor material.
- the substrate 12 may include an epitaxial layer grown on a wafer.
- the integrated circuits 14 may each include a plurality of bond pads 18 electrically coupled to the integrated circuit 14. As described in more detail below, the bond pads 18 provide electrical contacts through which the integrated circuit 14 may be connected to external components. In one embodiment, the bond pads 18 may be disposed along a center line 20 of the integrated circuit 14. In this embodiment, the number and configuration of the bond pads 18 may vary depending on the application. For example, the integrated circuit 14 may include one or more staggered or parallel rows of bond pads 18. It will be understood that the bond pads 18 may be disposed elsewhere on the integrated circuit 14 within the scope of the present invention.
- Each integrated circuit 14 and surrounding section of the substrate 12 may define a discrete integrated circuit chip 22.
- the integrated circuit chips 22 may each be packaged to provide connections to external components and to provide protection from environmental factors. Typically, patterned wafers are sawed into individual integrated circuit chips for packaging. The integrated circuit chips are each separately mounted and coupled to a lead frame, and then encapsulated with that lead frame. A problem with this method is that the separate packaging of integrated circuit chips is both time consuming and costly. Additionally, it prevents packaging from being carried out as a continuation of the wafer fabrication process.
- the present invention solves this problem by providing a method of packaging integrated circuit chips at the wafer level.
- the integrated circuit chips 22 are packaged concurrently while still part of the patterned wafer 10. Accordingly, the packaging process may be carried out as a continuation of the wafer fabrication process. This serves to streamline and shorten the packaging process.
- the method of the present invention produces a chip size package. As a result, the packaged integrated circuit chips 22 may be used in applications which require miniaturized devices consuming an area not larger than individual chips.
- a polymide coating 24 may be applied to the surface 16 of the substrate 12.
- the polymide coating 24 may provide better adhesion for encapsulating material that will cover and protect the integrated circuits 14.
- Conventional pattern etching techniques may be used to prevent the polymide coating 24 from covering the bonding pads 18. It will be understood that other or no coatings may be used within the scope of the present invention.
- a sheet of lead frames 26 may be disposed opposite the surface 16 of the substrate 12.
- the sheet of lead frames 26 may include a plurality of individual lead frames 28 that each provide electrical connections for one of the integrated circuit chips 22.
- the sheet of lead frames 26 may be a unitary sheet of material.
- the material of the lead frames 28 may be Alloy 42 locally plated with silver. It will be understood that a variety of other materials may be used for the lead frames 28 within the scope of the present invention.
- the lead frames 28 may each include a plurality of leads 30 within a periphery 32 of an opposing integrated circuit chip 22. Accordingly, the leads 30 do not overlap other integrated circuit chips 22. As described in more detail below, the leads 30 may be electrically coupled to the bonding pads 18 and extend from the encapsulant for connection to external components.
- the leads 30 may be in a dual level configuration. In this configuration, as shown by FIGURE 1B, an upper set of leads 30 may be disposed on a lower set of leads 30. Accordingly, the dual level configuration provides a greater number of leads 30 for the integrated circuit chips 22.
- the lead frames 28 may also include an elongated strip (not shown) connecting one or more leads 30. The strip may be employed as a ground or supply voltage conductor. It will be understood that other lead frame 28 configurations may be used within the scope of the present invention.
- the leads 30 may each have a distal end 34 for connection to an external device.
- the distal ends 34 are in substantially one plane and may extend the periphery 32 of the integrated circuit chip 22.
- the lead frames 28 may be cut from the lead frame sheet 26 by the post packaging sawing process used to cut the patterned wafer 10 into individual integrated circuit chips 22.
- each distal end 34 may be substantially parallel to the integrated circuit chip 22.
- the distal end 34 may include palladium.
- the palladium pre-plating allows the distal end 34 to be more easily soldered to a printed circuit board and the like. It will be understood that the distal end 34 may include other or no pre-plating within the scope of the present invention.
- the distal end 34 may be solder pre-plated.
- the lead frames 28 may each be mounted to an opposing integrated circuit chip 22.
- an adhesive tape 40 may be used to mount the lead frames 28 to the opposing integrated circuit chip 22.
- the adhesive tape 40 is non-conducting to prevent electrical shorting.
- the adhesive tape 40 may be tacky on both sides to adhere to the polymide layer 24 and to the leads 30 of the lead frame 28.
- the adhesive tape 40 may be attached to the lead frame 28 in a variety of ways and a variety of thicknesses. Such methods are well known and will not be further described.
- the upper set of leads 30 may be mounted to the lower set of leads 30 by the adhesive tape 40.
- adhesive tape 40 has been discussed for mounting the leads 30, it will be understood that the lead frames 28 may be otherwise mounted to the opposing integrated circuit chip 22.
- the upper leads may be otherwise mounted to the lower leads.
- the leads 30 and/or lead frame 28 may be mechanically coupled by an epoxy or the like.
- a connector 42 may electrically couple the leads 30 to the bonding pads 18 of the opposing integrated circuit chip 22.
- the connectors 42 may each comprise a wire bonded to a lead 30 and to a bonding pad 18.
- the wire may be any thin, durable conductive metal.
- the wire may be gold wire having a diameter of about 1.0 to 1.2 mils.
- the wire may be wedge, ball or similarly bonded to the leads 30 and the bonding pads 18.
- the wire bonding process may use trapezoidal looping which results in a low looping profile.
- the connector 42 may be other than a wire within the scope of the present invention.
- the connector 42 may be a solder or a gold ball, or alternately wire and ball.
- the integrated circuit chips 22, connectors 42 and at least a portion of the lead frames 28 may be encapsulated.
- the encapsulant 44 serves to protect the integrated circuit chips 22 from exposure to environmental factors that could damage the circuit components.
- the encapsulant 44 also serves to make the entire assembly mechanically rigid and durable.
- Each encapsulated integrated circuit, connectors and opposing lead frame may form a discrete integrated circuit package 50.
- the encapsulant 44 may be applied to only the side of the wafer 10 including the integrated circuits 14, connectors 42 and lead frames 28.
- the encapsulant 44 may be applied as a liquid by a syringe. In this embodiment, the liquid may be at first low viscosity and quickly solidify. It will be understood that the encapsulant 44 may be otherwise applied within the scope of the present invention.
- the encapsulant 44 may be applied using conventional transfer molding or 3P molding technology, a mold cavity as large as the wafer 10 or the like. It will be further understood that both sides of the wafer 10 may be encapsulated within the scope of the present invention.
- each lead 30 may remain exposed after encapsulation.
- the exposed portion of the leads 30 provide connections for the integrated circuit chip 22 to external components, such as a printed circuit board and the like.
- the exposed portion of the leads 30 may be the distal ends 34.
- the distal ends 34 may be pre-plating with palladium to be more easily soldered to a printed circuit board or the like.
- the distal ends 34 may be left exposed by regulating the volume of encapsulant 44 applied to the wafer 10.
- the volume of the encapsulant 44 may be the amount necessary to fill up to an underside 46 of the distal ends 34.
- the distal ends 34 may be substantially parallel to the integrated circuit chip 22 to allow the encapsulant 44 to fill up to the underside 46 of the distal ends 34 without covering an outer side 46 of the distal ends 34.
- the substantially parallel distal ends 34 will also allow the packaged chip to sit flat against a printed circuit board or the like.
- the encapsulated wafer may be sawed to detach the individual integrated circuit packages 50 from one another.
- the integrated circuit packages 50 may be complete and ready for testing, stenciling and shipment to customers. If desired, however, ends 52 of the integrated circuit packages 50 and/or the back side 54 of the substrate 12 may be first sealed.
- the present invention provides a method of packaging integrated circuits at the wafer level.
- the wafer level packaging may be carried out as a continuation of the wafer fabrication process to streamline and shorten the packaging process.
- each integrated circuit package 50 may be a chip sized package. Accordingly, neither the lead frame 28, connectors 42 or encapsulant 44 extend beyond the periphery 32 of the integrated circuit chip 22. As a result, package volume is minimized and the chip may be used in devices requiring extremely small chips.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US3146496P | 1996-11-21 | 1996-11-21 | |
US31464P | 1996-11-21 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0844665A2 true EP0844665A2 (de) | 1998-05-27 |
EP0844665A3 EP0844665A3 (de) | 1999-10-27 |
Family
ID=21859599
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP97120173A Withdrawn EP0844665A3 (de) | 1996-11-21 | 1997-11-18 | Halbleiterscheibengrosse Verpackung |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP0844665A3 (de) |
JP (1) | JPH10163405A (de) |
KR (1) | KR19980042617A (de) |
SG (1) | SG74604A1 (de) |
TW (1) | TW386272B (de) |
Cited By (52)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19856833A1 (de) * | 1998-12-09 | 2000-06-21 | Siemens Ag | Verfahren zur Herstellung eines integrierten Schaltkreises |
EP1018762A2 (de) * | 1998-10-16 | 2000-07-12 | Shinko Electric Industries Co. Ltd. | Halbleiteranordnung und Verfahren zu ihrer Herstellung |
US6521485B2 (en) | 2001-01-17 | 2003-02-18 | Walsin Advanced Electronics Ltd | Method for manufacturing wafer level chip size package |
US6639308B1 (en) | 1999-12-16 | 2003-10-28 | Amkor Technology, Inc. | Near chip size semiconductor package |
US6833609B1 (en) | 1999-11-05 | 2004-12-21 | Amkor Technology, Inc. | Integrated circuit device packages and substrates for making the packages |
US6847099B1 (en) | 2003-02-05 | 2005-01-25 | Amkor Technology Inc. | Offset etched corner leads for semiconductor package |
US7687893B2 (en) | 2006-12-27 | 2010-03-30 | Amkor Technology, Inc. | Semiconductor package having leadframe with exposed anchor pads |
US7687899B1 (en) | 2007-08-07 | 2010-03-30 | Amkor Technology, Inc. | Dual laminate package structure with embedded elements |
US7723852B1 (en) | 2008-01-21 | 2010-05-25 | Amkor Technology, Inc. | Stacked semiconductor package and method of making same |
US7732899B1 (en) | 2005-12-02 | 2010-06-08 | Amkor Technology, Inc. | Etch singulated semiconductor package |
US7768135B1 (en) | 2008-04-17 | 2010-08-03 | Amkor Technology, Inc. | Semiconductor package with fast power-up cycle and method of making same |
US7777351B1 (en) | 2007-10-01 | 2010-08-17 | Amkor Technology, Inc. | Thin stacked interposer package |
US7808084B1 (en) | 2008-05-06 | 2010-10-05 | Amkor Technology, Inc. | Semiconductor package with half-etched locking features |
US7829990B1 (en) | 2007-01-18 | 2010-11-09 | Amkor Technology, Inc. | Stackable semiconductor package including laminate interposer |
US7847392B1 (en) | 2008-09-30 | 2010-12-07 | Amkor Technology, Inc. | Semiconductor device including leadframe with increased I/O |
US7847386B1 (en) | 2007-11-05 | 2010-12-07 | Amkor Technology, Inc. | Reduced size stacked semiconductor package and method of making the same |
US7875963B1 (en) | 2008-11-21 | 2011-01-25 | Amkor Technology, Inc. | Semiconductor device including leadframe having power bars and increased I/O |
US7928542B2 (en) | 2001-03-27 | 2011-04-19 | Amkor Technology, Inc. | Lead frame for semiconductor package |
US7956453B1 (en) | 2008-01-16 | 2011-06-07 | Amkor Technology, Inc. | Semiconductor package with patterning layer and method of making same |
US7960818B1 (en) | 2009-03-04 | 2011-06-14 | Amkor Technology, Inc. | Conformal shield on punch QFN semiconductor package |
US7968998B1 (en) | 2006-06-21 | 2011-06-28 | Amkor Technology, Inc. | Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package |
US7977774B2 (en) | 2007-07-10 | 2011-07-12 | Amkor Technology, Inc. | Fusion quad flat semiconductor package |
US7982298B1 (en) | 2008-12-03 | 2011-07-19 | Amkor Technology, Inc. | Package in package semiconductor device |
US7982297B1 (en) | 2007-03-06 | 2011-07-19 | Amkor Technology, Inc. | Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same |
US7989933B1 (en) | 2008-10-06 | 2011-08-02 | Amkor Technology, Inc. | Increased I/O leadframe and semiconductor device including same |
US8008758B1 (en) | 2008-10-27 | 2011-08-30 | Amkor Technology, Inc. | Semiconductor device with increased I/O leadframe |
US8026589B1 (en) | 2009-02-23 | 2011-09-27 | Amkor Technology, Inc. | Reduced profile stackable semiconductor package |
US8058715B1 (en) | 2009-01-09 | 2011-11-15 | Amkor Technology, Inc. | Package in package device for RF transceiver module |
US8067821B1 (en) | 2008-04-10 | 2011-11-29 | Amkor Technology, Inc. | Flat semiconductor package with half package molding |
US8072050B1 (en) | 2008-11-18 | 2011-12-06 | Amkor Technology, Inc. | Semiconductor device with increased I/O leadframe including passive device |
US8089159B1 (en) | 2007-10-03 | 2012-01-03 | Amkor Technology, Inc. | Semiconductor package with increased I/O density and method of making the same |
US8089145B1 (en) | 2008-11-17 | 2012-01-03 | Amkor Technology, Inc. | Semiconductor device including increased capacity leadframe |
US8125064B1 (en) | 2008-07-28 | 2012-02-28 | Amkor Technology, Inc. | Increased I/O semiconductor package and method of making same |
US8184453B1 (en) | 2008-07-31 | 2012-05-22 | Amkor Technology, Inc. | Increased capacity semiconductor package |
US8410585B2 (en) | 2000-04-27 | 2013-04-02 | Amkor Technology, Inc. | Leadframe and semiconductor package made using the leadframe |
US8575742B1 (en) | 2009-04-06 | 2013-11-05 | Amkor Technology, Inc. | Semiconductor device with increased I/O leadframe including power bars |
US8648450B1 (en) | 2011-01-27 | 2014-02-11 | Amkor Technology, Inc. | Semiconductor device including leadframe with a combination of leads and lands |
US8674485B1 (en) | 2010-12-08 | 2014-03-18 | Amkor Technology, Inc. | Semiconductor device including leadframe with downsets |
US8680656B1 (en) | 2009-01-05 | 2014-03-25 | Amkor Technology, Inc. | Leadframe structure for concentrated photovoltaic receiver package |
US8866278B1 (en) | 2011-10-10 | 2014-10-21 | Amkor Technology, Inc. | Semiconductor device with increased I/O configuration |
US9048298B1 (en) | 2012-03-29 | 2015-06-02 | Amkor Technology, Inc. | Backside warpage control structure and fabrication method |
US9054117B1 (en) | 2002-11-08 | 2015-06-09 | Amkor Technology, Inc. | Wafer level package and fabrication method |
US9082833B1 (en) | 2011-01-06 | 2015-07-14 | Amkor Technology, Inc. | Through via recessed reveal structure and method |
US9184148B2 (en) | 2013-10-24 | 2015-11-10 | Amkor Technology, Inc. | Semiconductor package and method therefor |
US9184118B2 (en) | 2013-05-02 | 2015-11-10 | Amkor Technology Inc. | Micro lead frame structure having reinforcing portions and method |
US9631481B1 (en) | 2011-01-27 | 2017-04-25 | Amkor Technology, Inc. | Semiconductor device including leadframe with a combination of leads and lands and method |
US9673122B2 (en) | 2014-05-02 | 2017-06-06 | Amkor Technology, Inc. | Micro lead frame structure having reinforcing portions and method |
US9691734B1 (en) | 2009-12-07 | 2017-06-27 | Amkor Technology, Inc. | Method of forming a plurality of electronic component packages |
US9704725B1 (en) | 2012-03-06 | 2017-07-11 | Amkor Technology, Inc. | Semiconductor device with leadframe configured to facilitate reduced burr formation |
US9947623B1 (en) | 2011-11-29 | 2018-04-17 | Amkor Technology, Inc. | Semiconductor device comprising a conductive pad on a protruding-through electrode |
US10014240B1 (en) | 2012-03-29 | 2018-07-03 | Amkor Technology, Inc. | Embedded component package and fabrication method |
US10811341B2 (en) | 2009-01-05 | 2020-10-20 | Amkor Technology Singapore Holding Pte Ltd. | Semiconductor device with through-mold via |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6143981A (en) | 1998-06-24 | 2000-11-07 | Amkor Technology, Inc. | Plastic integrated circuit package and method and leadframe for making the package |
KR20010004529A (ko) | 1999-06-29 | 2001-01-15 | 김영환 | 웨이퍼 레벨 패키지 및 그의 제조 방법 |
US7723210B2 (en) | 2002-11-08 | 2010-05-25 | Amkor Technology, Inc. | Direct-write wafer level chip scale package |
US6798047B1 (en) | 2002-12-26 | 2004-09-28 | Amkor Technology, Inc. | Pre-molded leadframe |
US6750545B1 (en) | 2003-02-28 | 2004-06-15 | Amkor Technology, Inc. | Semiconductor package capable of die stacking |
US6794740B1 (en) | 2003-03-13 | 2004-09-21 | Amkor Technology, Inc. | Leadframe package for semiconductor devices |
US7572681B1 (en) | 2005-12-08 | 2009-08-11 | Amkor Technology, Inc. | Embedded electronic component package |
US7902660B1 (en) | 2006-05-24 | 2011-03-08 | Amkor Technology, Inc. | Substrate for semiconductor device and manufacturing method thereof |
US8796561B1 (en) | 2009-10-05 | 2014-08-05 | Amkor Technology, Inc. | Fan out build up substrate stackable package and method |
US8937381B1 (en) | 2009-12-03 | 2015-01-20 | Amkor Technology, Inc. | Thin stackable package and method |
US8324511B1 (en) | 2010-04-06 | 2012-12-04 | Amkor Technology, Inc. | Through via nub reveal method and structure |
US8294276B1 (en) | 2010-05-27 | 2012-10-23 | Amkor Technology, Inc. | Semiconductor device and fabricating method thereof |
US8440554B1 (en) | 2010-08-02 | 2013-05-14 | Amkor Technology, Inc. | Through via connected backside embedded circuit features structure and method |
US8487445B1 (en) | 2010-10-05 | 2013-07-16 | Amkor Technology, Inc. | Semiconductor device having through electrodes protruding from dielectric layer |
US8791501B1 (en) | 2010-12-03 | 2014-07-29 | Amkor Technology, Inc. | Integrated passive device structure and method |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02125633A (ja) * | 1988-11-04 | 1990-05-14 | Nec Corp | 集積回路 |
US5444301A (en) * | 1993-06-23 | 1995-08-22 | Goldstar Electron Co. Ltd. | Semiconductor package and method for manufacturing the same |
US5519251A (en) * | 1992-10-20 | 1996-05-21 | Fujitsu Limited | Semiconductor device and method of producing the same |
DE19712551A1 (de) * | 1996-05-17 | 1997-11-20 | Lg Semicon Co Ltd | Zuleitungsrahmen und darauf angewendetes Herstellungsverfahren für Halbleitergehäuse in Chipgröße |
-
1997
- 1997-11-18 EP EP97120173A patent/EP0844665A3/de not_active Withdrawn
- 1997-11-19 SG SG1997004089A patent/SG74604A1/en unknown
- 1997-11-20 KR KR1019970061369A patent/KR19980042617A/ko active IP Right Grant
- 1997-11-21 JP JP9321580A patent/JPH10163405A/ja active Pending
- 1997-12-12 TW TW086117537A patent/TW386272B/zh active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02125633A (ja) * | 1988-11-04 | 1990-05-14 | Nec Corp | 集積回路 |
US5519251A (en) * | 1992-10-20 | 1996-05-21 | Fujitsu Limited | Semiconductor device and method of producing the same |
US5444301A (en) * | 1993-06-23 | 1995-08-22 | Goldstar Electron Co. Ltd. | Semiconductor package and method for manufacturing the same |
DE19712551A1 (de) * | 1996-05-17 | 1997-11-20 | Lg Semicon Co Ltd | Zuleitungsrahmen und darauf angewendetes Herstellungsverfahren für Halbleitergehäuse in Chipgröße |
Non-Patent Citations (2)
Title |
---|
GILG L: "KNOWN GOOD DIE MEETS CHIP SIZE PACKAGE. SURFACE MOUNTABLE CSPS RUGGEDIZE ICS FOR HANDLING FULL TESTING ANDASSEMBLY" , IEEE CIRCUITS AND DEVICES MAGAZINE, VOL. 11, NR. 4, PAGE(S) 32 - 37 XP000589119 ISSN: 8755-3996 * page 35; figure 6 * * |
PATENT ABSTRACTS OF JAPAN vol. 014, no. 359 (E-0959), 3 August 1990 (1990-08-03) -& JP 02 125633 A (NEC CORP), 14 May 1990 (1990-05-14) * |
Cited By (82)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1018762A2 (de) * | 1998-10-16 | 2000-07-12 | Shinko Electric Industries Co. Ltd. | Halbleiteranordnung und Verfahren zu ihrer Herstellung |
EP1018762A3 (de) * | 1998-10-16 | 2001-08-22 | Shinko Electric Industries Co. Ltd. | Halbleiteranordnung und Verfahren zu ihrer Herstellung |
DE19856833A1 (de) * | 1998-12-09 | 2000-06-21 | Siemens Ag | Verfahren zur Herstellung eines integrierten Schaltkreises |
US6833609B1 (en) | 1999-11-05 | 2004-12-21 | Amkor Technology, Inc. | Integrated circuit device packages and substrates for making the packages |
US6639308B1 (en) | 1999-12-16 | 2003-10-28 | Amkor Technology, Inc. | Near chip size semiconductor package |
US8154111B2 (en) | 1999-12-16 | 2012-04-10 | Amkor Technology, Inc. | Near chip size semiconductor package |
US8410585B2 (en) | 2000-04-27 | 2013-04-02 | Amkor Technology, Inc. | Leadframe and semiconductor package made using the leadframe |
US9362210B2 (en) | 2000-04-27 | 2016-06-07 | Amkor Technology, Inc. | Leadframe and semiconductor package made using the leadframe |
US6521485B2 (en) | 2001-01-17 | 2003-02-18 | Walsin Advanced Electronics Ltd | Method for manufacturing wafer level chip size package |
US7928542B2 (en) | 2001-03-27 | 2011-04-19 | Amkor Technology, Inc. | Lead frame for semiconductor package |
US8102037B2 (en) | 2001-03-27 | 2012-01-24 | Amkor Technology, Inc. | Leadframe for semiconductor package |
US9871015B1 (en) | 2002-11-08 | 2018-01-16 | Amkor Technology, Inc. | Wafer level package and fabrication method |
US9054117B1 (en) | 2002-11-08 | 2015-06-09 | Amkor Technology, Inc. | Wafer level package and fabrication method |
US10665567B1 (en) | 2002-11-08 | 2020-05-26 | Amkor Technology, Inc. | Wafer level package and fabrication method |
US6847099B1 (en) | 2003-02-05 | 2005-01-25 | Amkor Technology Inc. | Offset etched corner leads for semiconductor package |
US7732899B1 (en) | 2005-12-02 | 2010-06-08 | Amkor Technology, Inc. | Etch singulated semiconductor package |
US8441110B1 (en) | 2006-06-21 | 2013-05-14 | Amkor Technology, Inc. | Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package |
US7968998B1 (en) | 2006-06-21 | 2011-06-28 | Amkor Technology, Inc. | Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package |
US8089141B1 (en) | 2006-12-27 | 2012-01-03 | Amkor Technology, Inc. | Semiconductor package having leadframe with exposed anchor pads |
US7687893B2 (en) | 2006-12-27 | 2010-03-30 | Amkor Technology, Inc. | Semiconductor package having leadframe with exposed anchor pads |
US7829990B1 (en) | 2007-01-18 | 2010-11-09 | Amkor Technology, Inc. | Stackable semiconductor package including laminate interposer |
US7982297B1 (en) | 2007-03-06 | 2011-07-19 | Amkor Technology, Inc. | Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same |
US8304866B1 (en) | 2007-07-10 | 2012-11-06 | Amkor Technology, Inc. | Fusion quad flat semiconductor package |
US7977774B2 (en) | 2007-07-10 | 2011-07-12 | Amkor Technology, Inc. | Fusion quad flat semiconductor package |
US7687899B1 (en) | 2007-08-07 | 2010-03-30 | Amkor Technology, Inc. | Dual laminate package structure with embedded elements |
US8283767B1 (en) | 2007-08-07 | 2012-10-09 | Amkor Technology, Inc. | Dual laminate package structure with embedded elements |
US7872343B1 (en) | 2007-08-07 | 2011-01-18 | Amkor Technology, Inc. | Dual laminate package structure with embedded elements |
US8319338B1 (en) | 2007-10-01 | 2012-11-27 | Amkor Technology, Inc. | Thin stacked interposer package |
US7777351B1 (en) | 2007-10-01 | 2010-08-17 | Amkor Technology, Inc. | Thin stacked interposer package |
US8227921B1 (en) | 2007-10-03 | 2012-07-24 | Amkor Technology, Inc. | Semiconductor package with increased I/O density and method of making same |
US8089159B1 (en) | 2007-10-03 | 2012-01-03 | Amkor Technology, Inc. | Semiconductor package with increased I/O density and method of making the same |
US7847386B1 (en) | 2007-11-05 | 2010-12-07 | Amkor Technology, Inc. | Reduced size stacked semiconductor package and method of making the same |
US7956453B1 (en) | 2008-01-16 | 2011-06-07 | Amkor Technology, Inc. | Semiconductor package with patterning layer and method of making same |
US8729710B1 (en) | 2008-01-16 | 2014-05-20 | Amkor Technology, Inc. | Semiconductor package with patterning layer and method of making same |
US7723852B1 (en) | 2008-01-21 | 2010-05-25 | Amkor Technology, Inc. | Stacked semiconductor package and method of making same |
US8067821B1 (en) | 2008-04-10 | 2011-11-29 | Amkor Technology, Inc. | Flat semiconductor package with half package molding |
US8084868B1 (en) | 2008-04-17 | 2011-12-27 | Amkor Technology, Inc. | Semiconductor package with fast power-up cycle and method of making same |
US7768135B1 (en) | 2008-04-17 | 2010-08-03 | Amkor Technology, Inc. | Semiconductor package with fast power-up cycle and method of making same |
US7808084B1 (en) | 2008-05-06 | 2010-10-05 | Amkor Technology, Inc. | Semiconductor package with half-etched locking features |
US8125064B1 (en) | 2008-07-28 | 2012-02-28 | Amkor Technology, Inc. | Increased I/O semiconductor package and method of making same |
US8184453B1 (en) | 2008-07-31 | 2012-05-22 | Amkor Technology, Inc. | Increased capacity semiconductor package |
US8299602B1 (en) | 2008-09-30 | 2012-10-30 | Amkor Technology, Inc. | Semiconductor device including leadframe with increased I/O |
US7847392B1 (en) | 2008-09-30 | 2010-12-07 | Amkor Technology, Inc. | Semiconductor device including leadframe with increased I/O |
US8432023B1 (en) | 2008-10-06 | 2013-04-30 | Amkor Technology, Inc. | Increased I/O leadframe and semiconductor device including same |
US7989933B1 (en) | 2008-10-06 | 2011-08-02 | Amkor Technology, Inc. | Increased I/O leadframe and semiconductor device including same |
US8008758B1 (en) | 2008-10-27 | 2011-08-30 | Amkor Technology, Inc. | Semiconductor device with increased I/O leadframe |
US8823152B1 (en) | 2008-10-27 | 2014-09-02 | Amkor Technology, Inc. | Semiconductor device with increased I/O leadframe |
US8089145B1 (en) | 2008-11-17 | 2012-01-03 | Amkor Technology, Inc. | Semiconductor device including increased capacity leadframe |
US8072050B1 (en) | 2008-11-18 | 2011-12-06 | Amkor Technology, Inc. | Semiconductor device with increased I/O leadframe including passive device |
US8188579B1 (en) | 2008-11-21 | 2012-05-29 | Amkor Technology, Inc. | Semiconductor device including leadframe having power bars and increased I/O |
US7875963B1 (en) | 2008-11-21 | 2011-01-25 | Amkor Technology, Inc. | Semiconductor device including leadframe having power bars and increased I/O |
US7982298B1 (en) | 2008-12-03 | 2011-07-19 | Amkor Technology, Inc. | Package in package semiconductor device |
US11869829B2 (en) | 2009-01-05 | 2024-01-09 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor device with through-mold via |
US8680656B1 (en) | 2009-01-05 | 2014-03-25 | Amkor Technology, Inc. | Leadframe structure for concentrated photovoltaic receiver package |
US10811341B2 (en) | 2009-01-05 | 2020-10-20 | Amkor Technology Singapore Holding Pte Ltd. | Semiconductor device with through-mold via |
US8058715B1 (en) | 2009-01-09 | 2011-11-15 | Amkor Technology, Inc. | Package in package device for RF transceiver module |
US8558365B1 (en) | 2009-01-09 | 2013-10-15 | Amkor Technology, Inc. | Package in package device for RF transceiver module |
US8026589B1 (en) | 2009-02-23 | 2011-09-27 | Amkor Technology, Inc. | Reduced profile stackable semiconductor package |
US8729682B1 (en) | 2009-03-04 | 2014-05-20 | Amkor Technology, Inc. | Conformal shield on punch QFN semiconductor package |
US7960818B1 (en) | 2009-03-04 | 2011-06-14 | Amkor Technology, Inc. | Conformal shield on punch QFN semiconductor package |
US8575742B1 (en) | 2009-04-06 | 2013-11-05 | Amkor Technology, Inc. | Semiconductor device with increased I/O leadframe including power bars |
US9691734B1 (en) | 2009-12-07 | 2017-06-27 | Amkor Technology, Inc. | Method of forming a plurality of electronic component packages |
US10546833B2 (en) | 2009-12-07 | 2020-01-28 | Amkor Technology, Inc. | Method of forming a plurality of electronic component packages |
US8674485B1 (en) | 2010-12-08 | 2014-03-18 | Amkor Technology, Inc. | Semiconductor device including leadframe with downsets |
US9082833B1 (en) | 2011-01-06 | 2015-07-14 | Amkor Technology, Inc. | Through via recessed reveal structure and method |
US8648450B1 (en) | 2011-01-27 | 2014-02-11 | Amkor Technology, Inc. | Semiconductor device including leadframe with a combination of leads and lands |
US9631481B1 (en) | 2011-01-27 | 2017-04-25 | Amkor Technology, Inc. | Semiconductor device including leadframe with a combination of leads and lands and method |
US9508631B1 (en) | 2011-01-27 | 2016-11-29 | Amkor Technology, Inc. | Semiconductor device including leadframe with a combination of leads and lands and method |
US9275939B1 (en) | 2011-01-27 | 2016-03-01 | Amkor Technology, Inc. | Semiconductor device including leadframe with a combination of leads and lands and method |
US9978695B1 (en) | 2011-01-27 | 2018-05-22 | Amkor Technology, Inc. | Semiconductor device including leadframe with a combination of leads and lands and method |
US8866278B1 (en) | 2011-10-10 | 2014-10-21 | Amkor Technology, Inc. | Semiconductor device with increased I/O configuration |
US10410967B1 (en) | 2011-11-29 | 2019-09-10 | Amkor Technology, Inc. | Electronic device comprising a conductive pad on a protruding-through electrode |
US9947623B1 (en) | 2011-11-29 | 2018-04-17 | Amkor Technology, Inc. | Semiconductor device comprising a conductive pad on a protruding-through electrode |
US11043458B2 (en) | 2011-11-29 | 2021-06-22 | Amkor Technology Singapore Holding Pte. Ltd. | Method of manufacturing an electronic device comprising a conductive pad on a protruding-through electrode |
US9704725B1 (en) | 2012-03-06 | 2017-07-11 | Amkor Technology, Inc. | Semiconductor device with leadframe configured to facilitate reduced burr formation |
US10090228B1 (en) | 2012-03-06 | 2018-10-02 | Amkor Technology, Inc. | Semiconductor device with leadframe configured to facilitate reduced burr formation |
US10014240B1 (en) | 2012-03-29 | 2018-07-03 | Amkor Technology, Inc. | Embedded component package and fabrication method |
US9048298B1 (en) | 2012-03-29 | 2015-06-02 | Amkor Technology, Inc. | Backside warpage control structure and fabrication method |
US9184118B2 (en) | 2013-05-02 | 2015-11-10 | Amkor Technology Inc. | Micro lead frame structure having reinforcing portions and method |
US9184148B2 (en) | 2013-10-24 | 2015-11-10 | Amkor Technology, Inc. | Semiconductor package and method therefor |
US9543235B2 (en) | 2013-10-24 | 2017-01-10 | Amkor Technology, Inc. | Semiconductor package and method therefor |
US9673122B2 (en) | 2014-05-02 | 2017-06-06 | Amkor Technology, Inc. | Micro lead frame structure having reinforcing portions and method |
Also Published As
Publication number | Publication date |
---|---|
TW386272B (en) | 2000-04-01 |
EP0844665A3 (de) | 1999-10-27 |
SG74604A1 (en) | 2000-08-22 |
KR19980042617A (ko) | 1998-08-17 |
JPH10163405A (ja) | 1998-06-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0844665A2 (de) | Halbleiterscheibengrosse Verpackung | |
US6407333B1 (en) | Wafer level packaging | |
US7816187B2 (en) | Method for fabricating semiconductor package free of substrate | |
US6255840B1 (en) | Semiconductor package with wire bond protective member | |
US5397921A (en) | Tab grid array | |
US6400004B1 (en) | Leadless semiconductor package | |
US6387732B1 (en) | Methods of attaching a semiconductor chip to a leadframe with a footprint of about the same size as the chip and packages formed thereby | |
US6689640B1 (en) | Chip scale pin array | |
US7378298B2 (en) | Method of making stacked die package | |
US7423340B2 (en) | Semiconductor package free of substrate and fabrication method thereof | |
EP0623956A2 (de) | Halbleiteranordnung ohne Chipträgeroberflächen und Herstellungsverfahren | |
US6177723B1 (en) | Integrated circuit package and flat plate molding process for integrated circuit package | |
US7939383B2 (en) | Method for fabricating semiconductor package free of substrate | |
KR101119708B1 (ko) | 집적 회로 다이를 패키징하는 방법 | |
WO2005104211A2 (en) | Land grid array packaged device and method of forming same | |
US20080197466A1 (en) | Semiconductor device and manufacturing method thereof | |
US7354796B2 (en) | Method for fabricating semiconductor package free of substrate | |
US6284566B1 (en) | Chip scale package and method for manufacture thereof | |
US20050194665A1 (en) | Semiconductor package free of substrate and fabrication method thereof | |
US20030030132A1 (en) | Semiconductor chip package and manufacturing method thereof | |
US20050184368A1 (en) | Semiconductor package free of substrate and fabrication method thereof | |
US20030214019A1 (en) | Packaging system for semiconductor devices | |
EP3840039B1 (de) | Halbleiterbauelement und entsprechendes verfahren | |
JPH02180061A (ja) | リードフレームおよび半導体装置 | |
JPH04306855A (ja) | 樹脂封止型半導体装置及びその形成方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): DE FR GB IT NL |
|
AX | Request for extension of the european patent |
Free format text: AL;LT;LV;MK;RO;SI |
|
PUAL | Search report despatched |
Free format text: ORIGINAL CODE: 0009013 |
|
AK | Designated contracting states |
Kind code of ref document: A3 Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE |
|
AX | Request for extension of the european patent |
Free format text: AL;LT;LV;MK;RO;SI |
|
17P | Request for examination filed |
Effective date: 20000414 |
|
AKX | Designation fees paid |
Free format text: DE FR GB IT NL |
|
17Q | First examination report despatched |
Effective date: 20030704 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
18D | Application deemed to be withdrawn |
Effective date: 20060516 |