TW386272B - Wafer level and chip size packaging - Google Patents

Wafer level and chip size packaging Download PDF

Info

Publication number
TW386272B
TW386272B TW086117537A TW86117537A TW386272B TW 386272 B TW386272 B TW 386272B TW 086117537 A TW086117537 A TW 086117537A TW 86117537 A TW86117537 A TW 86117537A TW 386272 B TW386272 B TW 386272B
Authority
TW
Taiwan
Prior art keywords
integrated circuit
wiring
scope
patent application
item
Prior art date
Application number
TW086117537A
Other languages
English (en)
Inventor
Walter H Schroen
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of TW386272B publication Critical patent/TW386272B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20752—Diameter ranges larger or equal to 20 microns less than 30 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20753—Diameter ranges larger or equal to 30 microns less than 40 microns

Description

Α7 Β7 五、發明説明（1 ) 發明領域 本發明一般相關於積體電绛的封裝，並更特定於積體電路的 晶圓層次封裝β · 發明背景 有關電路晶片的製造及封裝的處理是眾所周知的。通常相同 電路的陣列係圖樣在圓形的半導體晶圓上，利用習知的微石版印刷 技術9此晶圓接著被切割成許多的方形單位來彼此分隔個別的電 路’這樣每個電路只佔自己的電路晶片。 此晶片個別的配置到接線框，其以環氧基樹脂的方式固定在 一位置。接著用一導線結合器來建立晶片上的晶粒塾與接線框的個 別接線之間的電氣連接。 於晶片實體上及電氣上的接附到接線框後，晶片與接線框被放 置在鑄模設備中，其中塑膠被轉換鑄模來包圍此組件《這塑膠封裝 係用來保護晶片不要接觸到會損壞電路元件的光、没氣以及污染 物，以及機構上使整個組件堅硬耐久。此鑄模塑膠接著以在烤箱中 加熱幾個小時的方式烘乾。 接著修剪接線框的接線並形成所要的形狀。例如，此接線可 以形成給表面黏著晶片使用的”海鷗翼”形狀。在這個階段，執行不同 的電氣以及機構測試來決定此晶片是否如預期的工作。 -3 - 本紙張尺度適用中國國家揉準（CNS ) Α4規格（210Χ297公釐） Λ3. (請先聞讀背面之注$項再填寫本頁) J'e 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 A7 _B7_ 五、發明説明（2) 這個電路晶片工業是非常的成本競爭的β因此希望要縮短， 流暢或消除封裝的步驟來縮短生產時間以及降低晶片的生產成本。 發明概要 因此本技藝產生一需求來改善積體電路的封裝。本發明提供 一種在晶圓層次封裝積體電路的方法。另外，本發明提供晶片尺寸 的封裝。 根據本發明，積體電路的封裝可以包含一積體電路晶片。接 線框可以面對積體電路晶片之電路面。此接線框可以至少包含 一接線來在電狄上的藉由連接器連結到此積艘電路。此接線可以是 在積體電路晶片的週邊中。一密封可以覆蓋此積體電路，連接器以 及接線框的一部份。接線框的剩餘部份是可以曝露在密封外。 更特定的，根據本發明之一具體實例，一積體電路可以在晶 圓層次封裝。在此具體實例中，一個薄片的接線植可以面對複數個積體 電^晶片。此密封可以覆蓋此積體電路以及每個接線框的一部份。每個 密封的積體電路以及面對的接線框可以形成個別的積體電路封裝。 本發明的重要技術優點包含提供積體電路的晶片尺寸封 裝。尤其，接線框、連接器以及密封並未超出面對的積體電路晶 片的週邊。因此，封裝的體積可以達到最小，而此晶片可用在需要 非常小的晶片的裝置上》 -4 - }紙張尺歧用中關家鮮（CNS ) Α4胁（21GX297公釐) ~ Ί 裝 訂 線 {請先聞讀背面之注意事項再填寫本頁) A7 B7__ 五、發明説明（3 ) 本發明的另一個技術上的優點包含提供在晶圓層次封裝積 體電路晶片的方法。尤其，積體電路晶片可以它在仍然是晶圓的 一部份的同時來封裝。因此，封裝程序的完成可以當作是晶圓製造 程序的延續β這可以用來流暢及縮短組件與封裝的程序。 其他的技術優點對於熟習本技藝的人可以輕易的從下面的 圖式’說明以及申請專利範圍而變得更明顯。 圖示簡述 為了更完整的了解本發明及其優點，現在參考下面併同隨附 圖式的說明，其中類似的參考數字代表類似的零件，其中： 圖1Α-Ε為連串示意的橫切面圓，說明一積艘電路的晶圓層 次封裝，根據本發明之一具體實例。 較佳具體實例的詳細說明 經濟部智慧財產局員工消費合作社印製 本發明的較佳具體實例及其優點現在藉由更詳盡地參考圖 式的圖1Α-Ε來得到最佳的理解’其中在所有的幾個觀點中類似的數 字參考到類似的零件。囷1Α-Ε說明在晶圓層次封裝積體電路的方 法。晶圓層次的封裝的完成可以當作晶圓製造程序的延續來流暢化 及縮短封裝的程序》 圈U顯示一圓樣的晶圓1〇。圖樣的晶圓可以包含基質12 以及形成在基質12的表面16中的複數個積體電路14。此基質12 可以包含一或多個半導體材料層》例如，此基質12可以包含在晶圓 _：________ 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297公釐） A7 __ _B7___ 五、發明説明（4 ) 上成長的外延層。 (請先閲讀背面之注意事項再填寫本頁) 每個積體電路14可以包含複數個在電氣上連結到此積體電 路14的連結塾18 ^如在下面會更詳細說明的，連結些18提供電氣 上的接觸，透過它積體電路14可以連接到外部的元件。在一具體實 例中’連結墊18可以配置在積艘電路14的中心線20上。在此具趙 實例中’連結墊18的數目與組態可隨應用的不同而變化。例如積艘 電路14可以包含一或多個交錯的或平行的連結整* a列。可以理解 的’在本發明的範疇内’此連結墊18可以配置在積體電路μ的其 他地方〇 每個積體電路14以及基質12的周圍部份可以定義一個別的 積體電路晶片22。每個此積艘電路晶片22可以封裝來提供對外部 元件的連接以及提供對環境因素的防護》典型的，圖樣的晶圓被分 割成個別的積體電路晶片以便封裝。每個此積體電路晶片分別的附 接以及連結到接線框，並接著與該接線框一起密封。這種方法的一 個問題是’積體電路晶片的分別封裝既耗費時間且成本昂貴。另外， 它讓封裝的完成無法成為晶圓製造程序的延續。 經濟部智慧財產局員工消費合作社印製 本發明藉由提供在晶圓層次對積體電路晶片的封裝方法來 解決這個問題。如同在下面更詳盡的說明，此積艘電路晶片22在仍 然是晶圓10—部份的同時封裝。因此，封裝程序的完成可以當作是 晶圓製造程序的延續。這用來流暢及縮短封裝的程序。再者，.如下 面更詳盡的說明’本發明的這個方法產生晶片大小的封裝。結果， 封裝的積體電路晶片22可以用在需要小型化裝置所耗費的面積不大 • 6 - 本紙張尺度適用中圃國家揉準（CNS > Α4規格（2!〇>〇97公釐） ~ ' Α7 Β7 五、發明説明（5 ) 於個別的晶片的應用上。 參考圖1B，聚合物塗層24可以用在基質12的表面16。聚 合物塗層24可以提供密封材料.更耔的黏著，其將會覆蓋並保護積體 電路14。傳統的圓樣蝕刻技術可以用來防止聚合物塗層24蓋住連 結墊18。可以理解的，在本發明的範疇内可以使用其他的或不使用 塗層。 一薄片的接線框26可以配置在基質12的表面16的反面。 此薄片的接線框26可以包含複數個個別的接線框28 ,其每一個提 供積體電路晶片22的一個連接。 此薄片的接線框26可為單一的薄片材料》在一具體實例 中，此接線框28的材料可以是局部被覆銀的合金42。可以理解在 本發明的範疇内接線框28可以用不同的其他材料。 每一個接線框28在面對之積體電路晶片22的週邊32令包含 複數個接線30。因此’接線30不會重疊到其他的積體電路晶片22 ^ 如在下面會做更詳盡說明的，接線30可以電氣地連結到連結墊18 並從密封延伸出來連接外部的元件β 在一具體實例中’接線30可以是雙層的組態。在這種組態 中，如圓1Β所顯示的，較上方的接線3〇組可以配置在較下方的接 線30組的上面°因此雙層組態提供積艘電路晶片22較多數目的接 線30 〇接線框28也可以包含連接一或多個接線3〇的延長細條（未 類示）°此細條可以拿來當作地電位或是電源電壓導體。可以理解的 -7 - 本紙張尺度適用中國國家揉準（CNS ) Α4規格（2丨ΟΧ297公釐） --------穿-- (請先閲讀背面之注意事項再填寫本頁) τ
I 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 A7 _B7 五、發明説明（6 ) 在本發明的範疇中可以使用其他的接線框28組態。 每一接線30可以有一末端點34來連接到外部裝置^在一具 體實例令，如圖1B所顯示的’此末端點34實質上位於一平面上並 可以延伸積體電路晶片22的週邊32 »在此具體實例中，藉由用來將 囷樣的晶圓10切割成個別的積艘電路晶片22的後處理之封裝分割處 理，接線框28可以從接線框薄片26切割出來。 如圖1所顯示的，每個末端點34可以實質的平行於積艘電 路晶片22。在一具體實例中，此末端點34可以包含鈀此鈀的預 被覆可以讓末端點34更輕易的焊接到印刷電路板以及類似者。可理 解的是，在本發明的範疇中’此末端點34可以包含其他的或沒有任 何的預被覆。例如，此末端點34可以預被覆銲錫。 每個接線框28可以固定至面對的積體電路晶片22。在一具 體實例中，一黏性膠帶40可以用來將接線框28固定在面對的積體 電路晶片22。此黏性膠帶40最好是非傳導性的以防止電氣短路。 此黏性膠帶可以雙面發黏的來將聚合物層24黏在接線框28的接線 30。此黏性膠帶可以不同的方式及不同的厚度附接到接線框28。這 樣的方法是眾所周知的而不再說明。 另外，上方接線30組可以黏性膠帶40固定在下方的接線3〇 組。雖然黏性的膠帶的用處在接線30的附接部份討論，可以理解的 是，接線框28可以另外的附接到面對的積體電路晶片22。類似的， 上方的接線可以另外的附接到下方的接線^例如，接線30及/或接 線框28可以機構上地以環氧基樹脂或類似的來固定。 ___- 8 -_ 一 本紙張尺度逍用中國國家椹準（CNS >A4規格（210X297公着） ' I I i I I I I I I I i I 訂— I I . I 線 (請先閱讀背面之注$項再填寫本頁) 丨 經濟部智慧財產局員工消費合作社印製 A7 ___B7 五、發明説明（7 ) 參考圖1C，一連接器42可以電氣地的將接線3〇連結到面對 之積體電路晶片22的連結藝18。在一具嫂實例中，每一連接器42 可以包含一導線以連結到一接線3〇及一連結墊18。在此具體實例 中，導線可以任何細的，耐用的導體金屬。在特定的具體實例中， 此導線可以是直徑大約1.0到1.2釐的金線。此導線可以是楔子， 求或類似的連結到接線30及連結墊18 ^在一具體實例中，此導線 連結處理可以用梯形迴路，其產生低迴路的外形。可以理解的是， 在本發明的範疇中，此連接器42可以其他的導線。例如連接器42 可以是一銲錫或是金球，或替換的導線及球。 參考圓1D ’此積體電路晶片22，連接器42以及至少接線 框28的一部份可以被密封。此密封44係用來保護22不會曝露在造 成電珞元件損壞的環境因素下。此密封44也可以用來讓整個組件在 機構上的堅硬及耐久。每個密封的積體電路、連接器及面對的接線 框可以形成個別的積體電路封裝50 » 在一具體實例中，此密封44也可以只塗抹在晶園1〇包含積 體電路14、連接器以及接線框28的這一面。此密封44也可以藉由 注射器如液體般的塗抹。在此具體實例中，此液體可以先是低黏度 並接著快速的凝結。可以理解的是，在本發明的範疇中，此密封44 可以是另外的方式塗抹。例如，密封44可以用傳統的轉換鑄模或3ρ 的鑄模技術來塗袜，一鑄模腔就像晶圓1〇或類似的一樣大^可以進 一步理解的是，在本發明的範疇中，晶圓1Q的兩面都可以密封。 如圖Π)所顯示的，每一接線30的剩餘部份在密封後仍可以 -δ - 本紙張尺度適用中圃國家樣準（CNS ) Α4規格7 210Χ297公釐) ·' II I II 装 — — .1 訂 —i 線 (锖先閲讀背面之注$項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 A7 B7 --- -----—___________-—* 五、發明説明（8 ) 維持曝露在外的。接線30的曝露部份提供積體電路晶片22對外部 元件的連接，例如印刷電路板及類似的，在一具體實例中，接線3〇 的曝露部份可以是末端點34。如前面所討論的，末端點34可以是 預被覆鈀以便容易的焊接到印刷電路板或類似者。 末端點34可以藉由調節塗抹到晶圓iq的密封料量而予以 曝露。在囷1D的具體實例，密封44的艘積必須是可以填滿末 端點34未焊接處的數量。在此具體實例中，末端點34可以實質的 平行於積體電路晶片22來讓密封44填滿末端點34未焊接處46而 不會復蓋末端點34的外面端46。此實質平行的末端點34也可以讓 封裝的晶片在印刷電路板或類似的上面保持平坦。 參考圖1E，密封的晶圓可予以分割以使得個別的積艘電路封裝 50彼此分開。根據本發明，積體電路封裝5〇可以完整並輕易的測試、 模板印刷及運送給客戶。然而，如果要的話，雜電路封裝5〇的端 點52及/或基質12的背φ 54可以先密封包裝。因此，本發明提供 一種在晶圓層次封裝積體電路的方法。此晶圓層次的封裝完成可以 當作晶圓製造程序的延續來流暢並縮短封裝程序β 如圖1Ε所顯示的’每一積體電路封裝5〇可以是晶片尺寸的 封裝。因此，接線框28、連接器42及密封44都不會延伸到積體電 路晶片22的週邊32之外。結果，封裝的效積達到最小化而此晶片 可以用在需要極小晶片的裝置中。 雖然本發明錢減財例加W賴，仍可建議熟習本技藝 的人做不同的改變及修改^明·所想要包含的雜改變及修改均 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） II--------装丨------訂------線 C请先聞讀背面之注^^項再填寫本頁) A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（9 ) 在隨附的申請專利範圍的範疇中。 圈式元件對照表： 10 晶圓 12 基質 14 積體電路 16 表面 18 連結墊 20 中心線 22 積體電路晶片 24 聚合物塗層 26 薄片接線框 28 個別接線框 30 接線 32 周邊 34 末端點 40 黏性膠帶 42 連接器 44 密封 46 未焊接處 50 積體電路封裝 54 背面 IT--------^-------1T------0 (請先閲讀背面之注意事項再填寫本頁) -11 - 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）

Claims (1)

  1. 知年日修正
    、 經濟部智慧財產局員工消費合作社印製 專利申請案第86117537號 ApPln* No. 86117537 t請專利範圍中文本-附件= telded Claims in Chirmse - PnJ-^ κ (ν5?Λ8 年 < 月、 Cbubmitted on August ^ , 1999) 種積體電路封裝，包含： 一具有一表面之積體電路晶片，含有一積體電路， 該表面上設有連結墊； —接線框’面對該表面且安置在該表面上； 此接線框含有至少一藉連接器在電氣上連結到積體 電路之一連結墊的接線； 此接線位在積體電路的週邊之中； 一覆蓋此積體電路、連接器以及此接線框的一部份 的密封；以及 此接線框的剩餘部份曝露在此密封之外。 2.如申請專利範圍第1項的積體電路封裝，其中此接線框 含有複數個接線，且一固定劑將接線固定至該表面。 3_如申請專利範圍第2項的積體電路封裝，其中固定劑在 電氣上與該表面絕緣’且該固定劑分隔該接線與該表 面。 4如申請專利範圍第2 的積體電路封裝，其中連接器為 連結到接線及到積體電路的導線。 5.如申請專利範圍第2項的積體電路封裝，還包含： 一連結墊，電氣的連結到此積體電路； .此連結塾係配置為接近此積體電路的中心線；以及 12 本紙張尺度逍用中國國家標率（CNS ) A4规格（210x297公釐）紐EVAPC86578-Claim/Tim ----------^------ir------0 (請先Μ讀背面之注意事項再填寫本頁) 知年日修正
    、 經濟部智慧財產局員工消費合作社印製 專利申請案第86117537號 ApPln* No. 86117537 t請專利範圍中文本-附件= telded Claims in Chirmse - PnJ-^ κ (ν5?Λ8 年 < 月、 Cbubmitted on August ^ , 1999) 種積體電路封裝，包含： 一具有一表面之積體電路晶片，含有一積體電路， 該表面上設有連結墊； —接線框’面對該表面且安置在該表面上； 此接線框含有至少一藉連接器在電氣上連結到積體 電路之一連結墊的接線； 此接線位在積體電路的週邊之中； 一覆蓋此積體電路、連接器以及此接線框的一部份 的密封；以及 此接線框的剩餘部份曝露在此密封之外。 2.如申請專利範圍第1項的積體電路封裝，其中此接線框 含有複數個接線，且一固定劑將接線固定至該表面。 3_如申請專利範圍第2項的積體電路封裝，其中固定劑在 電氣上與該表面絕緣’且該固定劑分隔該接線與該表 面。 4如申請專利範圍第2 的積體電路封裝，其中連接器為 連結到接線及到積體電路的導線。 5.如申請專利範圍第2項的積體電路封裝，還包含： 一連結墊，電氣的連結到此積體電路； .此連結塾係配置為接近此積體電路的中心線；以及 12 本紙張尺度逍用中國國家標率（CNS ) A4规格（210x297公釐）紐EVAPC86578-Claim/Tim ----------^------ir------0 (請先Μ讀背面之注意事項再填寫本頁) 申請專利範圍 此連結器是連結到此接線及到此連結墊的導線。 6. 如申請專利範圍第2項的積體電路封裝，其中此接線被 覆有把。 7. —種封裝的晶圓，包含： 一含有複數個積體電路晶片的晶圓，各晶片具有一 表面； 每一積體電路晶片含有一積體電路，於該表面上嗖 有連結墊； ° 裝 一薄片的接線框，面對該表面且安置在該表面上，· 每-接線框含有-藉由連接器在電氣上連結到積體 電路之一連結墊的接線； 各接線框之接線位在面對之積體電路的遇邊之申； 一密封覆蓋此積雜電路、連接器以及每-接線框的 一部份；以及 每一接線框的剩餘部份曝露在密封之外。 專利範圍第7項的封裝的晶圓，其中薄片的接線 框為單一薄片的材料。 9·=請專利範圍第8項的封裝的晶圓，每一接線框還包 :複數個接線，且一固定劑將接線固定至該表面，每一 接線位在面對之積體電路晶片的週邊中。 ㈣9項的封裝的晶圓’其中固定劑在電 上’且該固定劑分隔該接線與該表面^ 11·=睛專利範圍第9項的封裝的晶圓，其中每一連接器 為連結到接線及到面對之積體電路的導線。 |_____ * 13 - (CNS) A4*#. A8 B8 C8 D8 386272 六、申請專利範圍 12. 如申請專利範圍第9項的封裝的晶圓，還包含： 一連結墊，在電氣上連結每一個積體電路； 此連結墊係配置為接近此積體電路的中心線；以及 此連接器為連結到此接線及到此連結墊的導線。 13. 如申請專利範圍第9項的封裝的晶圓，其中此接線被覆 有把。 14. 一種封裝積體電路的方法，包含步驟： 配置一薄片的接線框面對複數個積體電路晶片，各 晶片含有一積體電路，每一接線框含有一接線在一面對 的積體電路晶片的週邊中； 電氣地連結每一接線框的此接線到面對的積體電路 晶片；以及 密封此積體電路以及每一接線框的一部份，每個密 封的積體電路以及面對的接線框形成一個別的積體電路 封裝。 15. 如申請專利範圍第14項的方法，其中此薄片的接線框 為單一薄片的材料。 16_如申請專利範圍第14項的方法，其中將此接線與面對 的積體電路做電氣地連結的步驟包含將導線連結到此接 線及到此面對的積體電路的連結墊之步驟。 17. 如申請專利範圍第14項的方法，還包含將積體電路封 裝做彼此分離的步驟。 18. 如申請專利範圍第14項的方法，還包含將每一接線框 附接到面對的積體電路的步驟。 -14 - 本紙張尺度適用中國國家標準（CNS > A4規格（210X297公釐） 1·^-- (請先閲讀背面之注意事項再填寫本頁) •訂 線 經濟部智慧財產局員工消費合作社印製 ^ A8 38027A ll D8 六、申請專利範圍 19. 如申請專利範圍第14項的方法，還包含在積體電路晶 片上形成聚合物層的步驟。 20. 如申請專利範圍第14項的方法，還包含在接線上被覆 把的步驟。 (請先聞讀背面之注$項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 -15 - 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐）
TW086117537A 1996-11-21 1997-12-12 Wafer level and chip size packaging TW386272B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US3146496P 1996-11-21 1996-11-21

Publications (1)

Publication Number Publication Date
TW386272B true TW386272B (en) 2000-04-01

Family

ID=21859599

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086117537A TW386272B (en) 1996-11-21 1997-12-12 Wafer level and chip size packaging

Country Status (5)

Country Link
EP (1) EP0844665A3 (zh)
JP (1) JPH10163405A (zh)
KR (1) KR19980042617A (zh)
SG (1) SG74604A1 (zh)
TW (1) TW386272B (zh)

Families Citing this family (67)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6143981A (en) 1998-06-24 2000-11-07 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
JP2000124350A (ja) * 1998-10-16 2000-04-28 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
DE19856833A1 (de) * 1998-12-09 2000-06-21 Siemens Ag Verfahren zur Herstellung eines integrierten Schaltkreises
KR20010004529A (ko) 1999-06-29 2001-01-15 김영환 웨이퍼 레벨 패키지 및 그의 제조 방법
US6580159B1 (en) 1999-11-05 2003-06-17 Amkor Technology, Inc. Integrated circuit device packages and substrates for making the packages
US6639308B1 (en) 1999-12-16 2003-10-28 Amkor Technology, Inc. Near chip size semiconductor package
US7042068B2 (en) 2000-04-27 2006-05-09 Amkor Technology, Inc. Leadframe and semiconductor package made using the leadframe
US6521485B2 (en) 2001-01-17 2003-02-18 Walsin Advanced Electronics Ltd Method for manufacturing wafer level chip size package
KR100369393B1 (ko) 2001-03-27 2003-02-05 앰코 테크놀로지 코리아 주식회사 리드프레임 및 이를 이용한 반도체패키지와 그 제조 방법
US7723210B2 (en) 2002-11-08 2010-05-25 Amkor Technology, Inc. Direct-write wafer level chip scale package
US6905914B1 (en) 2002-11-08 2005-06-14 Amkor Technology, Inc. Wafer level package and fabrication method
US6798047B1 (en) 2002-12-26 2004-09-28 Amkor Technology, Inc. Pre-molded leadframe
US6847099B1 (en) 2003-02-05 2005-01-25 Amkor Technology Inc. Offset etched corner leads for semiconductor package
US6750545B1 (en) 2003-02-28 2004-06-15 Amkor Technology, Inc. Semiconductor package capable of die stacking
US6794740B1 (en) 2003-03-13 2004-09-21 Amkor Technology, Inc. Leadframe package for semiconductor devices
US7507603B1 (en) 2005-12-02 2009-03-24 Amkor Technology, Inc. Etch singulated semiconductor package
US7572681B1 (en) 2005-12-08 2009-08-11 Amkor Technology, Inc. Embedded electronic component package
US7902660B1 (en) 2006-05-24 2011-03-08 Amkor Technology, Inc. Substrate for semiconductor device and manufacturing method thereof
US7968998B1 (en) 2006-06-21 2011-06-28 Amkor Technology, Inc. Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package
US7687893B2 (en) 2006-12-27 2010-03-30 Amkor Technology, Inc. Semiconductor package having leadframe with exposed anchor pads
US7829990B1 (en) 2007-01-18 2010-11-09 Amkor Technology, Inc. Stackable semiconductor package including laminate interposer
US7982297B1 (en) 2007-03-06 2011-07-19 Amkor Technology, Inc. Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same
US7977774B2 (en) 2007-07-10 2011-07-12 Amkor Technology, Inc. Fusion quad flat semiconductor package
US7687899B1 (en) 2007-08-07 2010-03-30 Amkor Technology, Inc. Dual laminate package structure with embedded elements
US7777351B1 (en) 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
US8089159B1 (en) 2007-10-03 2012-01-03 Amkor Technology, Inc. Semiconductor package with increased I/O density and method of making the same
US7847386B1 (en) 2007-11-05 2010-12-07 Amkor Technology, Inc. Reduced size stacked semiconductor package and method of making the same
US7956453B1 (en) 2008-01-16 2011-06-07 Amkor Technology, Inc. Semiconductor package with patterning layer and method of making same
US7723852B1 (en) 2008-01-21 2010-05-25 Amkor Technology, Inc. Stacked semiconductor package and method of making same
US8067821B1 (en) 2008-04-10 2011-11-29 Amkor Technology, Inc. Flat semiconductor package with half package molding
US7768135B1 (en) 2008-04-17 2010-08-03 Amkor Technology, Inc. Semiconductor package with fast power-up cycle and method of making same
US7808084B1 (en) 2008-05-06 2010-10-05 Amkor Technology, Inc. Semiconductor package with half-etched locking features
US8125064B1 (en) 2008-07-28 2012-02-28 Amkor Technology, Inc. Increased I/O semiconductor package and method of making same
US8184453B1 (en) 2008-07-31 2012-05-22 Amkor Technology, Inc. Increased capacity semiconductor package
US7847392B1 (en) 2008-09-30 2010-12-07 Amkor Technology, Inc. Semiconductor device including leadframe with increased I/O
US7989933B1 (en) 2008-10-06 2011-08-02 Amkor Technology, Inc. Increased I/O leadframe and semiconductor device including same
US8008758B1 (en) 2008-10-27 2011-08-30 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe
US8089145B1 (en) 2008-11-17 2012-01-03 Amkor Technology, Inc. Semiconductor device including increased capacity leadframe
US8072050B1 (en) 2008-11-18 2011-12-06 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including passive device
US7875963B1 (en) 2008-11-21 2011-01-25 Amkor Technology, Inc. Semiconductor device including leadframe having power bars and increased I/O
US7982298B1 (en) 2008-12-03 2011-07-19 Amkor Technology, Inc. Package in package semiconductor device
US20170117214A1 (en) 2009-01-05 2017-04-27 Amkor Technology, Inc. Semiconductor device with through-mold via
US8680656B1 (en) 2009-01-05 2014-03-25 Amkor Technology, Inc. Leadframe structure for concentrated photovoltaic receiver package
US8058715B1 (en) 2009-01-09 2011-11-15 Amkor Technology, Inc. Package in package device for RF transceiver module
US8026589B1 (en) 2009-02-23 2011-09-27 Amkor Technology, Inc. Reduced profile stackable semiconductor package
US7960818B1 (en) 2009-03-04 2011-06-14 Amkor Technology, Inc. Conformal shield on punch QFN semiconductor package
US8575742B1 (en) 2009-04-06 2013-11-05 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including power bars
US8796561B1 (en) 2009-10-05 2014-08-05 Amkor Technology, Inc. Fan out build up substrate stackable package and method
US8937381B1 (en) 2009-12-03 2015-01-20 Amkor Technology, Inc. Thin stackable package and method
US9691734B1 (en) 2009-12-07 2017-06-27 Amkor Technology, Inc. Method of forming a plurality of electronic component packages
US8324511B1 (en) 2010-04-06 2012-12-04 Amkor Technology, Inc. Through via nub reveal method and structure
US8294276B1 (en) 2010-05-27 2012-10-23 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
US8440554B1 (en) 2010-08-02 2013-05-14 Amkor Technology, Inc. Through via connected backside embedded circuit features structure and method
US8487445B1 (en) 2010-10-05 2013-07-16 Amkor Technology, Inc. Semiconductor device having through electrodes protruding from dielectric layer
US8791501B1 (en) 2010-12-03 2014-07-29 Amkor Technology, Inc. Integrated passive device structure and method
US8674485B1 (en) 2010-12-08 2014-03-18 Amkor Technology, Inc. Semiconductor device including leadframe with downsets
US8390130B1 (en) 2011-01-06 2013-03-05 Amkor Technology, Inc. Through via recessed reveal structure and method
TWI557183B (zh) 2015-12-16 2016-11-11 財團法人工業技術研究院 矽氧烷組成物、以及包含其之光電裝置
US8648450B1 (en) 2011-01-27 2014-02-11 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands
US8866278B1 (en) 2011-10-10 2014-10-21 Amkor Technology, Inc. Semiconductor device with increased I/O configuration
US8552548B1 (en) 2011-11-29 2013-10-08 Amkor Technology, Inc. Conductive pad on protruding through electrode semiconductor device
US9704725B1 (en) 2012-03-06 2017-07-11 Amkor Technology, Inc. Semiconductor device with leadframe configured to facilitate reduced burr formation
US9048298B1 (en) 2012-03-29 2015-06-02 Amkor Technology, Inc. Backside warpage control structure and fabrication method
US9129943B1 (en) 2012-03-29 2015-09-08 Amkor Technology, Inc. Embedded component package and fabrication method
KR101486790B1 (ko) 2013-05-02 2015-01-28 앰코 테크놀로지 코리아 주식회사 강성보강부를 갖는 마이크로 리드프레임
KR101563911B1 (ko) 2013-10-24 2015-10-28 앰코 테크놀로지 코리아 주식회사 반도체 패키지
US9673122B2 (en) 2014-05-02 2017-06-06 Amkor Technology, Inc. Micro lead frame structure having reinforcing portions and method

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02125633A (ja) * 1988-11-04 1990-05-14 Nec Corp 集積回路
JP2934357B2 (ja) * 1992-10-20 1999-08-16 富士通株式会社 半導体装置
KR0152901B1 (ko) * 1993-06-23 1998-10-01 문정환 플라스틱 반도체 패키지 및 그 제조방법
KR0179920B1 (ko) * 1996-05-17 1999-03-20 문정환 칩 사이즈 패키지의 제조방법

Also Published As

Publication number Publication date
KR19980042617A (ko) 1998-08-17
EP0844665A2 (en) 1998-05-27
EP0844665A3 (en) 1999-10-27
JPH10163405A (ja) 1998-06-19
SG74604A1 (en) 2000-08-22

Similar Documents

Publication Publication Date Title
TW386272B (en) Wafer level and chip size packaging
KR100263723B1 (ko) 가요성 박막 반도체 패키지
TW502347B (en) Semiconductor device and method of manufacturing same
US7037756B1 (en) Stacked microelectronic devices and methods of fabricating same
US6300679B1 (en) Flexible substrate for packaging a semiconductor component
TW541635B (en) Semiconductor package and a method for producing the same
US5677575A (en) Semiconductor package having semiconductor chip mounted on board in face-down relation
TW312844B (zh)
TW464998B (en) Film-type carrier tape, semiconductor module, semiconductor apparatus and its manufacturing method, mounted substrate and electronic machine
TW558817B (en) A semiconductor package and the method of the semiconductor package
TW200924147A (en) Stackable integrated circuit package
US7723835B2 (en) Semiconductor device package structure
JPH0786477A (ja) 回路パッケージおよびその形成方法
US6987313B2 (en) Semiconductor device
TW201036124A (en) Package structure and manufacturing method thereof
TW200531246A (en) Semiconductor package
TW200534454A (en) Exposed pad module integrated a passive device therein
TW543127B (en) Chip scale package with improved wiring layout
US20040152242A1 (en) Device package utilizing interconnect strips to make connections between package and die
US5596172A (en) Planar encapsulation process
TWI250597B (en) Method for manufacturing multi-chip package having encapsulated bond-wires between stack chips
JPH09293750A (ja) テープキャリアパッケージ及びそのテープキャリアパッケージを備えた液晶表示装置
JPH10213627A (ja) チップキャリア及びそれを用いた半導体装置のバーンイン方法及びテスト方法
US11688715B2 (en) Semiconductor die with multiple contact pads electrically coupled to a lead of a lead frame
TW408458B (en) Method and structure for taped multi-chip package