EP0344259A1 - Procede et agencement de fabrication de boitiers de dispositifs semi-conducteurs - Google Patents

Procede et agencement de fabrication de boitiers de dispositifs semi-conducteurs

Info

Publication number
EP0344259A1
EP0344259A1 EP89900040A EP89900040A EP0344259A1 EP 0344259 A1 EP0344259 A1 EP 0344259A1 EP 89900040 A EP89900040 A EP 89900040A EP 89900040 A EP89900040 A EP 89900040A EP 0344259 A1 EP0344259 A1 EP 0344259A1
Authority
EP
European Patent Office
Prior art keywords
die
semiconductor device
device package
conductive
conductive layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP89900040A
Other languages
German (de)
English (en)
Other versions
EP0344259A4 (en
Inventor
Jon Long
Rachel S. Sidorovsky
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LSI Corp
Original Assignee
LSI Logic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LSI Logic Corp filed Critical LSI Logic Corp
Publication of EP0344259A1 publication Critical patent/EP0344259A1/fr
Publication of EP0344259A4 publication Critical patent/EP0344259A4/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • This invention relates to a method and means of fabricating a semiconductor device package.
  • Prior art semiconductor device packages are. fabricated in a sandwich mold configuration wherein the semiconductor device is encapsulated forming a package on both sides of the die.
  • the larger molded package tends to curl, which results in a defective or unusable device.
  • the package has any minute openings or cracks that allow moisture to penetrate to the elements of the semiconductor device, delamination of the semiconductor die can occur, which will render the device defective, or will cause the device to have a reduced operating life.
  • the use of a mold to construct the package increases the height and area of the package significantly.
  • a composite package assembly such as disclosed in the aforementioned copending patent applications, is formed with a rigid lead frame and a thin flexible tape-like structure.
  • the tape-like structure is configured with lead fingers that are connected to leads of the lead frame.
  • the semiconductor assembly which includes bond.wires, is encapsulated using a two section mold that requires a number of molding steps to encompass .the semiconductor device with the lead frame, tape-like structure, bond wires and conductive leads.
  • Conventional semiconductor molded packages which are standard in the semiconductor industry accommodate up to 160 conductive leads, which typically are spaced between 50 and 25 milli-inches from center to center. As the number of leads are increased, the number of bond wires that connect to the leads are increased accordingly. The increase in bond wires results in a larger package.
  • a major objective of the semiconductor industry is to make semiconductor devices with more conductive leads and yet to have a more compact package.
  • semiconductor die with more die pads can be used, which requires closer spacing of the leads of the semiconductor assembly.
  • higher circuit operating speeds- can be realized ' with improved operating reliability.
  • Another object is to provide a semiconductor package that affords a relatively large number of conductive leads and external pins.
  • a further object is to provide a semiconductor package that affords a high degree of protection frpm moisture.
  • a tape is formed of a patterned insulating layer and a conductive layer that is joined to the insulating layer.
  • a semiconductor die is attached to a pad on one surface of the tape and electri ⁇ cally connected to leads of the conductive layer.
  • An insulating coat is dispensed over the die and wire leads.
  • a tape element is adhered to the conductive layer.
  • a package frame or body frame is joined to the tape surrounding the semiconductor die and electrical connections and leads. The body frame serves to contain an encapsulant that is distributed over the top of the body frame, the die and conductive wires and leads.
  • conductive bumps in lieu of wire leads are used for electrical connection.
  • Tab bonding is employed to join the bumps which are formed on the die and the conductive layer.
  • Figure 1 is a sectional side view of a semiconductor assembly, in part, made in accordance with this invention.
  • Figure 2 depicts the attachment of a semiconductor die to the partial assembly of Figure 1;
  • Figure 3 illustrates the wire bonding of the die to conductive lead fingers of the assembly;
  • Figure 4 shows the application of a protective coating over the semiconductor die and bond wires
  • Figure 5 illustrates the partial assembly, turned upside down, for attaching an aligned backside tape, in accordance with this invention
  • Figure 6 illustrates the joinder of a frame body to the assembly
  • Figure 7 is a sectional view of a semiconductor device package, made in accordance with this invention.
  • Figure 8 is a top plan view, par ⁇ ly opened, depicting a semiconductor device package, made in accordance with this invention.
  • Figure 9 is a sectional view of a semiconductor device package, using tape automated bonding (TAB), to join and electrically connect the semiconductor die to the patterned conductive layer by means of conductive bumps; and
  • TAB tape automated bonding
  • FIG. 10 is an exploded view of the semiconductor device package of this invention. Similar numerals refer to similar elements throughout the drawing.
  • a wire bondable tape 10 is formed of a patterned insulating layer 12 made of Kapton (trademark of DuPont), for e:. ⁇ . ⁇ ple» and a gold plate layer 14 that is joined to the Kapton layer.
  • the gold plate layer is about 30-40 microinches thick, by way of example.
  • a thin copper film 16 is sputtered onto the Kapton layer 12 prior to deposition of the gold layer 14 to provide conductivity to the layer 12 and to facilitate adhesion of the gold to the Kapton material.
  • the layer 12 is etched and patterned with cavities for down bonding, as disclosed in copending U.S. Patent Application Serial No. 07/049,641, filed on May 13, 1987.
  • the patterned wire bondable tape is positioned in a fixture 18, to provide flatness to the tape.
  • Die attach epoxy 22, such as Amicon 990C (trademark of Amicon) is spread cr. a die attach pad 20 formed on one surface of the wire bondable tape.
  • a semiconductor die 24 is then aligned and placed on the die attach epoxy as illustrated in Fig. 2.
  • the die attached unit is placed in an oven for curing at a maximum cure temperature of about 150°C for a maximum cure time of about one hour.
  • the cured die attached unit is placed on a vacuum heater block (such as disclosed in copending U.S. Patent Application Serial Number 07/043,894 filed April 29, 1987) to hold the unit rigid and at a temperature of about 200°C. Then the unit is wire bonded thermosonically with 0 gold wires 26 as shown in Fig. 3 to make electrical connec ⁇ tion between the die 24 and lead fingers or conductive elements of the patterned gold layer 14.
  • a silicone gel 28, such as Dow Corning Ql-4939, having a 1 to 10 mixing ratio of curing agent to its base is then applied as a die coat 5 over the die, first starting in the corners and then distributing the gel in the middle of the die. The gel is permitted to flow to cover the die and wires ⁇ see Fig. 4) but. is contained within a prescribed area, as disclosed in the aforementioned copending patent application Serial No. 0 07/049,641.
  • the die coated unit is then cured in an oven at about 150°C for about one hour.
  • the unit is turned upside down and is positioned within an alignment fixture 30 as depicted in Fig. 5.
  • the fixture 18 is used to protect the die, wires 5 and die coat from damage.
  • a tape element 32 that has an adhesive 34 on one surface is set down on the lower surface or backside of the conductive layer 14 which is part of the wire bondable tape 10.
  • a metal block 36 that has been preheated on a hot plate at a temperature in the range of Q 100-150°C approximately is brought into contact with the tape element 32 for about 1 to 1.5 minutes to cause the adhesive 34 to flow and adhere to the backside of the conductive element 14, while the tape 10 is maintained in alignment.
  • the fixture 30 is replaced by a fixture (not -.
  • a package frame or body frame 40 preferably made of a polymer material such as Ryton (trademark of Phillips Chemical Co) is joined to the cured unit by means of an epoxy adhesive 42, which may be a B-stage adhesive such as RT-4B (trademark of RJR Polymers).
  • Ryton trademark of Phillips Chemical Co
  • RT-4B trademark of RJR Polymers
  • the body frame 40 is placed into the alignment fixture 48 so that the adhesive 42 makes contact with the gold plate layer 14 and the tape element 32.
  • a slight force is applied to the top perimeter of the frame by means of a block 50, as shown in Fig. 6.
  • the pressure is applied to the frame for about 15-30 seconds.
  • the unit with the attached frame is then cured at about 150°C for approximately one hour.
  • an electr ⁇ .Yic grade epoxy material 52 such as Hysol CNB 405-12 (trademark, of Hysol) is used to encapsulate the device, while the temperature of the unit is maintained at about 50-70°C.
  • the epoxy is distributed by a dispensing needle, for example, in a circular motion, starting at the perimeter or, corners inside the body frame and moving to the center of the die area. The epoxy is made to flow evenly so .that a substan- tially flat surface results and air bubbles are elimi ⁇ nated. •
  • the epoxy effectively encapsulates the top of the body frame and the elements contained within the frame, as shown in Fig. 7.
  • the epoxy encapsulant is then cured by placing the unit in an oven for 2-4 hours at a temperature between 130°C to 150°C.
  • the novel semiconductor device package of this invention the relationship of the body frame 40 to the patterned Kapton layer 12 is shown.
  • Sprocket holes 56 are provided with the wire bondable tape 10 to aid in the automated processing of the tape.
  • conductive bumps 54 are employed in lieu of bond wires 26, to provide a conductive path from the die pad 20 to the conductive layer 14, as illustrated in Fig. 9.
  • the bumps which may be made of gold, copper or solder, are formed and joined by a tape automated bonding (TAB) process, which is well known in the art.
  • TAB tape automated bonding
  • the use of the bumps reduces the space required for the bond wires.
  • the assembly provides a more compact package and allows a relatively high lead count, because there is no physical space limitation by a molded enclosure as found in the prior art. '
  • the exploded view of the semiconductor device package of this invention shows the body frame 40, which has a vertical dimension, which may be approximately 60 milli-inches for example, and the epoxy encapsulant body 52 as they relate to the wire bondable tape.
  • the assembly does not include a molded package surrounding the semiconductor elements and does not incorporate a conductive patterned lead frame which is part of the electrically conductive path.
  • the body frame or package frame of this invention eliminates the need for molding a package around the semiconductor device and may be made of plastic or nonconductive material.
  • the body frame is used to contain the epoxy encapsulant body which provides the desired protection to the components of the semicon- ductor device.
  • the novel plastic package eliminates the need for a molded enclosure, is greatly reduced in height and overall area, and realizes improved electrical performance and reliability.
  • the insulating area which is Kapton for example, from the conductive layer, with a conductive film therebetween. Moisture penetration is effectively minimized. Also there is no problem of die surface corrosion.

Abstract

On produit un assemblage de dispositifs semi-conducteurs sans boîtier moulé en utilisant une bande ayant une couche structurée d'isolation (12) reliée à une couche conductrice (14). Un dé semi-conducteur (24) est placé sur la couche conductrice (14) et électriquement connecté à des sorties de la couche (14) conductrice structurée. On place un châssis (40) autour du dé (24), de même que des conducteurs et des connexions électriques, et on distribue un matériau d'enrobage (28) sur le cadre (40), à l'intérieur du cadre (40), sur le dé (24) et sur les conducteurs et connexions électriques.
EP19890900040 1987-10-30 1988-10-26 Method and means of fabricating a semiconductor device package Ceased EP0344259A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11522887A 1987-10-30 1987-10-30
US115228 1987-10-30

Publications (2)

Publication Number Publication Date
EP0344259A1 true EP0344259A1 (fr) 1989-12-06
EP0344259A4 EP0344259A4 (en) 1991-04-24

Family

ID=22360053

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19890900040 Ceased EP0344259A4 (en) 1987-10-30 1988-10-26 Method and means of fabricating a semiconductor device package

Country Status (4)

Country Link
EP (1) EP0344259A4 (fr)
JP (1) JP2664259B2 (fr)
KR (1) KR920008256B1 (fr)
WO (1) WO1989004552A1 (fr)

Cited By (5)

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WO1999020726A1 (fr) 1997-10-23 1999-04-29 The Procter & Gamble Company Compositions de blanchiment comprenant des variantes de protease multisubstituees
EP1997897A1 (fr) 1998-04-15 2008-12-03 Genencor International, Inc. Protéines mutantes disposant d'une réponse allergénique inférieure chez les humains et procédés de construction, d'identification et de production de telles protéines
EP2287320A1 (fr) 2002-01-16 2011-02-23 Genencor International, Inc. Variantes multiples de protéase substituée
EP2363460A2 (fr) 2004-12-30 2011-09-07 Genencor International, Inc. Protéases fongiques acides
EP2500423A2 (fr) 2003-02-26 2012-09-19 Genencor International, Inc. Amylases produisant une réponse immunogène altérée et leurs procédés de fabrication et d'utilisation

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4980753A (en) * 1988-11-21 1990-12-25 Honeywell Inc. Low-cost high-performance semiconductor chip package
FR2651923B1 (fr) * 1989-09-14 1994-06-17 Peugeot Circuit integre de puissance.
US5386342A (en) * 1992-01-30 1995-01-31 Lsi Logic Corporation Rigid backplane formed from a moisture resistant insulative material used to protect a semiconductor device
US5831836A (en) * 1992-01-30 1998-11-03 Lsi Logic Power plane for semiconductor device
JP3461204B2 (ja) * 1993-09-14 2003-10-27 株式会社東芝 マルチチップモジュール
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EP1997897A1 (fr) 1998-04-15 2008-12-03 Genencor International, Inc. Protéines mutantes disposant d'une réponse allergénique inférieure chez les humains et procédés de construction, d'identification et de production de telles protéines
EP2287320A1 (fr) 2002-01-16 2011-02-23 Genencor International, Inc. Variantes multiples de protéase substituée
EP2287321A1 (fr) 2002-01-16 2011-02-23 Genencor International, Inc. Variantes multiples de protéase substituée
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KR890702249A (ko) 1989-12-23
EP0344259A4 (en) 1991-04-24
KR920008256B1 (ko) 1992-09-25
JPH03503342A (ja) 1991-07-25
WO1989004552A1 (fr) 1989-05-18
JP2664259B2 (ja) 1997-10-15

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