WO1995010852A1 - Soudage de connexions directement sur zones actives de puces - Google Patents

Soudage de connexions directement sur zones actives de puces Download PDF

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Publication number
WO1995010852A1
WO1995010852A1 PCT/US1994/010398 US9410398W WO9510852A1 WO 1995010852 A1 WO1995010852 A1 WO 1995010852A1 US 9410398 W US9410398 W US 9410398W WO 9510852 A1 WO9510852 A1 WO 9510852A1
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WIPO (PCT)
Prior art keywords
die
lead frame
bonding pads
integrated circuit
bonding
Prior art date
Application number
PCT/US1994/010398
Other languages
English (en)
Inventor
Anthony E. Giraudo
Original Assignee
Atmel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corporation filed Critical Atmel Corporation
Publication of WO1995010852A1 publication Critical patent/WO1995010852A1/fr

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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Definitions

  • the present invention relates to assembling an integrated circuit package by mounting a completed integrated circuit die or chip onto a carrier or lead frame, and securing the mounted die and lead frame within a chip package or housing having external leads or contacts.
  • the invention relates in particular to the locations where leads are bonded to the integrated circuit die.
  • the completed integrated circuit chip or die is usually mounted on a substrate or carrier, which in turn is secured within a chip package.
  • the carrier is a flexible tape having a sequence of lead frames defined on the tape, one frame for each die to be mounted.
  • the lead frames have con ⁇ ductive paths that typically are arranged to interconnect inner and outer terminals or contact regions on the frames at which wire leads may be attached.
  • the tape may be an electrically insulative sheet material with metal ⁇ lic lines printed or otherwise formed on the insulative sheet to create the conductive paths. Paths may be pro- vided in more than one level and some paths may be com ⁇ pletely embedded or buried within the tape.
  • the tape may be a thin strip of copper with leads defined therein. Excess portions of this conductive frame material are cut or etched away after bonding to the chip is complete. Fine wires may be used to connect the inner contact regions or inner ends of the leads to bonding pads on the chip. Alternatively, the bonding pads of the chip could be connected directly to the leads or contact regions on the tape. Outer terminals of the lead frame are coupled to external contacts of a chip package.
  • transistors and other active circuit elements are gener ⁇ ally located in a central area of the chip, while bonding pads are generally located around the periphery of the active area, so that bonding of leads at the bonding pads are less likely to damage the active circuit elements, and thereby ruin the chip.
  • Heat and pressure resulting from the use of thermocompression bonding techniques expose any underlying circuit elements to the risk of possible damage.
  • Ultrasonic bonding and reflow soldering techniques can also damage underlying active circuit elements. Placing the point of bonding away from the active circuit area of the chip minimizes this risk.
  • bonding pads that are peripherally posi ⁇ tioned occupy a substantial percentage of the available substrate area so that the size of the chip is not as small as one would like. This is particularly true of small integrated circuits in which die are only about 1000 to 1500 ⁇ m square, where peripheral bonding pad areas may take up to 25% of the die's area. For high volume applications, such as telephone integrated circuit products, it is particularly important to reduce the die size to maximize productivity.
  • the structure includes a shock absorbing polyimide layer and a puncture-resistant silicon nitride or silicon oxynitride layer formed over the active region and a metal bonding pad formed over these protective layers and extending downward as a metal column through a via hole formed through the protective layers and any additional underlying passivation layers to make electrical contact with a circuit element on the surface of the substrate.
  • the metal bonding extends laterally over the protective layers, terminating at a location offset from the circuit element contact location. Thermocompression bonds can be made at the offset location instead of directly over the circuit element contact, thereby reducing the risk of circuit element damage.
  • An object of the invention is to reduce inte ⁇ grated circuit die size (area) while continuing to permit the bonding of the die to a lead frame for assembling into an integrated circuit package.
  • the object is met by placing the bonding pads directly over the active circuit areas of the die and by using a conductive adhesive material to adhere the die to a lead frame.
  • the bonding pads include pads that are formed at locations other than at the periphery of the integrated circuit die and thus achieve a reduction in the overall die area.
  • Pads are formed by placing an insulative layer over the active circuitry to provide electrical isolation, then forming via holes through this insulative layer to circuit elements of the integrated circuit die. Electrically conductive material is then disposed in the via holes to make contact with the selected circuit elements and also formed on top of the insulative layer to create a bond pad both directly over and in the immediate vicinity of the via holes.
  • the lead frame has contact regions at locations corresponding to the bonding pads on the die.
  • the conductive adhesive such as a z-axis epoxy, is applied to the lead frame, the die or both at least at locations corresponding to the bonding pads and contact regions.
  • the die is then mount ⁇ ed to the lead frame such that the corresponding bonding pads and contact regions precisely match and the adhesive is cured until the die firmly adheres to the lead frame.
  • the lead frame has means, such as a die-sized opening, associated with the lead frame for precisely positioning the die in the required matching corres ⁇ pondence with the lead frame's contact regions. Curing of the conductive adhesive may include heating of the mounted die and lead frame as well as the uniform appli- cation of some pressure.
  • Fig. 1 is a top plan view of an integrated circuit die of the prior art.
  • Fig. 2 is a top plan view of an integrated circuit die for assembling according to the present invention into an integrated circuit package.
  • Fig. 3 is a side sectional view of a portion of an integrated circuit die in accord with the present invention, centered about a bonding pad of the die, in combination with a corresponding portion of a lead frame to which the die is adhered.
  • Fig. 4 is a side view of a mounted die and lead frame assembly for an integrated circuit package of the present invention.
  • a prior integrated circuit die 11 is typically fabricated with an active circuit area 13 that is placed in the center region of the die 11 and metal bonding pads 15 that are placed in the periphery of the die 11 on one or more sides of the active circuit area 13.
  • the metal bonding pads 15 provide electrical access to the active circuit elements of the integrated circuit formed on the die 11 in the active circuit area 13.
  • the die is usually bonded on a chip carrier or "lead frame", and the die and lead frame are electrically connected by means of fine conductive wires that are thermocompressively bonded to the bonding pads 15 and to inner lead ends or contact regions on the lead frame.
  • the bonding pads constitute a significant portion of the overall die area.
  • Pad sizes for use with wire bonds are typically at least about 100 ⁇ m on a side. The minimum size of the bonding pads is constrained by the requirements for current conduction through the pads to the wire leads and by alignment tolerances for automated bonding.
  • an integrated circuit die 21 consistent with the present invention has an active circuit area 23 that now occupies the entire surface of the die 21.
  • this bonding pad arrangement achieves a 20 to 25% reduction in die area over the prior arrangement.
  • the bonding pads 25 may be as small as those in the prior peripheral arrange- ment, i.e., about 100 ⁇ m square, the space requirements of the active circuitry now controls the die size, so that the bonding pads 25 can be made larger to fill the available space (with at least a 15 ⁇ m spacing separating each pad) in order to improve current conduction and relax alignment tolerances.
  • the bonding pads 25 are formed as follows.
  • a semiconductor die substrate 27 has an integrated circuit formed therein by the usual techniques, including a plurality of active circuit elements, represented here by the contact area 31 for one such element.
  • Contact area 31 might, for example, be a metal interconnect line, a polysilicon gate or a doped source or drain region of the substrate 27.
  • the insu ⁇ lative material layer 29 is deposited over the surface of the substrate 27 including over the active circuit elements and their contact areas 31.
  • a via hole 33 is made through this insulative material layer 29, e.g., by etching, to selected contact areas 31 of selected circuit elements to allow electrical contact between the bonding pad 25 and the active circuitry below it.
  • the via hole 33 typically has a width or diameter of about 80 ⁇ m.
  • the metal bonding pads 25 are then formed by a metal deposi ⁇ tion followed by a selective etch.
  • the metal material typically gold or a gold alloy, fills the via holes 33 so as to make electrically conductive contact with the contact areas 31 of the selected circuit elements of the integrated circuit formed in the die substrate 27.
  • the metal bonding pad material is disposed over the insu ⁇ lative layer 29 immediately above the via holes 33 and in the immediate vicinity of the via holes 33.
  • the bonding pad material which is on top of the layer 29 has a thickness of about 1.5 to 3 ⁇ m.
  • such pads 25 are centered directly over the contact areas 31 below.
  • the integrated circuit die 21 is adhered to a lead frame 41.
  • the lead frame 41 has contact regions 43 for conductively coupling to corresponding bonding pads 25 on the die 21. While wire bonds might be used to connect the contact regions 43 to the bonding pads 25, if care is taken to avoid damaging the underlying circuit elements from application of too high a local pressure during thermocompression, the preferred method used in the present invention employs direct bonding of the die bonding pads 25 to the corresponding lead frame contact regions 43 with a conductive adhesive material 37.
  • the preferred material is a z-axis epoxy paste that can be applied either to the die or the lead frame and then cured.
  • Z-axis epoxy is a type of conductive adhesive characterized by unidirec ⁇ tional conductivity in the direction perpendicular to the opposed mating surfaces (the z-axis direction) . Uni ⁇ directional conductivity may be achieved by suspending conductive particles in a dielectric medium, where the suspended particles have a density that ensures that con ⁇ ductivity does not occur until the material is compressed between the opposed mating surfaces.
  • Such z-axis epoxy material is commercially available.
  • the lead frame 41 may be a standard metal strip 43, such as a strip of copper-nickel-gold alloy, that has had sections punched out or otherwise removed so that the remaining material forms conductive leads.
  • the metal strip 43 may have a dielectric backing or substrate 45 bonded thereto for support, which is made of a flexible insulative sheet material such as the plastic material sold commercially under the tradena e FR-4.
  • conductive paths may be patterned by deposition-and-etch or another technique directly on the dielectric substrate 45. In either case, the inner ends of these conductive paths or leads 43 form contact regions that are positioned to match the locations of corresponding bonding pads 25 of the die 21.
  • the lead frame 41 might also have an additional dielectric layer 47, again composed of FR-4 or another flexible insulative sheet material, which has a hole 49 punched out for the die 21 and which is disposed over the conductive leads 43.
  • This hole 49 acts as a self-aligning cavity for die placement so that when the die 21 fits within the hole 49 the contact regions 43 on the lead frame will precisely match the positions of the corresponding bonding pads 25 on the die 21.
  • the layer 47 preferably has a thickness that substantially matches the die thickness (about 60 ⁇ m) so that the mounted die—frame module will have a flat surface profile.
  • Z-axis epoxy paste 37 is applied within the hole 49 over the contact regions 43 and the die 21 is inserted into the hole, pad-side down.
  • the adhesive 37 is then cured.
  • curing is preferably done by applying heat to a temperature of between 125°C and 175°C and pressure up to about 275 kPa (40 psi) for a time period of up to about 50 seconds.
  • the pressure when applied, is uniformly distributed over the entire bonding surface to avoid local pressure gradients that might damage active circuit elements in the die 21. If necessary, lower temperatures and pressures can be applied over a longer curing period.
  • the cured z-axis epoxy has excellent unidirectional conductive properties, excellent adhesion and is very flexible for long life.
  • the conductive leads 43 extend outwardly from the contact areas for connection to a chip package.
  • chip packages are very well known and typically consist of a ceramic thermally conductive housing with external contacts or leads in a variety of possible configura ⁇ tions.
  • the lead frame 41 and die 21 module in Fig. 4 can easily be mounted in such a chip package using well known techniques, such that the leads 43 of the lead frame 41 electrically couple to the external contacts of the chip package.
  • via holes with metal plugs 51 may connect the outer ends of leads 43 to outer bonding pads 53 of the lead frame 41, where wire bonds between the lead frame 41 and the external contacts of the chip package can be made.
  • Other connection schemes may also be employed.
  • the present invention reduces the overall die size by using a conductive adhe ⁇ sive to adhere bonding pads of a die to a lead frame, thereby permitting placement of bonding pads directly over active circuit elements on the die.
  • the bonding pads are no longer restricted to peripheral regions surrounding the active circuit areas of the die, thus saving area. Mass production of such die will be more economical because of this size reduction.

Abstract

Des plages de connexion (25) sont formées directement sur les zones de circuit actives (23) d'une puce (21) et l'époxy à axe z (un adhésif conducteur) (37) est utilisé pour assurer l'adhésion de la puce sur une grille de connexion (41), de telle sorte que les zones de contact (43) situées aux extrémités internes de la grille de connexion (41), correspondent exactement aux plages de connexion correspondantes (25) situées sur la puce (21). La formation des plages (25) directement sur les éléments de circuit actifs (31) dans la puce plutôt que dans les régions périphériques (15) entourant la zone de circuit acitve (13), implique la réduction globale de la dimension de la puce. Le matériau adhésif conducteur (37) peut être traité par chauffage associé à l'application uniforme de pression sur le module monté puce-et-grille de connexion (21, 41). Le module peut alors être placé dans un boîtier de circuit intégré, les extrémités des conducteurs externes (53) de la grille de connexion étant électriquement couplées aux contacts externes du boîtier.
PCT/US1994/010398 1993-10-12 1994-09-15 Soudage de connexions directement sur zones actives de puces WO1995010852A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13508893A 1993-10-12 1993-10-12
US135,088 1993-10-12

Publications (1)

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WO1995010852A1 true WO1995010852A1 (fr) 1995-04-20

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997006557A1 (fr) * 1995-08-10 1997-02-20 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Procede de connexion de puces, sans bosse de contact, et circuit electrique obtenu a l'aide dudit procede
WO2011015732A1 (fr) * 2009-08-06 2011-02-10 Rfideal Connexion ohmique au moyen de zones de connexion elargies dans un objet electronique portatif

Families Citing this family (1)

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Publication number Priority date Publication date Assignee Title
CN112786540A (zh) 2019-11-06 2021-05-11 富泰华工业（深圳）有限公司 扇出型封装结构及其制作方法

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US5302849A (en) * 1993-03-01 1994-04-12 Motorola, Inc. Plastic and grid array semiconductor device and method for making the same
US5338970A (en) * 1993-03-24 1994-08-16 Intergraph Corporation Multi-layered integrated circuit package with improved high frequency performance
US5359222A (en) * 1992-01-31 1994-10-25 Kabushiki Kaisha Toshiba TCP type semiconductor device capable of preventing crosstalk
US5376825A (en) * 1990-10-22 1994-12-27 Seiko Epson Corporation Integrated circuit package for flexible computer system alternative architectures
US5384487A (en) * 1993-05-05 1995-01-24 Lsi Logic Corporation Off-axis power branches for interior bond pad arrangements

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Publication number Priority date Publication date Assignee Title
US5376825A (en) * 1990-10-22 1994-12-27 Seiko Epson Corporation Integrated circuit package for flexible computer system alternative architectures
US5359222A (en) * 1992-01-31 1994-10-25 Kabushiki Kaisha Toshiba TCP type semiconductor device capable of preventing crosstalk
US5302849A (en) * 1993-03-01 1994-04-12 Motorola, Inc. Plastic and grid array semiconductor device and method for making the same
US5338970A (en) * 1993-03-24 1994-08-16 Intergraph Corporation Multi-layered integrated circuit package with improved high frequency performance
US5384487A (en) * 1993-05-05 1995-01-24 Lsi Logic Corporation Off-axis power branches for interior bond pad arrangements

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997006557A1 (fr) * 1995-08-10 1997-02-20 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Procede de connexion de puces, sans bosse de contact, et circuit electrique obtenu a l'aide dudit procede
WO2011015732A1 (fr) * 2009-08-06 2011-02-10 Rfideal Connexion ohmique au moyen de zones de connexion elargies dans un objet electronique portatif
FR2949018A1 (fr) * 2009-08-06 2011-02-11 Rfideal Connexion ohmique au moyen de zones de connexion elargies dans un objet electronique portatif

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