EP0301260A1 - Modulationsdotierter Hochelektronengeschwindigkeitstransistor mit einer n-i-p-i-Struktur - Google Patents

Modulationsdotierter Hochelektronengeschwindigkeitstransistor mit einer n-i-p-i-Struktur Download PDF

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Publication number
EP0301260A1
EP0301260A1 EP88110412A EP88110412A EP0301260A1 EP 0301260 A1 EP0301260 A1 EP 0301260A1 EP 88110412 A EP88110412 A EP 88110412A EP 88110412 A EP88110412 A EP 88110412A EP 0301260 A1 EP0301260 A1 EP 0301260A1
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EP
European Patent Office
Prior art keywords
semiconductor layer
semiconductor
modulation
field effect
layers
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
EP88110412A
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English (en)
French (fr)
Inventor
Erhard Dr. Kohn
Karl R. Dr. Hofmann
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Siemens AG
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Siemens AG
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material

Definitions

  • the present invention relates to field effect transistors and more particularly to modulation-doped high electron mobility field effect transistors.
  • FET'S Field effect transistors (FET'S) using gallium arsenide (GaAS) are known to be capable of high speed operation.
  • Devices using gallium arsenide/aluminum gallium arsenide (GaAs/AlGaAs) heterostructures form a two-dimensional electron gas (2DEG).
  • 2DEG two-dimensional electron gas
  • the donor impurities are confined away from the active channel in which electrons may flow. This separation of donor impurities from the electron layers causes the device to exhibit extremely high electron mobilities and thereby to be capable of extremely fast operation, for example, in high speed switching.
  • a modulation-­doped field effect transistor comprises a first semiconductor layer being substantially undoped, an arrangement on one side of the first semiconductor layer for supplying charge carriers into a first region of the first semiconductor layer adjacent the one side of the semiconductor layer, and an arrangement for locally modulating hole and electron density in a second region of the first semiconductor layer adjacent another side thereof in a repeating pattern of alternations so as to substantially inhibit conduction therethrough in the direction of the alternations.
  • the modulation doped field effect transistor includes a gate arrangement for shifting the charge carriers between the first and second regions.
  • the arrangement for locally modulating doping comprises alternating p and n doped semiconductor regions adjacent the second region.
  • the arrangement for supplying charge carriers comprises a second semiconductor layer adjacent the first region.
  • the first semiconductor layer is gallium arsenide and the second semiconductor layer is aluminum gallium arsenide.
  • the first and second semiconductor layers are separated by a third semiconductor layer of aluminum gallium arsenide, the third semiconductor layer being thin compared with the first and second semiconductor layers.
  • the alternating p and n doped semiconductor regions are formed in respective layers of aluminum gallium arsenide.
  • a modulation-doped field effect transistor includes a first semiconductor layer being substantially undoped, a second semiconductor layer of a first conducting type, formed over the first semiconductor layer, and a gate electrode arrangement formed over the second semiconductor layer for controlling conduction through a conduction channel formed in the first semiconductor layer.
  • the transistor includes a third semiconductor layer of the first conductivity type and a fourth semiconductor layer of a second conductivity type formed next the third semiconductor layer, the third and fourth semiconductor layers having respective ends on one side thereof abutting the first semiconductor layer.
  • the third and fourth semiconductor layers form part of a plurality of semiconductor layers of Al Ga As in a sandwich structure of alternating p and n conductivity type semiconductor layers, the plurality of layers having respective ends on the one side abutting the first semiconductor layer and having respective ends on the other side abutting the fifth semiconductor layer.
  • a sixth semiconductor layer of substantially undoped AlGaAs is interposed between the first and second semiconductor layers, the sixth semiconductor layer being relatively thin compared with the first and second semiconductor layers.
  • a semiconductor layer of AlGaAs of substantially intrinsic conductivity is interposed between each one of the plurality of semiconductor layers and the next, such that a repeating pattern of conductivities is formed in the sandwich structure of n-conductivity, intrinsic-conductivity, p-conductivity, and intrinsic-conductivity semiconductor layers.
  • a modulation-doped field effect transistor comprises a first-semiconductor layer being substantially undoped, and a second semiconductor layer of a first conductivity type, formed over the first layer.
  • the transistor further includes a gate electrode formed over the second semiconductor layer for controlling conduction through a conduction channel formed in the first semiconductor layer, the conduction channel forming a main controllable-conduction path of the transistor, and a plurality of semiconductor layers of the first conductivity type and a second conductivity type, in a layered structure with the first and second conductivity types alternating.
  • the plurality of semiconductor layers has respective ends on one side thereof abutting the first semiconductor layer such that the plurality of semiconductor layers on the one hand and the first and second layers on the other hand are in substantially mutually perpendicular planes with the first and second conductivity types in the plurality of semiconductor layers alternating progressively along a length direction of the conduction channel, the layers in the plurality being of sufficient thickness to prevent substantially conduction through the plurality of semiconductor layers in a direction perpendicular to the planes of the plurality of semiconductor layers.
  • 100 is a substrate layer of gallium arsenide (GaAs).
  • Adjoining substrate layer 100 is a region generally designated in Fig. 1 as 102, comprising a composite of aluminum gallium arsenide (AlGaAs) layers lying in planes substantially perpendicular to the plane of substrate 100.
  • the layers are arranged in a sequence of n-doped, intrinsic (i), p-doped (p), intrinsic (i), n-doped, intrinsic materials, and so on, in the same repeating group sequence of n-i-p-i. While more than one such n-i-p-i group is utilized in the exemplary embodiment, the total number of such groups is not, in itself, a primary consideration.
  • the lateral thickness of the n-i-p-i layers is made sufficiently large to substantially prevent superlattice behavior.
  • Adjoining n-i-p-i region 102 in a plane generally parallel to the plane of substrate 100 is a layer 104 of substantially undoped GaAs. Accordingly, layer 100 and layer 104 include n-i-p-i region 102 therebetween, the planes of the n-i-p-i region being substantially perpendicular to the planes of layer 100 and layer 104.
  • Adjoining layer 104 is a layer 106 of substantially undoped AlGaAs, referred to herein as spacer 106. Spacer 106 is a relatively thin layer.
  • Adjoining spacer 106 is a layer 108 of n-doped AlGaAs which forms a gate dielectric for a gate 110 which is of a conductive material and is adjacent layer 108.
  • the layer arrangement comprises semi-insulating substrate 100, n-i-p-i region 102, undoped GaAs layer 104, undoped AlGaAs spacer 106, n-doped AlGaAs layer 108, and conductive gate 110.
  • layer 108 performs the function of an electron donor, contributing electrons which, having passed through spacer 106, form a two dimensional electron gas, commonly referred to in the literature as 2DEG, in at least that portion of undoped GaAs layer 104 which adjoins spacer 106 and which can be thought of as the active channel.
  • 2DEG two dimensional electron gas
  • spacer 106 provides a compromise since increasing the thickness leads to higher electron mobility but will also cause lower electron densities in the active channel. Spacer 106 may also be dispensed with altogether, as will be described later.
  • the present arrangement resembles known selectively doped hetero-junction transistors (SDHT), also referred to as high electron mobility transistors (HEMT) in which such separation is achieved by using the band-gap discontinuity in the conduction band of two epitaxially grown layers of different composition and doping (e.g. AlGaAs and GaAs).
  • SDHT selectively doped hetero-junction transistors
  • HEMT high electron mobility transistors
  • n-i-p-i region 102 With no bias applied between layer 104 and n-i-p-i region 102, the density of holes and electrons in layer 104 will be formed or modulation doped in a pattern corresponding to the n-i-p-i layers. Accordingly, current cannot flow in a horizontal direction at this interface, i.e. parallel to the interface. Thus, if n-i-p-i region 102 is allowed to float electrically, and a potential difference is applied in a horizontal direction, that is, in a direction along the plane of layer 104 substantially no current will flow in response to such an electric field applied between the ends of layer 104, for example by way of source and drain electrodes, not shown in FIG. 1.
  • the device in accordance with the present invention functions similarly to a conventional HEMT.
  • the electron wave is towards the lower interface, the heterojunction between layer 104 and n-i-p-i region 102, then the channel current depends on the condition at this lower interface where horizontal mobility is constrained, as has been described.
  • transfer of the electron wave from the top interface to the lower interface, achieved by a relatively high negative bias on gate 110 can also occur as a result of a relatively high positive bias on susbtrate 100, used thus as a back gate, in contrast to top gate 110.
  • the transistor structure of FIG. 2 has a vertical configuration and represents a convenient configuration for fabrication.
  • Adjacent a semi-insulating substrate 200 is an n-doped GaAs substrate 201 which is provided with drain contacts 212, 212′ and adjoins n-i-p-i region 202.
  • Undoped GaAs layers 204, 204′ adjoin n-i-p-i region 202 on respective sides thereof to provide active channel areas.
  • N-doped layers 208, 208′ adjoin layers 204, 204′, respectively and support respective gate electrodes 210, 210′.
  • a source region 214 surmounts n-i-p-i region 202 in a plane parallel to the plane of the n-i-p-i layers and has an electrode 216 coupled thereto.
  • the transistor in accordance with the present invention has at least two principal fields of application.
  • One field is as a high speed logic switch element, e.g. as an inverter.
  • Another application is as a microwave oscillator, using differential negative resistance controllable by gate bias.
  • n-i-p-i region 102 or 202 are not essential, since appropriate modulation doping can also be produced by an n-p-n-p-n-etc. sequence.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
EP88110412A 1987-07-06 1988-06-29 Modulationsdotierter Hochelektronengeschwindigkeitstransistor mit einer n-i-p-i-Struktur Withdrawn EP0301260A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/069,685 US4855797A (en) 1987-07-06 1987-07-06 Modulation doped high electron mobility transistor with n-i-p-i structure
US69685 1987-07-06

Publications (1)

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EP0301260A1 true EP0301260A1 (de) 1989-02-01

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EP88110412A Withdrawn EP0301260A1 (de) 1987-07-06 1988-06-29 Modulationsdotierter Hochelektronengeschwindigkeitstransistor mit einer n-i-p-i-Struktur

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US (1) US4855797A (de)
EP (1) EP0301260A1 (de)
JP (1) JPS6424467A (de)

Families Citing this family (7)

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Publication number Priority date Publication date Assignee Title
US5225895A (en) * 1989-12-20 1993-07-06 Sanyo Electric Co., Ltd. Velocity-modulation transistor with quantum well wire layer
JP2582946B2 (ja) * 1991-03-26 1997-02-19 積水化学工業株式会社 粒状体入り人工芝
JP3086748B2 (ja) * 1991-07-26 2000-09-11 株式会社東芝 高電子移動度トランジスタ
US5408111A (en) * 1993-02-26 1995-04-18 Sumitomo Electric Industries, Ltd. Field-effect transistor having a double pulse-doped structure
US5408107A (en) * 1993-05-20 1995-04-18 The Board Of Regents Of The University Of Texas System Semiconductor device apparatus having multiple current-voltage curves and zero-bias memory
JP2003142492A (ja) * 2001-10-30 2003-05-16 Sumitomo Chem Co Ltd ３−５族化合物半導体および半導体装置
JP5506258B2 (ja) * 2008-08-06 2014-05-28 キヤノン株式会社 整流素子

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EP0091831A2 (de) * 1982-04-14 1983-10-19 Hiroyuki Sakaki Feldeffekttransistor mit modulierter Beweglichkeit
GB2171250A (en) * 1985-01-30 1986-08-20 Sony Corp Heterojunction field effect transistors

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JPS6424467A (en) 1989-01-26
US4855797A (en) 1989-08-08

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