EP0301260A1 - Modulation doped high electron mobility transistor with n-i-p-i structure - Google Patents

Modulation doped high electron mobility transistor with n-i-p-i structure Download PDF

Info

Publication number
EP0301260A1
EP0301260A1 EP88110412A EP88110412A EP0301260A1 EP 0301260 A1 EP0301260 A1 EP 0301260A1 EP 88110412 A EP88110412 A EP 88110412A EP 88110412 A EP88110412 A EP 88110412A EP 0301260 A1 EP0301260 A1 EP 0301260A1
Authority
EP
European Patent Office
Prior art keywords
semiconductor layer
semiconductor
modulation
field effect
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP88110412A
Other languages
German (de)
French (fr)
Inventor
Erhard Dr. Kohn
Karl R. Dr. Hofmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0301260A1 publication Critical patent/EP0301260A1/en
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material

Definitions

  • the present invention relates to field effect transistors and more particularly to modulation-doped high electron mobility field effect transistors.
  • FET'S Field effect transistors (FET'S) using gallium arsenide (GaAS) are known to be capable of high speed operation.
  • Devices using gallium arsenide/aluminum gallium arsenide (GaAs/AlGaAs) heterostructures form a two-dimensional electron gas (2DEG).
  • 2DEG two-dimensional electron gas
  • the donor impurities are confined away from the active channel in which electrons may flow. This separation of donor impurities from the electron layers causes the device to exhibit extremely high electron mobilities and thereby to be capable of extremely fast operation, for example, in high speed switching.
  • a modulation-­doped field effect transistor comprises a first semiconductor layer being substantially undoped, an arrangement on one side of the first semiconductor layer for supplying charge carriers into a first region of the first semiconductor layer adjacent the one side of the semiconductor layer, and an arrangement for locally modulating hole and electron density in a second region of the first semiconductor layer adjacent another side thereof in a repeating pattern of alternations so as to substantially inhibit conduction therethrough in the direction of the alternations.
  • the modulation doped field effect transistor includes a gate arrangement for shifting the charge carriers between the first and second regions.
  • the arrangement for locally modulating doping comprises alternating p and n doped semiconductor regions adjacent the second region.
  • the arrangement for supplying charge carriers comprises a second semiconductor layer adjacent the first region.
  • the first semiconductor layer is gallium arsenide and the second semiconductor layer is aluminum gallium arsenide.
  • the first and second semiconductor layers are separated by a third semiconductor layer of aluminum gallium arsenide, the third semiconductor layer being thin compared with the first and second semiconductor layers.
  • the alternating p and n doped semiconductor regions are formed in respective layers of aluminum gallium arsenide.
  • a modulation-doped field effect transistor includes a first semiconductor layer being substantially undoped, a second semiconductor layer of a first conducting type, formed over the first semiconductor layer, and a gate electrode arrangement formed over the second semiconductor layer for controlling conduction through a conduction channel formed in the first semiconductor layer.
  • the transistor includes a third semiconductor layer of the first conductivity type and a fourth semiconductor layer of a second conductivity type formed next the third semiconductor layer, the third and fourth semiconductor layers having respective ends on one side thereof abutting the first semiconductor layer.
  • the third and fourth semiconductor layers form part of a plurality of semiconductor layers of Al Ga As in a sandwich structure of alternating p and n conductivity type semiconductor layers, the plurality of layers having respective ends on the one side abutting the first semiconductor layer and having respective ends on the other side abutting the fifth semiconductor layer.
  • a sixth semiconductor layer of substantially undoped AlGaAs is interposed between the first and second semiconductor layers, the sixth semiconductor layer being relatively thin compared with the first and second semiconductor layers.
  • a semiconductor layer of AlGaAs of substantially intrinsic conductivity is interposed between each one of the plurality of semiconductor layers and the next, such that a repeating pattern of conductivities is formed in the sandwich structure of n-conductivity, intrinsic-conductivity, p-conductivity, and intrinsic-conductivity semiconductor layers.
  • a modulation-doped field effect transistor comprises a first-semiconductor layer being substantially undoped, and a second semiconductor layer of a first conductivity type, formed over the first layer.
  • the transistor further includes a gate electrode formed over the second semiconductor layer for controlling conduction through a conduction channel formed in the first semiconductor layer, the conduction channel forming a main controllable-conduction path of the transistor, and a plurality of semiconductor layers of the first conductivity type and a second conductivity type, in a layered structure with the first and second conductivity types alternating.
  • the plurality of semiconductor layers has respective ends on one side thereof abutting the first semiconductor layer such that the plurality of semiconductor layers on the one hand and the first and second layers on the other hand are in substantially mutually perpendicular planes with the first and second conductivity types in the plurality of semiconductor layers alternating progressively along a length direction of the conduction channel, the layers in the plurality being of sufficient thickness to prevent substantially conduction through the plurality of semiconductor layers in a direction perpendicular to the planes of the plurality of semiconductor layers.
  • 100 is a substrate layer of gallium arsenide (GaAs).
  • Adjoining substrate layer 100 is a region generally designated in Fig. 1 as 102, comprising a composite of aluminum gallium arsenide (AlGaAs) layers lying in planes substantially perpendicular to the plane of substrate 100.
  • the layers are arranged in a sequence of n-doped, intrinsic (i), p-doped (p), intrinsic (i), n-doped, intrinsic materials, and so on, in the same repeating group sequence of n-i-p-i. While more than one such n-i-p-i group is utilized in the exemplary embodiment, the total number of such groups is not, in itself, a primary consideration.
  • the lateral thickness of the n-i-p-i layers is made sufficiently large to substantially prevent superlattice behavior.
  • Adjoining n-i-p-i region 102 in a plane generally parallel to the plane of substrate 100 is a layer 104 of substantially undoped GaAs. Accordingly, layer 100 and layer 104 include n-i-p-i region 102 therebetween, the planes of the n-i-p-i region being substantially perpendicular to the planes of layer 100 and layer 104.
  • Adjoining layer 104 is a layer 106 of substantially undoped AlGaAs, referred to herein as spacer 106. Spacer 106 is a relatively thin layer.
  • Adjoining spacer 106 is a layer 108 of n-doped AlGaAs which forms a gate dielectric for a gate 110 which is of a conductive material and is adjacent layer 108.
  • the layer arrangement comprises semi-insulating substrate 100, n-i-p-i region 102, undoped GaAs layer 104, undoped AlGaAs spacer 106, n-doped AlGaAs layer 108, and conductive gate 110.
  • layer 108 performs the function of an electron donor, contributing electrons which, having passed through spacer 106, form a two dimensional electron gas, commonly referred to in the literature as 2DEG, in at least that portion of undoped GaAs layer 104 which adjoins spacer 106 and which can be thought of as the active channel.
  • 2DEG two dimensional electron gas
  • spacer 106 provides a compromise since increasing the thickness leads to higher electron mobility but will also cause lower electron densities in the active channel. Spacer 106 may also be dispensed with altogether, as will be described later.
  • the present arrangement resembles known selectively doped hetero-junction transistors (SDHT), also referred to as high electron mobility transistors (HEMT) in which such separation is achieved by using the band-gap discontinuity in the conduction band of two epitaxially grown layers of different composition and doping (e.g. AlGaAs and GaAs).
  • SDHT selectively doped hetero-junction transistors
  • HEMT high electron mobility transistors
  • n-i-p-i region 102 With no bias applied between layer 104 and n-i-p-i region 102, the density of holes and electrons in layer 104 will be formed or modulation doped in a pattern corresponding to the n-i-p-i layers. Accordingly, current cannot flow in a horizontal direction at this interface, i.e. parallel to the interface. Thus, if n-i-p-i region 102 is allowed to float electrically, and a potential difference is applied in a horizontal direction, that is, in a direction along the plane of layer 104 substantially no current will flow in response to such an electric field applied between the ends of layer 104, for example by way of source and drain electrodes, not shown in FIG. 1.
  • the device in accordance with the present invention functions similarly to a conventional HEMT.
  • the electron wave is towards the lower interface, the heterojunction between layer 104 and n-i-p-i region 102, then the channel current depends on the condition at this lower interface where horizontal mobility is constrained, as has been described.
  • transfer of the electron wave from the top interface to the lower interface, achieved by a relatively high negative bias on gate 110 can also occur as a result of a relatively high positive bias on susbtrate 100, used thus as a back gate, in contrast to top gate 110.
  • the transistor structure of FIG. 2 has a vertical configuration and represents a convenient configuration for fabrication.
  • Adjacent a semi-insulating substrate 200 is an n-doped GaAs substrate 201 which is provided with drain contacts 212, 212′ and adjoins n-i-p-i region 202.
  • Undoped GaAs layers 204, 204′ adjoin n-i-p-i region 202 on respective sides thereof to provide active channel areas.
  • N-doped layers 208, 208′ adjoin layers 204, 204′, respectively and support respective gate electrodes 210, 210′.
  • a source region 214 surmounts n-i-p-i region 202 in a plane parallel to the plane of the n-i-p-i layers and has an electrode 216 coupled thereto.
  • the transistor in accordance with the present invention has at least two principal fields of application.
  • One field is as a high speed logic switch element, e.g. as an inverter.
  • Another application is as a microwave oscillator, using differential negative resistance controllable by gate bias.
  • n-i-p-i region 102 or 202 are not essential, since appropriate modulation doping can also be produced by an n-p-n-p-n-etc. sequence.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

A modulation-doped field effect transistor includes an undoped semiconductor layer (104) and an arrangement (106, 108) for supplying charge carriers into a region of the semiconductor layer (104) adjacent one side. An arrangement (102) is provided for locally modulating the charge carrier density in another region adjacent the other side of the semiconductor layer (104) in a repeating pattern of alternations so as to inhibit current flow in the direction of the alternations.

Description

  • The present invention relates to field effect transistors and more particularly to modulation-doped high electron mobility field effect transistors.
  • Field effect transistors (FET'S) using gallium arsenide (GaAS) are known to be capable of high speed operation. Devices using gallium arsenide/aluminum gallium arsenide (GaAs/AlGaAs) heterostructures form a two-dimensional electron gas (2DEG). In such devices the donor impurities are confined away from the active channel in which electrons may flow. This separation of donor impurities from the electron layers causes the device to exhibit extremely high electron mobilities and thereby to be capable of extremely fast operation, for example, in high speed switching.
  • Nevertheless, since the electrons in the device must still transit the channel length, an ultimate switching speed depending on the channel length will exist, so long as the conductivity modulation of the device is achieved by varying the carrier density in the channel.
  • In accordance with a first aspect of the invention, a modulation-­doped field effect transistor comprises a first semiconductor layer being substantially undoped, an arrangement on one side of the first semiconductor layer for supplying charge carriers into a first region of the first semiconductor layer adjacent the one side of the semiconductor layer, and an arrangement for locally modulating hole and electron density in a second region of the first semiconductor layer adjacent another side thereof in a repeating pattern of alternations so as to substantially inhibit conduction therethrough in the direction of the alternations.
  • In accordance with a second aspect of the invention, the modulation doped field effect transistor includes a gate arrangement for shifting the charge carriers between the first and second regions.
  • In accordance with a third aspect of the invention, the arrangement for locally modulating doping comprises alternating p and n doped semiconductor regions adjacent the second region.
  • In accordance with a fourth aspect of the invention, the arrangement for supplying charge carriers comprises a second semiconductor layer adjacent the first region.
  • In accordance with a fifth aspect of the invention, the first semiconductor layer is gallium arsenide and the second semiconductor layer is aluminum gallium arsenide.
  • In accordance with a sixth aspect of the invention, the first and second semiconductor layers are separated by a third semiconductor layer of aluminum gallium arsenide, the third semiconductor layer being thin compared with the first and second semiconductor layers.
  • In accordance with a seventh aspect of the invention, the alternating p and n doped semiconductor regions are formed in respective layers of aluminum gallium arsenide.
  • In accordance with an eighth aspect of the invention, a modulation-doped field effect transistor includes a first semiconductor layer being substantially undoped, a second semiconductor layer of a first conducting type, formed over the first semiconductor layer, and a gate electrode arrangement formed over the second semiconductor layer for controlling conduction through a conduction channel formed in the first semiconductor layer. The transistor includes a third semiconductor layer of the first conductivity type and a fourth semiconductor layer of a second conductivity type formed next the third semiconductor layer, the third and fourth semiconductor layers having respective ends on one side thereof abutting the first semiconductor layer.
  • In accordance with an ninth aspect of the invention, the third and fourth semiconductor layers form part of a plurality of semiconductor layers of Al Ga As in a sandwich structure of alternating p and n conductivity type semiconductor layers, the plurality of layers having respective ends on the one side abutting the first semiconductor layer and having respective ends on the other side abutting the fifth semiconductor layer.
  • In accordance with a tenth aspect of the invention, a sixth semiconductor layer of substantially undoped AlGaAs is interposed between the first and second semiconductor layers, the sixth semiconductor layer being relatively thin compared with the first and second semiconductor layers.
  • In accordance with an eleventh aspect of the invention, a semiconductor layer of AlGaAs of substantially intrinsic conductivity is interposed between each one of the plurality of semiconductor layers and the next, such that a repeating pattern of conductivities is formed in the sandwich structure of n-conductivity, intrinsic-conductivity, p-conductivity, and intrinsic-conductivity semiconductor layers.
  • In accordance with a further aspect of the invention, a modulation-doped field effect transistor comprises a first-semiconductor layer being substantially undoped, and a second semiconductor layer of a first conductivity type, formed over the first layer. The transistor further includes a gate electrode formed over the second semiconductor layer for controlling conduction through a conduction channel formed in the first semiconductor layer, the conduction channel forming a main controllable-conduction path of the transistor, and a plurality of semiconductor layers of the first conductivity type and a second conductivity type, in a layered structure with the first and second conductivity types alternating. The plurality of semiconductor layers has respective ends on one side thereof abutting the first semiconductor layer such that the plurality of semiconductor layers on the one hand and the first and second layers on the other hand are in substantially mutually perpendicular planes with the first and second conductivity types in the plurality of semiconductor layers alternating progressively along a length direction of the conduction channel, the layers in the plurality being of sufficient thickness to prevent substantially conduction through the plurality of semiconductor layers in a direction perpendicular to the planes of the plurality of semiconductor layers.
  • The invention will next be described in greater detail, with reference to the drawing, in which:
    • FIG. 1 shows a cross-sectional view, not to scale, of a four-terminal modulation doped field effect transistor structure in accordance with the invention; and
    • FIG. 2 shows a cross-sectional view, not to scale, of a vertical field effect transistor structure in accordance with the invention. Features in FIG. 2 corresponding to features in FIG. 1 are designated by the same reference numeral augumented by 100.
  • In the transistor structure of FIG. 1, 100 is a substrate layer of gallium arsenide (GaAs). Adjoining substrate layer 100 is a region generally designated in Fig. 1 as 102, comprising a composite of aluminum gallium arsenide (AlGaAs) layers lying in planes substantially perpendicular to the plane of substrate 100. The layers are arranged in a sequence of n-doped, intrinsic (i), p-doped (p), intrinsic (i), n-doped, intrinsic materials, and so on, in the same repeating group sequence of n-i-p-i. While more than one such n-i-p-i group is utilized in the exemplary embodiment, the total number of such groups is not, in itself, a primary consideration. The lateral thickness of the n-i-p-i layers is made sufficiently large to substantially prevent superlattice behavior.
  • Adjoining n-i-p-i region 102 in a plane generally parallel to the plane of substrate 100 is a layer 104 of substantially undoped GaAs. Accordingly, layer 100 and layer 104 include n-i-p-i region 102 therebetween, the planes of the n-i-p-i region being substantially perpendicular to the planes of layer 100 and layer 104. Adjoining layer 104 is a layer 106 of substantially undoped AlGaAs, referred to herein as spacer 106. Spacer 106 is a relatively thin layer. Adjoining spacer 106 is a layer 108 of n-doped AlGaAs which forms a gate dielectric for a gate 110 which is of a conductive material and is adjacent layer 108.
  • To summarize, the layer arrangement comprises semi-insulating substrate 100, n-i-p-i region 102, undoped GaAs layer 104, undoped AlGaAs spacer 106, n-doped AlGaAs layer 108, and conductive gate 110.
  • In operation, layer 108 performs the function of an electron donor, contributing electrons which, having passed through spacer 106, form a two dimensional electron gas, commonly referred to in the literature as 2DEG, in at least that portion of undoped GaAs layer 104 which adjoins spacer 106 and which can be thought of as the active channel.
  • The thickness of spacer 106 provides a compromise since increasing the thickness leads to higher electron mobility but will also cause lower electron densities in the active channel. Spacer 106 may also be dispensed with altogether, as will be described later.
  • To the extent of separating mobile carriers from the supplying dopant atoms, the present arrangement resembles known selectively doped hetero-junction transistors (SDHT), also referred to as high electron mobility transistors (HEMT) in which such separation is achieved by using the band-gap discontinuity in the conduction band of two epitaxially grown layers of different composition and doping (e.g. AlGaAs and GaAs).
  • With no bias applied between layer 104 and n-i-p-i region 102, the density of holes and electrons in layer 104 will be formed or modulation doped in a pattern corresponding to the n-i-p-i layers. Accordingly, current cannot flow in a horizontal direction at this interface, i.e. parallel to the interface. Thus, if n-i-p-i region 102 is allowed to float electrically, and a potential difference is applied in a horizontal direction, that is, in a direction along the plane of layer 104 substantially no current will flow in response to such an electric field applied between the ends of layer 104, for example by way of source and drain electrodes, not shown in FIG. 1.
  • On the other hand, when a positive bias voltage is applied to gate electrode 110, electron current responsive to a horizontally applied potential difference can flow horizontally in the upper portion of layer 104, that is, the portion distal from n-i-p-i region 102. The transition from non-conduction to conduction in layer 104 and vice versa occurs as a result of the 2DEG in layer 104 being switched from near the bottom interface to the top interface and vice versa. Since the thickness dimension of layer 104 is extremely small in comparison with the lateral dimensions, such switching is very fast in comparison with the classical FET action and does not suffer from the effects of transit time delay. No gate current or substrate current will flow, other than capacitive displacement current. The device described therefore functions as a very fast switch, a small vertical shift of the electron current between the upper and lower interfaces being sufficient to effect switching.
  • Thus, so long as the electrons are confined to the vicinity of the top horizontal interface between layer 104 and spacer 106, the device in accordance with the present invention functions similarly to a conventional HEMT. On the other hand, when the electron wave is towards the lower interface, the heterojunction between layer 104 and n-i-p-i region 102, then the channel current depends on the condition at this lower interface where horizontal mobility is constrained, as has been described. Moreover, transfer of the electron wave from the top interface to the lower interface, achieved by a relatively high negative bias on gate 110 can also occur as a result of a relatively high positive bias on susbtrate 100, used thus as a back gate, in contrast to top gate 110. Also, such a transfer will result from a high positive potential being applied to one end of layer 104, corresponding to a high positive applied drain voltage. Thus, as the applied drain voltage is first increased from a low value, the horizontal or drain current through layer 104 will at first increase in the aforementioned normal FET manner. Thereafter, as the electron wave is shifted toward the lower interface responsive to a higher drain voltage, the drain current will decrease, corresponding to a negative incremental or differential resistance. Such a characteristic is useful in high frequency oscillators and in logic switching. In the device in accordance with the present invention, the negative resistance is moreover controllable by changing the gate potential.
  • The transistor structure of FIG. 2 has a vertical configuration and represents a convenient configuration for fabrication. Adjacent a semi-insulating substrate 200 is an n-doped GaAs substrate 201 which is provided with drain contacts 212, 212′ and adjoins n-i-p-i region 202. Undoped GaAs layers 204, 204′ adjoin n-i-p-i region 202 on respective sides thereof to provide active channel areas. N-doped layers 208, 208′ adjoin layers 204, 204′, respectively and support respective gate electrodes 210, 210′. A source region 214 surmounts n-i-p-i region 202 in a plane parallel to the plane of the n-i-p-i layers and has an electrode 216 coupled thereto.
  • The transistor in accordance with the present invention has at least two principal fields of application. One field is as a high speed logic switch element, e.g. as an inverter. Another application is as a microwave oscillator, using differential negative resistance controllable by gate bias.
  • While the invention has been described in terms of preferred embodiments, various changes which do not depart from the scope of the claims following will suggest themselves to one skilled in the art. For example, the intrinsic layers in n-i-p-i region 102 or 202 are not essential, since appropriate modulation doping can also be produced by an n-p-n-p-n-etc. sequence.

Claims (20)

1. A modulation-doped field effect transistor including a first semiconductor layer being substantially undoped, a second semiconductor layer of a first conducting type, formed over said first semiconductor layer, and gate electrode means formed over said second semiconductor layer for controlling conduction through a conduction channel formed in said first semiconductor layer, comprising:
      a third semiconductor layer of said first conductivity type; and
      a fourth semiconductor layer of a second conductivity type formed next said third semiconductor layer, said third and fourth semiconductor layers having respective ends on one side thereof abutting said first semiconductor layer.
2. A modulation-doped field effect transistor according to Claim 1 wherein said first semiconductor layer is gallium arsenide (GaAs), and said second, third, and fourth layers are aluminum gallium arsenide (AlGaAs).
3. A modulation-doped field effect transistor according to Claim 2 wherein said first conductivity type is n and said second conductivity type is p.
4. A modulation-doped field effect transistor according to Claim 3 including a fifth layer of a semi-insulating semiconductor, said third and fourth semiconductor layers having respective ends on the other side thereof abutting said fifth semiconductor layer.
5. A modulation-doped field effect transistor according to Claim 4 wherein said third and fourth semiconductor layers form part of a plurality of semiconductor layers of AlGaAs in a sandwich structure of alternating p and n conductivity type semiconductor layers, said plurality of layers having respective ends on said one side abutting said first semiconductor layer and having respective ends on said other side abutting said fifth semiconductor layer.
6. A modulation-doped field effect transistor according to Claim 5 wherein a sixth semiconductor layer of substantially undoped AlGaAs is interposed between said first and second semiconductor layers, said sixth semiconductor layer being relatively thin compared with said first and second semiconductor layers.
7. A modulation-doped field effect transistor according to Claim 5, wherein a semiconductor layer of AlGaAs of substantially intrinsic conductivity is interposed between each one of said plurality of semiconductor layers and the next, such that a repeating pattern of conductivities is formed in said sandwich structure of n-conductivity, intrinisc-conductivity, p-conductivity, and intrinsic-conductivity semiconductor layers.
8. A modulation-doped field effect transistor according to Claim 6 wherein a semiconductor layer of AlGaAs of substantially intrinsic conductivity is interposed between each one of said plurality of semiconductor layers and the next, such that a repeating pattern of conductivities is formed in said sandwich structure of n-conductivity, intrinisc-conductivity, p-conductivity, and intrinsic-conductivity semiconductor layers.
9. A modulation-doped field effect transistor comprising:
      a first-semiconductor layer being substantially undoped;
      a second semiconductor layer of a first conductivity type, formed over said first layer;
      gate electrode means formed over said second semiconductor layer for controlling conduction through a conduction channel formed in said first semiconductor layer, said conduction channel forming a main controllable conduction path of said transistor; and
      a plurality of semiconductor layers of said first conductivity type and a second conductivity type, in a layered structure with said first and second conductivity types alternating, said plurality of semiconductor layers having respective ends on one side thereof abutting said first semiconductor layer such that said plurality of semiconductor layers on the one hand and said first and second layers on the other hand are in substantially mutually perpendicular planes with said first and second conductivity types in said plurality of semiconductor layers alternating progressively along a length direction of said conduction channel, said layers in said plurality being of sufficient thickness to prevent substantially conduction through said plurality of semiconductor layers in a direction perpendicular to the planes of said plurality of semiconductor layers.
10. A modulation-doped field effect transistor according to Claim 9 including a third semiconductor layer, being substantially undoped and being interposed between said first and second layers.
11. A modulation-doped field effect transistor according to Claim 10 including a fourth semiconductor layer of semi-insulating conductivity, said plurality of semiconductor layers having respective ends thereof, on a side thereof opposite said one side thereof, abutting said fourth semiconductor layer.
12. A modulation-doped field effect transistor according to Claim 10 wherein said first semiconductor layer is gallium arsenide, said second, third, and fourth semiconductor layers are aluminum gallium arsenide.
13. A modulation-doped field effect transistor according to Claim 10 wherein said third semiconductor layer is thin compared with said first and second semiconductor layers.
14. A modulation-doped field effect transistor comprising:
      a first semiconductor layer being substantially undoped;
      means on one side of said first semiconductor layer for supplying charge carriers into a first region of said first semiconductor layer adjacent said one side of said semiconductor layer; and
      means for locally modulating doping of holes and electrons in a second region of said first semiconductor layer adjacent another side thereof in a repeating pattern of alternations so as to substantially inhibit conduction therethrough in the direction of said alternations.
15. A modulation-doped field effect transistor according to Claim 14 including gate means for shifting said charge carriers between said first and second regions.
16. A modulation-doped field effect transistor according to Claim 15 wherein said means for locally modulating doping comprises alternating p and n doped semiconductor regions adjacent said second region.
17. A modulation-doped field effect transistor according to Claim 15 wherein said means for supplying charge carriers comprises a second semiconductor layer adjacent said first region.
18. A modulation-doped field effect transistor according to Claim 15 wherein said first semiconductor layer is gallium arsenide and said second semiconductor layer is aluminum gallium arsenide.
19. A modulation-doped field effect transistor according to Claim 18 wherein said first and second semiconductor layers are separated by a third semiconductor layer of aluminum gallium arsenide, said third semiconductor layer being thin compared with said first and second semiconductor layers.
20. A modulation-doped field effect transistor according to Claim 16 wherein said alternating p and n doped semiconductor regions are formed in respective layers of aluminum gallium arsenide.
EP88110412A 1987-07-06 1988-06-29 Modulation doped high electron mobility transistor with n-i-p-i structure Withdrawn EP0301260A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US69685 1987-07-06
US07/069,685 US4855797A (en) 1987-07-06 1987-07-06 Modulation doped high electron mobility transistor with n-i-p-i structure

Publications (1)

Publication Number Publication Date
EP0301260A1 true EP0301260A1 (en) 1989-02-01

Family

ID=22090582

Family Applications (1)

Application Number Title Priority Date Filing Date
EP88110412A Withdrawn EP0301260A1 (en) 1987-07-06 1988-06-29 Modulation doped high electron mobility transistor with n-i-p-i structure

Country Status (3)

Country Link
US (1) US4855797A (en)
EP (1) EP0301260A1 (en)
JP (1) JPS6424467A (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5225895A (en) * 1989-12-20 1993-07-06 Sanyo Electric Co., Ltd. Velocity-modulation transistor with quantum well wire layer
JP2582946B2 (en) * 1991-03-26 1997-02-19 積水化学工業株式会社 Artificial turf with granular material
JP3086748B2 (en) * 1991-07-26 2000-09-11 株式会社東芝 High electron mobility transistor
US5408111A (en) * 1993-02-26 1995-04-18 Sumitomo Electric Industries, Ltd. Field-effect transistor having a double pulse-doped structure
US5408107A (en) * 1993-05-20 1995-04-18 The Board Of Regents Of The University Of Texas System Semiconductor device apparatus having multiple current-voltage curves and zero-bias memory
JP2003142492A (en) * 2001-10-30 2003-05-16 Sumitomo Chem Co Ltd 3-5 compound semiconductor and semiconductor device
JP5506258B2 (en) * 2008-08-06 2014-05-28 キヤノン株式会社 Rectifier element

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0056904A2 (en) * 1980-12-29 1982-08-04 Fujitsu Limited High electron mobility single heterojunction semiconductor devices and methods of production of such devices
EP0091831A2 (en) * 1982-04-14 1983-10-19 Hiroyuki Sakaki Mobility-modulation field effect transistor
GB2171250A (en) * 1985-01-30 1986-08-20 Sony Corp Heterojunction field effect transistors

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3626328A (en) * 1969-04-01 1971-12-07 Ibm Semiconductor bulk oscillator
DE2261527C2 (en) * 1972-12-15 1983-04-21 Max-Planck-Gesellschaft zur Förderung der Wissenschaften e.V., 3400 Göttingen Semiconductor body with alternately successive n- and p-doped zones in a predetermined direction, method for its production and uses of the semiconductor body
US4205329A (en) * 1976-03-29 1980-05-27 Bell Telephone Laboratories, Incorporated Periodic monolayer semiconductor structures grown by molecular beam epitaxy
US4250515A (en) * 1978-06-09 1981-02-10 The United States Of America As Represented By The Secretary Of The Army Heterojunction superlattice with potential well depth greater than half the bandgap
US4257055A (en) * 1979-07-26 1981-03-17 University Of Illinois Foundation Negative resistance heterojunction devices
US4261771A (en) * 1979-10-31 1981-04-14 Bell Telephone Laboratories, Incorporated Method of fabricating periodic monolayer semiconductor structures by molecular beam epitaxy
IT1149814B (en) * 1979-11-26 1986-12-10 Ibm SEMICONDUCTIVE STRUCTURE
JPS5776879A (en) * 1980-10-31 1982-05-14 Hitachi Ltd Semiconductor device
US4439782A (en) * 1980-11-21 1984-03-27 University Of Illinois Foundation Semiconductor device with heterojunction of Alx Ga1-x As--AlAs--Ga
US4410902A (en) * 1981-03-23 1983-10-18 The United States Of America As Represented By The Secretary Of The Army Planar doped barrier semiconductor device
JPS58139464A (en) * 1982-02-15 1983-08-18 Semiconductor Energy Lab Co Ltd Semiconductor device
JPS58141561A (en) * 1982-02-18 1983-08-22 Semiconductor Energy Lab Co Ltd Semiconductor device
JPS58141552A (en) * 1982-02-18 1983-08-22 Semiconductor Energy Lab Co Ltd Semiconductor device
JPS58141573A (en) * 1982-02-18 1983-08-22 Semiconductor Energy Lab Co Ltd Semiconductor device
JPS58147173A (en) * 1982-02-26 1983-09-01 Fujitsu Ltd Semiconductor device
JPS58147158A (en) * 1982-02-26 1983-09-01 Oki Electric Ind Co Ltd Compound semiconductor field effect transistor
US4538165A (en) * 1982-03-08 1985-08-27 International Business Machines Corporation FET With heterojunction induced channel
EP0122047B1 (en) * 1983-03-11 1988-06-01 Exxon Research And Engineering Company A multi-layered amorphous semiconductor material
JPS59168677A (en) * 1983-03-14 1984-09-22 Fujitsu Ltd Manufacture of semiconductor device
JPS59168651A (en) * 1983-03-15 1984-09-22 Mitsubishi Electric Corp Semiconductor device
US4695857A (en) * 1983-06-24 1987-09-22 Nec Corporation Superlattice semiconductor having high carrier density
JPS6052060A (en) * 1983-08-31 1985-03-23 Masataka Inoue Heterojunction semiconductor device
FR2557368B1 (en) * 1983-12-27 1986-04-11 Thomson Csf FIELD EFFECT TRANSISTOR, WITH SUBMICRON VERTICAL STRUCTURE, AND METHOD FOR PRODUCING THE SAME
JPS60189268A (en) * 1984-03-08 1985-09-26 Fujitsu Ltd Semiconductor device
US4558337A (en) * 1984-05-30 1985-12-10 Texas Instruments Inc. Multiple high electron mobility transistor structures without inverted heterojunctions
US4590507A (en) * 1984-07-31 1986-05-20 At&T Bell Laboratories Variable gap devices
JPH06194376A (en) * 1992-12-22 1994-07-15 Matsushita Electric Works Ltd Automatic switch equipped with direction detection sensor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0056904A2 (en) * 1980-12-29 1982-08-04 Fujitsu Limited High electron mobility single heterojunction semiconductor devices and methods of production of such devices
EP0091831A2 (en) * 1982-04-14 1983-10-19 Hiroyuki Sakaki Mobility-modulation field effect transistor
GB2171250A (en) * 1985-01-30 1986-08-20 Sony Corp Heterojunction field effect transistors

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
APPLIED PHYSICS LETTERS, vol. 47, no. 12, 15th December 1985, pages 1324-1326, American Institute of Physics, Woodbury, New York, US; Y.-C. CHANG et al.: "A new one-dimensional quantum well structure" *
JAPANESE JOURNAL OF APPLIED PHYSICS, vol. 23, no. 2, February 1984, pages L61-L63, Tokyo, JP; K. INOUE et al.: "A new highly-conductive (AlGa)As/GaAs/(AlGa)As selectively-doped double-heterojunction field-effect transistor (SD-DH-FET)" *
MICROELECTRONICS JOURNAL, vol. 13, no. 3, May/June 1982, pages 5-22, Benn Electronics Publications Ltd, Luton, GB; K. PLOOG et al.: "Growth and properties of new artificial doping superlattices in GaAs" *

Also Published As

Publication number Publication date
US4855797A (en) 1989-08-08
JPS6424467A (en) 1989-01-26

Similar Documents

Publication Publication Date Title
US6777278B2 (en) Methods of fabricating aluminum gallium nitride/gallium nitride high electron mobility transistors having a gate contact on a gallium nitride based cap segment
JP3135939B2 (en) HEMT type semiconductor device
US5705827A (en) Tunnel transistor and method of manufacturing same
EP0202383A1 (en) Semiconductor device using holes as charge carriers
US4740822A (en) Field effect device maintaining a high speed operation in a high voltage operation
JPS6342864B2 (en)
US4704622A (en) Negative transconductance device
EP0334006A1 (en) Stacked channel heterojunction fet
JP2661555B2 (en) Heterojunction field effect transistor
JPH024140B2 (en)
US4907045A (en) Resonant-tunneling functional device using multiple negative differential resistances
US4855797A (en) Modulation doped high electron mobility transistor with n-i-p-i structure
US4980731A (en) Atomic planar-doped field-effect transistor
JP2001085671A (en) Field-effect semiconductor device
USRE33584E (en) High electron mobility single heterojunction semiconductor devices
CA1290864C (en) Transistor comprising a 2-dimensional carrier gas collector situated between emitter and gate
EP0278093B1 (en) Semiconductor structure with a multilayer contact
US3273030A (en) Majority carrier channel device using heterojunctions
US4882608A (en) Multilayer semiconductor device having multiple paths of current flow
JPH07273311A (en) Band versus band resonance tunnelling transistor
EP0240567A1 (en) Semiconductor device
EP0136108A1 (en) Heterojunction semiconductor device
EP1083608B1 (en) Field-effect semiconductor device
US5825048A (en) Semiconductor functional device and electronic circuit provided with the same
JP2000174256A (en) Tunnel transistor and its manufacture

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB NL

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 19890802