JPS58141552A - Semiconductor device - Google Patents

Abstract

PURPOSE:To unify a phototransistor array onto the same substrate also including a peripheral circuit, and to form the array at low cost through a low process which does not exist in a single crystalline semiconductor by laminating NIPIN or PINIP type semiconductors onto the substrate and forming an IGFET with a channel forming region into IPI or INI regions. CONSTITUTION:A metallic film 2 made of Ni, Cr, Mo1Si, etc. is buried into the insulating substrate such as a glass or alumina substrate, and the surface is formed as approximately the same plane as the substrate. A metallic or semiconductor layer constituting a gate electrode is laminated again. The film is etched, and the gate electrode 12 is laminated and formed onto a gate insulator 11 in the lateral direction. A first conductive layer 2 shields incident light from the substrate side, and the IGFET20 is used as an IGFET having no photosensitivity merely. X-axis wiring is formed by first conductive layers 2, 3 and Y-axis wiring by a second conductive layer 9 in bipolar phototransistors 21, 22, and the phototransistors are constituted in matrix shape.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a vertical channel type 4/4 layer type insulated gate type semiconductor device (in the above, The present invention relates to a semiconductor device equipped with a GFET (GFET).

By connecting the leakage current in the off-state (in or source), the off-state leakage current can be reduced to
It is characterized by a further 1/1o to 1/1o' increase compared to GFBT K.

The present invention provides an N'IP process N' or a separate INIP process on the same substrate.
The present invention is characterized in that by providing a bipolar transistor, particularly a phototransistor, having a junction, a B-nee MLS type integrated circuit can be constructed using a non-single-crystal semiconductor.

The present invention provides an amorphous or manually inserted single crystal (semi-amorphous) or micro-crystalline material having crystallinity (regularity) on the order of a short range of 5 to 100 A on the electrode of a conductive layer on a substrate'tIL electrode or an insulating substrate. By laminating so-called non-single-crystal semiconductors with a polycrystalline structure, it is possible to produce P-type, N-type, or P-type semiconductors.

Regarding IGNET, which supports N-engineering, P-engineering, and N-structures, bipolar transistors and their composite semiconductor devices.

In the present invention, a transparent conductive film is provided as a first electrode on a transparent substrate, and the above-mentioned non-single crystal semi-solid body to which hydrogen or a halogen element is added as an eleventh agent among recombination centers is laminated on the upper surface of the transparent conductive film. Then, by combining transistors with this semiconductor, we can create an optical sensor array using bipolar transistors.
In addition, the decoders, drivers, etc. in the surrounding areas are subject to engineering work.
The present invention relates to a light conversion integrated circuit that integrates FETs and improves sensitivity to irradiated light by also utilizing the amplification effect of transistors.

Conventionally, when a photoelectric conversion device is to be provided by laminating semiconductor layers by a plasma OVD method or a low pressure Cv'D method, solar cells of diodes 11 to 11 having a P-IJ junction are well known. This was made by the inventor VC,
June 20, 1973 (Special face 1971-71 '73
The details are shown in B). Furthermore, in order to reduce light absorption loss in the P' or ilN layer on the light incidence source side, the photoelectric conversion device i='e of the hetero] conjoint is made of silicon carbide, E, etc. with a wide Eg. It has been published by. (U-Japan P4.239.554 Corresponding Japanese patent application 53-86867, 53-868681 Fujil filed on July 17, 1953) However, these are all diode structures, and the transistor and E7 are expected to have a widening effect. Can not do it. Therefore, it is unsuitable for detecting faint light as a light sensor, and when a matrix array is provided, it is impossible to make the decoder driver in the peripheral area using the same process. In order to eliminate such drawbacks, the present invention aims to heat the Bibo 2 transistor at temperatures of 100 to 400°C, particularly 150 to 30°C.
Made at a temperature of 0”O.

That is, non-single crystal silicon, silicon carbide,
Using germanium as the main material,! The present invention relates to a semiconductor device manufactured by a lamination method on a board.

In addition, regarding a bipolar transistor using the plasma OVD method, there is a patent filed by the present inventor (υSF4.
254.429 corresponding Japanese patent patent application 53-8346'
7.53-83468 January 8, 1978) is known. This patent makes the energy band width a heterojunction and has a continuous junction 7' (PIP or N P
It is related to N-type transistors. It also has NPN, P-N junction, and GFI! ! In order to configure T, the patent filed by the present inventor @5a-1
74120 (Semiconductor Device W, October 29, 1981) is known. However, in all of these, it is impossible to provide a bipolar transistor and an M-type 8-type 11'lDT on the same substrate, and either type of transistor has a 9NIPIN or a P-type N-type P junction. A feature of the present invention is that it has become possible for the first time.

Examples are shown below according to the drawings.

Example 1 Figure 1 is a vertical cross-sectional view of the multilayer mold G'F Fi TO of the present invention and its manufacturing process.
A metal film (2) of , Or, Mo□61, etc. was embedded in the substrate, and its surface was formed approximately on the same plane as the substrate. Furthermore, one layer (3) of the light-transmitting conduit was selectively formed using n% titanium oxide or the like. This conductive layer (2) is formed by coating a resist film on the surface of the substrate where this conductive layer (2) is not formed, and using this resist film as a mask, the substrate is coated with a resist film.
Etch to a depth of 1-3μ. Furthermore, (metal film is deposited on the entire surface.

After forming by electroless plating or the like, the resist film was dissolved away to perform lift-off. In this way, the substrate surface and the conductive layer were made to be approximately on the same plane.
(3) A first chihiro body E11 (4) of N or P was formed thereon to a thickness of 100 to 1000 Å by plasma vapor phase method. Furthermore, on top of this 81 (4), a second true or substantially intrinsic (no impurities are artificially added) semiconductor (5) (hereinafter simply referred to as one layer) (82) is added at 500 m
In addition, a semiconductor layer (83(6)) of a conductivity type opposite to 81(4) was formed to a thickness of ~3000A.
was formed to a thickness of 100 to 200 OA. Next, 82 (
5) One layer similar to 84 (7
). Furthermore, tζ the first semiconductor and the pair,
A fifth semiconductor (8) (hereinafter simply referred to as 85) having the same conductivity type as (81←) is used as the source or drain, collector or emitter of (19).
One piece was stacked to a thickness of 0 to 200 OA and provided as shown in FIG. 1(A). Furthermore, in the drawing, a second conductive layer (9
), a single layer of a transparent conductive film such as 8 n O, or AI,
Ni, Or, etc. may be laminated by a vapor deposition method to promote ohmic contact between the Ni, Or, and the 85(8) and the first conductive layer.

This semiconductor is provided on a substrate using a silane glow discharge method or arc discharge method at a temperature of room temperature to ζ00°C, and is amorphous or 5 to 100A.
A so-called non-single-crystal silicon semiconductor having a semi-amorphous structure having microcrystallinity of 50 to 600 A or a microcrystalline structure of 50 to 600 A is used. In particular, in order to make 81(4) have a wide ]Thg, methane (OH,) is simultaneously introduced to form 8 i x O,
-4 (0<x<1 x=0.S'-0,5).

Regarding this 8A8, the patent application (
A detailed example thereof is shown in Japanese Patent Application No. 55-026388855.3.3 (Semi-Amorphous Semiconductor).

In addition, when forming the semiconductor layer using the plasma OVD method, a reaction furnace is provided for each semiconductor layer to prevent impurities from flowing in by stacking the layers in front of each other, and each semiconductor layer is formed independently. .

A reactor for this purpose was formed based on the patent application No. 53-15288R1853.12.10 filed by the present inventor.

Furthermore, in FIG. 1, the second conductive layer (9) is selectively removed using a mask (2) using a so-called lithography technique using a screen printing method or a photoetching method. 4(7),
Selectively remove S3(6), 82(5) and -r
-'r 82, 83, 84 having a channel forming region and 85 or conductive layer (8) thereon were fabricated to have approximately the same shape.

At this time, selective etching may be performed on S1 as well.

On this second conductive layer (9), in order to further reduce the parasitic capacitance in FIG.
0.0 by D method (low pressure vapor phase method) or plasma OVD method.
A silicon oxide film may be formed to a thickness of 3 to 1 μm.

(9) Also, in No. 111(B), it was effective to remove the step cut on the surface of the substrate (1) on the side surface.

Furthermore, after this, the entire surface of these 61 to S5 is insulated to 11Ka.
υ was formed as a gate insulating film (II) particularly on the side surfaces of 82 to 4. This insulating film has a frequency of 13°56MHz to 2.4
By electromagnetic energy with a frequency of 5 GHz') (l", r
1 in an oxygen or mixed gas atmosphere of oxygen and hydrogen.
00~500'01j1 and oxidize, 200~200
It was formed to the thickness of OA.

%, if the substrate is glass, there is a high possibility that mobile ions such as sodium disturbed therein will diffuse into the kneading gate insulating film over a long period of time. Therefore, this insulating film is made of silicon nitride (813 town-, O<xi4)
Alternatively, it is extremely important to use silicon carbide (SizCθxi1) or the like.

Therefore, the nitrided moon-cumulative film was prepared as follows. That is, ammonia or nitrogen ionized from silane (S i H, or S
0.1-0 as Q compound gas 2 1:20-1:5000
．． A second frequency of 13.56 MHz was introduced into the reactor maintained at 5 torr, and a 13.56 MHz secondary
By using a two-stage plasma OVD method in which high-frequency plasma (output of 5 to 50 W) is applied, the channel forming region of semiconductors, especially GFETs, can be browned. )
, S4(7) is coated with a low temperature (200 to
400'O), the gate insulating film could be formed to a thickness of 200 to 1000A. When the nitride gas is sufficiently ionized by microwave (50 to 300 W) (excitation from c), these 9 elements will be impregnated into the inside of the associated silane during film formation, so generally It was a preferable insulating film that did not exhibit so-called hysteresis characteristics and also had masking properties against sodium and the like.

Regarding 5ix(!+, (O< carbon by plasma CVD method (0.1 to 1 torr substrate temperature 200 to 400
'O) 2.5~3°5ev in the energy band
'f: Formation was possible.

When the substrate is made of glass like this, the forming temperature is set to 200℃.
Considering that -400"O was used to prevent semiconductor and substrate deterioration, silicon nitride or silicon carbide formed by the plasma 0ViD method was an extremely effective gate insulating film.

Further, as shown in FIG. 1(B), the gate [K'
(The metal or semiconductor layer constituting the structure (P or N 4-electrode type silicon semiconductor or S.N.O., ■TO, etc.) was laminated again.Furthermore, the fourth photolithography technique (■) was used. υ This film was selectively VC etched to provide a gate with the pole 02 laterally stacked on top of the gate insulator 01).

(181) At this time, bipolar transistors ←ηQ are simultaneously stacked and formed on other parts of the same substrate.

This breaks the same convergence as IG1t'ET (branch), s1(4)i emitter, srs
(a) acts as a base, and s b(s) acts as a collector. The first layer (6) (8) constitutes a depletion layer region.

An insulating film α), which is the same as the gate insulating film, is formed on the surface of this transistor, particularly on the side surface having a junction, to prevent the generation of a parasitic channel.

Furthermore, at this time, these bipolar transistors eυ(2
) is omitted here because it is not necessary to provide the same metal electrode 04 as in the FET.

I was able to provide a 1GFET and a bipolar transistor H (x→) on the same substrate (1).

In this case, the base electrode lead of the bipolar transistor is omitted to form a so-called phototransistor array.

However, it may be manufactured according to the necessity of machining.

Figure 1 (0) shows polyimide and PIQ in the soil of Figure 1 (B).
etc. were applied as an interlayer insulator θQ to form a third conductive layer. In other words, the electrode size is the fifth
The mask ■ is provided, and the wiring 01 is added to A1 vapor 4.
is formed by the sixth mask (2).

Figure 1 (0)
The conductive layer (2) performs photo-locking, and the GFET (2) is simply used as HnT without photosensitivity.

In addition, the bipolar phototransistor e1) (c) is provided with wiring in the X-axis direction through the first conductive layers (2) and (3), and wiring in the Y-axis direction through the second conductive layer (9) K. I was able to create a matrix configuration.

Alternatively, in addition to preventing the generation of ghost noise between phototransistor Q1 (a), in order to lower the resistance of the conductive layer,
The first conductive layers (2) and (3) are overlapped.

Furthermore, the decoder, driver, and four peripheral components of this phototransistor array can be provided according to a multi-circuit design by providing a plurality of FITs on the same substrate.

As is clear from the above description, the present invention uses non-single crystal semiconductors, and is suitable for use in inexpensive substrates such as glass substrates.
A GFBT having a channel formation region in the 1N or 1N region is formed by stacking N or P type semiconductors, and phototransistors are also stacked vertically on the same substrate using the same semiconductors. It is characterized by being provided in such a way that current flows through it.

As a result, we were able to integrate a 500 x 500 phototransistor array on the same substrate and create it at a low cost and with a process that is not possible with single-crystal semiconductors.

In FIG. 1, an optical filter may be provided by forming a four-layer film on the side surface of the light-transmitting substrate (1) on which the light enters and the in side with the semiconductor to reduce the reflection of the light incident thereon.

Embodiment 2 This embodiment is a vertical channel TOFF! with N-type P-type N or P-type N-type P junction. The relationship with wiring for increasing T density is determined. The manufacturing method α is the same as in Example 1.

In Fig. 2 (A), the conductive layer (2) on the substrate (1) is wired horizontally, and the conductive layer (2) on the substrate (1) is wired horizontally.
, in one direction, and the other S5 (El) is wired in the direction perpendicular to the drawing. IGF in drawings
Although two ET ('Q eA's) are shown, 10 to 10'+ may be arranged in a 7-trick array on the same substrate. In the drawings, the numbers correspond to the embodiment of FIG. 1.

In its manufacture, lithography masks are
Only 34 cities are required. Gate 2 Floating City Layer 04 and S
In order to prevent the generation of parasitic capacitance (1) between the conductive layer of Example I VC and the conductive layer of
) is coated with a thickness f/C of 0.3 to 2μ.

For manufacturing, this silicon oxide θ1 is patterned, and the silicon oxide is used as a mask to form the underlying El 5(8)84(
7), El 3(6), s 2(5),” S 1
(4) shows an example in which all the semiconductor layers are formed into approximately the same shape by etching.

Example 3 FIG. 2() 11) shows another embodiment of the present invention.

In the drawing, the first conductive layer (2) connected to the wiring 81 (4) and the first conductive layer (2) are in the direction, and S@B)
Second conductive layer wiring 0 connected to K contact 0
The direction is horizontal, and the Y-th conductive layer α connected to the gate electrode
1 is provided in the vertical direction perpendicular to the drawing, and the conductive layers are spaced apart from each other by interlayer insulators (oI), on (on) and wired between them.

In the drawing, the conductive layer (2) on the substrate (1) is patterned using a mask of
) were laminated and etched using a self-aligned mask. Further, after forming a gate insulator α■, gate electrodes 0 and ν and their leads 0Y were formed thereon. In addition, after forming an interlayer insulator opening with polyimide resin, P-type Q, etc. to a thickness of 0.5 to 2μ, a contact hole 0'I) is made, and an 85(8)K connected electrode/lead is formed. The third conductive layer (1 layer) was fabricated using a mask (1), demonstrating that three-layer wiring can be fabricated using five types of masks.

Embodiment 4 Another embodiment of the present invention is shown in FIG. 2(0). That is, like the substrate (1), the first conductive layer (2) is shown in a shape extending in the lateral direction (X direction) in the drawing with a mask. Also S
5(8), the gate electrode/lead M Ili is shown in the perpendicular direction (Y direction).

In the process GFFjT..., the second conductive layer (9) S2 to S5 is covered with a mask 2, and the gate (82) covered in the channel formation region is again straddled over S5 (8). In addition, gate leads were made using a mask (2) only on Sunday, May 5th (8th), especially in areas VC of 82 to 84 where channels between elements are not formed.

As shown in Examples 2 and 3.4 above, the process G of the present invention
F'BT is S 1 (4
) Gate insulator 0 to form channel forming region 01 in S5(8) and S2 to S4 to form channel forming region 01 → Gate electrode 04 on top is left to control: # is completely free to change its design elements It became possible to form the pre-spun in the X direction and the Y direction by turning the father.

This is compared to the conventionally known IGFFiT K in which a channel is formed in the lateral direction, and the semiconductor Msl, 82.83.84. It has a structure in which 8184, 8184,
85 was made possible for the first time because it has a substantial self-line structure, and its industrial effects are extremely large.

In addition, in Example 2-4, the matrix ht is used as a phototransistor instead of these GNETs.
#177 (The things that can be done are not the same as those that are possible with the combination Vζ in Example 1.

In the present invention, when the bipolar phototransistor is configured as an element or a planar array, one layer of S2 is made of silicon Q (
2.a to 1.9 θV), the visibility is approximately the same as that of the human eye, and therefore the same wavelength sensitivity as human vision can be obtained. This image sensor may also be used as a computer card reading sensor to prevent thieves, such as a computer card reader.

Furthermore, in the present invention, an insulated gate field effect semiconductor device (IGFET) as shown in Examples 1 to 4 is configured in the peripheral portion of the phototransistor.
Engineering GFII on the same board! A bipolar transistor and a phototransistor can be made by using the same semiconductor layer. Therefore, it was possible to construct an integrated circuit using non-single crystal semiconductors including highly integrated amorphous semiconductors.

In the present invention, in the process of forming each semiconductor layer, the surface of the semiconductor is oxidized with air, and a thin film that can conduct current is removed from the C1 reactor. An insulating film is formed. However, in addition to the dynamic effects of these insulating films U: n K fftft, it is a modification of the semiconductor of the present invention to form an insulating film in or at the interface of these semiconductor layers 1 to S6.

S 1xol- used for the first semiconductor layer in the present invention
, (0 <
Since l is raw JN+, its crystallinity is as high as 20 to 50, υ, and in the semiconductor layer used in the semiconductor device using the non-single crystal semiconductor of the present invention, part of it is amorphous and part of it is semi-semi. It goes without saying that amorphous materials may be mixed.

[Brief explanation of the drawing]

FIG. 1 shows the manufacturing process of the present invention and also shows a vertical sectional view of the semiconductor device of the present invention. FIG. 2 is a vertical sectional view of a semiconductor device according to another embodiment of the invention.

Claims (1)

[Claims] 1. A first electrode made of a conductive layer on a conductive substrate or an insulating substrate, a first non-single crystal semiconductor layer of one conductivity type on the electrode, and an intrinsic or substantial semiconductor layer on the semiconductor layer. A semiconductor layer of the opposite sex, a third non-single crystal semiconductor layer having a conductivity type opposite to that of the first semiconductor layer on the semiconductor layer, and a C vertically or substantially substantially a first semiconductor region having a fourth non-single-crystal semiconductor layer intrinsic to the semiconductor layer, and a fifth non-single-crystal semiconductor layer having the same conductivity type as the first semiconductor layer on the semiconductor layer; an insulated gate field effect semiconductor device having at least a semiconductor region, in the first semiconductor region, the first and fifth semiconductors form a pair of sources and drains; In the semiconductor region, the first and fifth semiconductor regions form a bipolar It'1 which forms an emitter and a collector 141f.
1. That a semiconductor device was installed! 1! A conductor device with f characteristics.