JPS58139464A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a phototransistor having good sensitivity by forming a hetero junction on the conductive layer on a conductive or insulating substrate, superposing non-single crystal Si layer as an N-I-P-I-N or P-I-N-I-P structure and inserting the I layer between the layers E and (b) and between the B and C. CONSTITUTION:Amorphous Si layers 3-7 are laminated by the prescribed plasma CVD method on a transparent conductive film 2 on a glass 1 to form an N-I-P-I-N structure. Al electrodes 9, 8 are respectively formed on the film 2 and the layer 7. When a light 10 is emitted through the electrode 2, reverse p-n junction are formed between the layers 3 and 5 and between the layers 5 and 7. When positive voltage to the emitter 3 is applied to the collector 8, the layer 2 is energized from the layer 3, holes 25 which are produced by the light at no- voltage applying time are not discharge to the I layer and the base 5, and stored to lower the voltage between the E and B. In this manner, a phototransistor which amplifies the current between the E and B by the holes 25 produced in proportion to the emitted light amount during the voltage application is obtained to increase Eg of the layer 3 and to form a large barrier, and when the I layer 4 is formed thinly as compared with the I layer 6, high withstand voltage hFE can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a semi-amorphous material having crystallinity (regularity) on the short range order of S to 100 μm, with a substrate electrode on an electrode of a conductive layer on an insulating substrate. The present invention relates to a transistor having a PxF or NIPIN structure in which so-called non-single crystal semiconductors having a single crystalline (semi-amorphous) or micro-polycrystalline structure are stacked, and a semiconductor device having a composite thereof.

In the present invention, a transparent conductive film is provided as an Ml electrode on a transparent substrate, and a non-single crystal semiconductor as described above is laminated on the upper surface of the transparent conductive film to which hydrogen or a halogen element is added as a recombination center neutralizing agent. Photoconversion involves making a semiconductor operate as a bipolar transistor or phototransistor, compounding these transistors, providing an array of photosensors, and adding an amplifying effect to the transistors compared to a diode array to improve sensitivity to irradiated light. Concerning integrated circuits.

Traditionally, the low-pressure CVD method was used to produce goods.When a photoelectric conversion device is to be provided by stacking semiconductor layers, PxM is used.
Solar cells with a diode structure having a bonded metal are famous.

This is a work made by the inventor of the present invention, and its details are shown on June 2, 1973. Furthermore, at that time, the present inventor proposed a photoelectric conversion device using a heterojunction in which P on the light incident side is made of a material such as silicon carbide to slightly reduce light absorption loss in the summer. has been done. (U8?4.239.554
Corresponding Japanese patent patent application 53-86861, 63-86
868 (filed on July 1'7, 1972)) However, all of these have a diode structure), and cannot be expected to have a widening effect as a transistor. Therefore, it is unsuitable for detecting weak light as an optical sensor, and when a matrix array is provided, it is impossible to make the decoder and driver in the peripheral area by the same process.The present invention has these drawbacks. In order to remove this, a pievora transistor is made at a temperature of 100 to 400'O%K 16G-30000.

That is, non-single crystal silicon, silicon carbide,
◇ Regarding a semiconductor device manufactured using germanium as the main material by a lamination method on a substrate ◇ Also, regarding a bipolar transistor using a plasma OVD method, there is a patent filed by the present inventor (TRAPA,
254.4txe compatible Japanese patent patent application 53-834
61, 53-83468 (January 8, 1988) is known. This patent is characterized in that a PIP or 11 transistor is constructed by continuously connecting a Hete μ junction in the energy band. It is said that

However, this PIF t friend is MP
Alternatively, since 30 to 300 μm of summer-type impurities are mixed in with each other, sufficient diode characteristics cannot be obtained. So for example emitter grounded? The present invention further eliminates the drawbacks of the PM junction surface Kl (intrinsic mak-
A so-called substantially intrinsic semiconductor layer (hereinafter referred to as "processing") that does not contain any additives is interposed, and it is not a PIN diode (PIMIP and a layer with one of the two layers interposed in the PM junction), but the transistor There are nine characteristics that have been improved. In particular, this one layer has a layer ti of 100 to 3000 μm interposed between the emitter and the paste,
It is characterized by having 1000 μm to IOF between the pace and collector, making the ratio 3 to 100 times, and improving the withstand voltage of reverse bias between the pace and collector.

In addition, against Niotsuta, use Pace or one in between.
The emitter has a wide Ig compared to the layer, for example, the emitter is 1i
lxo+-x(0<x<1 Representative K ld x=0.
3 to 0.6) with Mg2.0 to 2.5 Mg, and the other layer has a silicon pace of 1.6 to 1.8 Mg.
It was made to have a V. In this way, it is possible to create a barrier against carriers flowing in the opposite direction from the base to the emitter. For example, in an M:[PIM] transistor, the current flow from the emitter to the base is increased to create a barrier against holes. As a result, the current increased by 4q 44 K, and it became possible to apply it to low-quality 1 transistors.

In addition, if this single electric ivy is provided on the first 11 poles on the substrate and this single electric ivy OEg is made larger than the one layer between the emitter and the paste as described above, light irradiation from the side of the translucent substrate can be achieved. On the other hand, the O light absorption loss can be reduced in the emitter region, and the irradiation light can be injected into the effective K1 layer. Therefore, electron-hole pairs can be generated efficiently. Of these, special K mxpxm)
In the case of 9 transistors, if the energy potential of the 4+, L, and base is lowered and the holes flow into the I layer, the base, or the auxiliary area near it, and the holes are made to flow instantaneously during pulse readout, the photosensitivity t can be reduced. I was able to increase it.

In this way, the present invention makes a Hede junction in terms of energy band, and furthermore, the non-single crystal semiconductor is N111M or MIII.
P structure, stacked Kx layer between Niotsuta and base,
By installing the bipolar transistor between the pace and the collector, it is now possible to provide a bipolar transistor (4IK) or an array thereof with high photosensitivity.

The details will be explained below according to the drawings.

Example 1 FIG. 1 shows a vertical sectional view of a semiconductor device of the present invention.

No. The first non-single crystal semiconductor φ1) of MtJ is formed on this upper surface to a thickness of ~5000 μm and 90 μm.
(3) to a thickness of 80 to 800 μm, and an intrinsic or substantially intrinsic third non-single crystal semiconductor (8 rich)←).

A third non-single crystal semiconductor of P type (
83) (5) to a thickness of 100 to 3000 μm as a mono-intrinsic or substantially intrinsic fourth non-single crystal semiconductor (84) (
6) Zoo the sixth non-single crystal semiconductor (II!S) ('F) of K11l to a thickness of 100mm to 1op.
-! A patent application filed on March 10, 1988, using the same reactor or separate type system for a thickness of 5,000 μm using the plasma 0MAD method (filed on March 10, 1988, s3-tt2gg7)
It was formed based on K.

This plasma 0 MAD method is shown in detail in the above-mentioned patent application of the present invention, which is maintained at 0.06 to 2 tOrrK, and silane, 81°, and 01°, etc. are added as necessary in the large reactor. Plasma plates are introduced together with B, IT, P, etc., and plasma plates are disassembled using the arc discharge method and then placed on the substrate.
A method of laminating and forming at a temperature of 10G to 400'O is shown. At this time, the outside of the first electrode (2) and the extracted electrode (9)
) is to be provided with a cover mask in advance to prevent the formation of a semiconductor. After that, the external lead electrode (9) and the 80th electrode (8) are formed using a vacuum evaporation method of 0.3 to 1.5 P. Metals such as Al joinery neem were formed to a thickness of .

The energy band diagram for this 11g1- is shown in Figure 3 (
The AK numbers are shown in correspondence.

As is clear from the drawing, the irradiation light CLΦ is applied through the first electrode (2), and the emitter (3) of 81 and the pace (5) of 83 are connected to the M (g) (4)? What constitutes the diode (5) and the Ka:so pace (5) and the collector () of 86? (6)

When a positive charge is given to the collector (8) K compared to the emitter, this energy band width is from left to lower right, 9〉, and the current flows from the emitter to the collector. Only 9% of the voltage is applied. Holes created by time through light irradiation
Since there is no base (5) K to be released, the potential between the base (5) and the base (5) is reduced, resulting in a decrease in the potential between the base and the base.

For this reason, the current flowing between the ivy and the base is sensitized (electron injection Therefore, a phototransistor having a so-called amplification effect can be constructed. Also, as is clear from Fig. 2 (■), the larger the barrier (B) of one emitter, the better, since the hole (into the hole) flows toward the emitter side.
In addition to reducing the absorption loss of the irradiated light in the pores, rounding is extremely important to improve the photomagnification effect.

Also, the voltage V between the emitter (3) and the collector (9),
Adding much of t to one layer of reverse diode (6)K
In addition to improving the withstand voltage, it is also possible to improve the current amplification rate. Therefore, in the two single layers (4) (@), the thickness of (←) is made thin and (6) is made thick, that is, the thickness of C,x (4)) This is extremely important for phototransistor operation.

Embodiment 3 FIG. 1 (2) shows another embodiment of the present invention. In this embodiment, metal is deposited on a substrate a) such as a conductive substrate electrode made of stainless steel, ceramics, or a heat-resistant organic film. It is best to set the electrode (2) to a thickness of 0.1 to 5P.

PW was applied to the top surface of the lint using the plasma vapor phase method in the same manner as in Example 1.
(81) (3), τ-type eighth semiconductor layer CB la) (4), summer-type third semiconductor layer (8
3) (5), 4O semiconductor layer (84) (6) in I type 01
, P type tD a-th semiconductor layer (B6) (b) was gradually laminated and provided.

At this time, a cover mask is formed during film formation so that a part of the surface of the third semiconductor (6) serving as the base is exposed. ) with two layers of non-single-crystal semiconductor (with large lateral resistance of force (8)). (8
) directly below (>aS(η) may be sufficient to make it function as an emitter.

Figure 1 (9) shows the emitter 85 pace s 5 (5),
The zero pace that constitutes the collector aX(S) constitutes the external extraction electrode portion @.An energy band diagram corresponding to (6) is shown in Fig. 8 @.

The numbers correspond to each other in Fig. 2 (4) and (9). 0 In this drawing, it is 21M air, but it may also be a K MIPIN structure as in Fig. 2 (4). 0 Emitter, base, collector, and The thickness of the two intermediate layers is the same as in Example 1.

Embodiment 3 In this embodiment, the III PIN junction phototransistors of Embodiment 10 are arranged in a matrix structure to form a phototransistor array.

Diagram IIs shows its circuit diagram.

FIG. 4 shows a plan view (4) and a vertical sectional view (9) of a play made according to the circuit diagram of FIG. S.

Figure S KTh, II PIN)? /Register MXP
The XM transistor is simply referred to as ) IPM ) transistor) The base of (a) is not connected, but the two-dimensional play of this phototransistor is that one transistor is connected by a diode between the emitter and base, as seen in -. There is a diode switch for circuit selection using a photodiode for photoelectric conversion and a diode between the base and collector in the opposite direction. This is a diode (blocking diode) for selecting this circuit when reading.
is turned on, and a photocurrent flows through the load resistor Re. At this time, it is thought that the light conversion photodiode was continuously exposed to light from the outside, so the reverse voltage applied during this readout As a result, the photodiode's capacitor α→ is charged, and the photocurrent generated during this period charges the photodiode's capacitor to the extent that it is discharged.The so-called storage effect is obtained by charging the photodiode's capacitor during readout. . This accumulation effect can increase the sensitivity by 10'-1 times as much as that of a 21M photodiode.In other words, the phototransistor constitutes a current amplification circuit with a common emitter structure as shown in Figure 3. There is.

In this semiconductor device, [0 as shown in Figure 4] As is clear from the drawing, the irradiated light α0) is applied to the substrate (1).
KM (3) on the transparent first electrode (2) given from the side
Similar to the first embodiment, the substrate and the plurality of upper surfaces are provided in a laminated manner over the entire surface thereof. The contrast of each element can be further improved by blocking light between the electrode lead wires of the first electrode (2) so that the semiconductor layer is not irradiated with light.

As is clear from the drawing, the first electrode lead (1)! When placed in the X direction, the third electrode/lead (8) is placed in the X direction, and their intersection constitutes one phototransistor. Since non-single crystal semiconductors are easily affected by adsorbed moisture, they are overcoated with moisture-resistant resin to a thickness of 0.5 to 3P, as shown in these semiconductor devices KWA*.
Friend working to improve its reliability.

Each transistor applies a reverse bias between the substrate and the collector, as seen in single crystal semiconductors, and isolation by q PI II coupling eliminates the need for rounding, which is the case with non-single crystal semiconductors.

In other words, the phototransistor array can be fabricated in exactly the same process as in Example 1 without additional mask alignment using 41 K:y odo-etch. It is a ninety-nine number using the characteristic that the ratio is 1/1o to 1/100.

By adopting such a structure), the phototransistor array is shown in FIG. 4 KII Example 1 with its numbers corresponding to those in FIG.
It was prepared in the same manner as .

This drawing shows a two-dimensional phototransistor array, and when used in an image sensor, etc., one layer is made of silicon (1,6
~1.8·ma), its luminous sensitivity is the same as that of the human eye, so it is possible to obtain the same wavelength sensitivity as human night light. -dimensional phototransistor array as shown in Figure 1.
It is also possible to manufacture only a part of the part i and use it as a card reading sensor of a co/peater.

A logic circuit using a bipolar transistor as shown in Embodiment 2 may be used around the phototransistor of the octopus, but an insulating tight field effect semiconductor device (w
eν1 may be configured. In this case, the vertical channel E GFI is used to configure the source, the collector to configure the drain or source, and the channel flowing in the vertical direction to the X-P-1 layer in between.
All you have to do is configure the IT.

In this way, an IGFIT, a bipolar transistor, and a phototransistor can be formed on the same substrate using the same semiconductor layer. It was possible to construct an integrated circuit using only one single crystal semiconductor, including the ninth highly integrated amorphous semiconductor.

In the present invention, when semiconductor devices are laminated or exposed outside a reactor, they are oxidized with air, forming a thin insulating film that can conduct current. These insulating films are semiconductor variations of the present invention, including the fact that they have particularly positive effects.

jlixO,- used for the first semiconductor layer in the present invention
Semiconductors with a wide Mg content of 4 (0 <That's expensive〉
It goes without saying that the semiconductor layer used in the semiconductor device using the non-single crystal semiconductor of the present invention may be partially amorphous and partially amorphous.

411*0 5epia FIG. 1 shows a vertical cross-sectional view of the semiconductor device of the present invention. FIG. 2 shows an energy band diagram of the semiconductor device corresponding to the ts1 diagram.

FIG. S shows a circuit diagram of a phototransistor array.

FIG. 1 corresponds to FIG. S and shows a semiconductor device according to the present invention.

'I'l'+,'l out, 1 person 1 stalk Ka3■ 2 stems 1 Atsushi 4th flash

Claims (1)

[Claims] 1. A first non-single crystal semiconductor of one conductivity type on a first electrode of an isoelectric layer on a conductive substrate or an insulating substrate; an intrinsic second non-single-crystal semiconductor, a third non-single-crystal semiconductor having a conductivity type opposite to that of the first semiconductor on the semiconductor, and an intrinsic or substantially intrinsic fourth non-single-crystal semiconductor on the semiconductor; A single crystal semiconductor and a fifth semiconductor having the same conductivity type as the first semiconductor are laminated on the semiconductor, and NIP is performed.
In addition to having a work-N joint or a P-work N-work P joint,
A semiconductor device characterized in that a second electrode is provided on the fifth semiconductor. 2. A semiconductor device according to claim 1, characterized in that a transistor is provided by providing a third electrode in close contact with a third semiconductor. 3. In claim 1, the first, second or third semiconductor is Sixo, -, (Q< x(υ), and the semiconductor constituting the other part is silicon or 5ixGθ,
(0<x<1), and a semiconductor device characterized in that hydrogen or a halogen element is added to these semiconductors.