JPS6052055A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6052055A JPS6052055A JP15981583A JP15981583A JPS6052055A JP S6052055 A JPS6052055 A JP S6052055A JP 15981583 A JP15981583 A JP 15981583A JP 15981583 A JP15981583 A JP 15981583A JP S6052055 A JPS6052055 A JP S6052055A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- emitter
- collector
- base
- gaas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 239000012535 impurity Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 31
- 238000000034 method Methods 0.000 abstract description 3
- 239000007787 solid Substances 0.000 description 14
- 238000013139 quantization Methods 0.000 description 6
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910004613 CdTe Inorganic materials 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- 229910007709 ZnTe Inorganic materials 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000002109 crystal growth method Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 101100326791 Caenorhabditis elegans cap-2 gene Proteins 0.000 description 1
- 229910004262 HgTe Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- UHYPYGJEEGLRJD-UHFFFAOYSA-N cadmium(2+);selenium(2-) Chemical compound [Se-2].[Cd+2] UHYPYGJEEGLRJD-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052596 spinel Inorganic materials 0.000 description 1
- 239000011029 spinel Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y20/00—Nanooptics, e.g. quantum optics or photonic crystals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
- H01L29/151—Compositional structures
- H01L29/152—Compositional structures with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
- H01L29/155—Comprising only semiconductor materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
- H01L31/035236—Superlattices; Multiple quantum well structures
- H01L31/035254—Superlattices; Multiple quantum well structures including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table, e.g. Si-SiGe superlattices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
- H01S5/343—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
- H01S5/34313—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser with a well layer having only As as V-compound, e.g. AlGaAs, InGaAs
- H01S5/3432—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser with a well layer having only As as V-compound, e.g. AlGaAs, InGaAs the whole junction comprising only (AI)GaAs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
- H01S5/347—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIBVI compounds, e.g. ZnCdSe- laser
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electromagnetism (AREA)
- Ceramic Engineering (AREA)
- Optics & Photonics (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Life Sciences & Earth Sciences (AREA)
- Biophysics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は高速動作が可能な半導体装置に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device capable of high-speed operation.
高速動作が可能と考えられている能動半導体装置の１つ
にｗｉｄｅ −ｇａｐ ｘミッタ（ＷＧＦ３） を有す
るバイポーラＱトランジスタがある。これは通常のホモ
接合のみを有するバイポーラ・トランジスタに比べて次
の２つの大きな利点を持っている。One of the active semiconductor devices considered to be capable of high-speed operation is a bipolar Q transistor having a wide-gap x-mitter (WGF3). This has two major advantages over conventional homojunction-only bipolar transistors:
１）エミッタ注入効率を劣化させることなくベース抵抗
を大幅に低減しベース幅を狭くし得る。1) The base resistance can be significantly reduced and the base width can be narrowed without deteriorating the emitter injection efficiency.
ｉ＋）エミッタ領域の不純物濃度を低減し得るためエミ
ッタ・ベース間容量を小さくできる。i+) Since the impurity concentration in the emitter region can be reduced, the emitter-base capacitance can be reduced.
しかし、従来のＷＧＥバイポーラ−トランジスタでは前
述の利点を有しているのにかかわらず、まだ高速化を阻
害する要素を含んでいるため、充分な高速化は達成され
ていない。However, although the conventional WGE bipolar transistor has the above-mentioned advantages, it still contains elements that impede speeding up, and therefore, sufficient speeding up has not been achieved.
第１図に従来構造のＷＧＢバイポーラ・トランジスタの
模式的断面図を示す。第１図において、１は半導体基板
、２は一導電型を有し第１の半導体からなるコレクタ層
、３は該コレクタ層２と異なる導電型を有し第１の半導
体からなるベース層、４はコレクタ層２と同一導電型を
有しコレクタ層２およびベース層３より禁止帯幅が広い
第２の半導体からなるエミツタ層、５は基板１およびコ
レクタ層２とオーミック接触を形成するコレクタ電極％
６はベース層３とオーミック接触を形成するベース電
極、７はエミツタ層４とオーミック接触を形成するエミ
ッタ電極である。FIG. 1 shows a schematic cross-sectional view of a conventional WGB bipolar transistor. In FIG. 1, 1 is a semiconductor substrate, 2 is a collector layer having one conductivity type and made of a first semiconductor, 3 is a base layer having a conductivity type different from that of the collector layer 2 and is made of a first semiconductor, and 4 5 is an emitter layer made of a second semiconductor that has the same conductivity type as the collector layer 2 and has a wider forbidden band width than the collector layer 2 and the base layer 3, and 5 is a collector electrode that forms ohmic contact with the substrate 1 and the collector layer 2.
6 is a base electrode that forms ohmic contact with the base layer 3, and 7 is an emitter electrode that forms ohmic contact with the emitter layer 4.
この従来構造の動作を、半導体基板１としてドナー濃度
が１×１０１８ｃＩＩＬ−３程度のｎ＋−ＧａＡｓ、コ
レクタ層２としてドナー濃度がＩ ＸＩＯ”ｃｍ ３程
度のｎ−ＧａＡｓ ｓベース層３としてアクセプタ濃度
がＩ ＸＩＯ”儂−３程度のｐ＋−龜Ａｓ、エミツタ層
４としテＶｔ−１１度カ５Ｘ１０”ｃＩｃ３程度のｎ
−Ａｌｌ ｏ３Ｇａ ｏ７Ａｓ を用い、このバンド構
成を示す第２図を用いて説明する。The operation of this conventional structure is as follows: the semiconductor substrate 1 is n+-GaAs with a donor concentration of about 1 x 1018 cIIL-3, the collector layer 2 is n-GaAs with a donor concentration of about IXIO"cm3, the base layer 3 is n-GaAs with an acceptor concentration of about I
-All o3Ga o7As will be used and explained with reference to FIG. 2 which shows the band configuration.
第２図は第１図のエミッタ層、ベース層、コレクタ層に
わたる模式的なバンド構造を示したものである。第１図
と同じ番号のものは第１図と同等物で同一機能を果すも
のであり、ＥＣは伝導帯幅、Ｅｒは充満帯幅、ＥＦはフ
ェルミ準位、ｖＥＢはエミッタ・ベース間の電圧、ＶＢ
Ｃはベース・コレクタ（３）
間の電圧である。FIG. 2 schematically shows a band structure spanning the emitter layer, base layer, and collector layer of FIG. 1. Items with the same numbers as in Figure 1 are equivalent to those in Figure 1 and have the same function. EC is the conduction band width, Er is the filling band width, EF is the Fermi level, and vEB is the emitter-base voltage. , V.B.
C is the voltage between base and collector (3).
エミッタ・ベース間にはＶＥＲの順方向バイアスをし、
ベース・コレクタ間にはＶＢｅの逆方向バイアスをする
と、エミッタからベースへ電子が拡散により注入され、
この電子の大部分はベース層を拡散でコレクタ側へ移動
し、ベース・コレクタ間の空乏層における強い電界で加
速されてコレクタに達する。エミッタからベースへの電
子の注入量はｖＥｎにより変化するため、コレクタ電流
がベース電圧により制御される。通常のホモ接合のみを
有するバイポーラトランジスタでは、エミッタからベー
スに電子を注入する際、ベースからエミッタへ正孔が注
入されるため、エミッタ注入効率（エミッタ電流のうち
の電子電流の割合）が低下する。しかし、ＷＧＥバイポ
ーラトランジスタではエミッタとベースとの間に）Ｊ
ｏ、ｓ Ｇａ Ｏ，７Ａｓ／（）ａＡｓへテロ界面が存
在するため、ベース側からエミッタ側を見ると正孔に対
し５ＱｍｅＶ程度の障壁が存在し、ベースからエミッタ
への正孔の注入は抑制される。したがって、エミッタ注
入効率を低下させ（４）
ることなくベースの正孔濃度を高めてエミッタの電子濃
度をある程度低く抑えることができる。その結果、ベー
ス抵抗が小さく、エミッタ・ベース間容量が小さく、ベ
ース幅が狭い高速動作に適した構造にすることができる
。A forward bias of VER is applied between the emitter and the base,
When a reverse bias of VBe is applied between the base and collector, electrons are injected from the emitter to the base by diffusion.
Most of these electrons diffuse through the base layer and move toward the collector, are accelerated by the strong electric field in the depletion layer between the base and collector, and reach the collector. Since the amount of electrons injected from the emitter to the base varies depending on vEn, the collector current is controlled by the base voltage. In a bipolar transistor that only has a normal homojunction, when electrons are injected from the emitter to the base, holes are injected from the base to the emitter, so the emitter injection efficiency (ratio of electron current to emitter current) decreases. . However, in a WGE bipolar transistor, J
o,s GaO,7As/()aAs heterointerface exists, so when looking from the base side to the emitter side, there is a barrier of about 5QmeV against holes, suppressing the injection of holes from the base to the emitter. be done. Therefore, the hole concentration in the base can be increased and the electron concentration in the emitter can be kept low to some extent without reducing the emitter injection efficiency (4). As a result, a structure suitable for high-speed operation with low base resistance, low emitter-base capacitance, and narrow base width can be obtained.
しかし、この従来のＷＧＥバイポーラ・トランジスタで
は、高速化で必要なコレクタ容量の低減およびコレクタ
抵抗の低減には効果がないこと、および薄いベース層に
オーミック電極を形成することが困難であることからベ
ース幅を極端に薄くすることができないといったことが
問題として残されている。However, this conventional WGE bipolar transistor is not effective in reducing the collector capacitance and collector resistance required for high speed, and it is difficult to form an ohmic electrode on the thin base layer. The problem remains that the width cannot be made extremely thin.
本発明の目的は、従来のＷＧＥバイポーラトランジスタ
の欠点を除去し、超高速動作が可能な半導体装置を提供
することにある。An object of the present invention is to eliminate the drawbacks of conventional WGE bipolar transistors and provide a semiconductor device capable of ultra-high-speed operation.
本発明によれば、半導体基板上に一導電型を有し第１の
半導体からなるコレクタ層と、不純物をほとんど含有し
ない第１の半導体からなるコレクタ空乏１脅と、前記コ
レクタ層と異なる導電型を有し第１の半導体からなるベ
ース層と、不純物をは（５）
とんど含有しない第４の半導体からなるエミッタ空乏層
と、前記コレクタ層と同一導電型を有し第１の半導体層
より禁止帯幅が広い第２の半導体からなるエミツタ層と
を順に積層した構造を有し、コレクタ＃、ベース層、エ
ミッタ層とそれぞれにオーミック接触を形成するコレク
タ電極、ベース電極、エミッタ電極を有することを特徴
とする半導体装置が得られる。According to the present invention, a collector layer made of a first semiconductor having one conductivity type on a semiconductor substrate, a collector depletion layer made of a first semiconductor containing almost no impurities, and a conductivity type different from that of the collector layer. an emitter depletion layer made of a fourth semiconductor containing almost no impurities (5); and a first semiconductor layer having the same conductivity type as the collector layer. It has a structure in which an emitter layer made of a second semiconductor with a wider forbidden band width is laminated in order, and has a collector electrode, a base electrode, and an emitter electrode that form ohmic contact with the collector #, base layer, and emitter layer, respectively. A semiconductor device characterized by this can be obtained.
以下、本発明について実施例を示す図面を参照して詳細
に説明する。EMBODIMENT OF THE INVENTION Hereinafter, the present invention will be described in detail with reference to drawings showing embodiments.
第３図は本発明の第１の実施例を示す模式的断面図であ
る。第３図に刺いて、第１図と同じ番号のものは第１図
と同等物で同一機能を果すものである。８は不純物をほ
とんど含有しない第１の半導体からなるコレクタ空乏層
、９は不純物をほとんど含有しないエミッタ空乏層であ
る。第１の実施例の各層の例としては、半導体基板１と
してドナー濃度がＩＸＩＱ呪ｒ”程度のｎ−’−ＧａＡ
ｓ 、：Ｉ レクタ層２としてドナー濃度が５Ｘ１０”
ご３程度のｎ＋−ＧａＡｓ、 ：ｌレクタ空乏層８とし
て１−ＧａＡｓ、べ（６）
−ス層３としてアクセプタ濃度が２ ＸＩＯ”ｍ−ｓ程
度のｐ＋−ＧａＡｓ、エミッタ空乏層９として１−Ｇａ
Ａｓ。FIG. 3 is a schematic cross-sectional view showing the first embodiment of the present invention. Components in FIG. 3 with the same numbers as in FIG. 1 are equivalent to those in FIG. 1 and perform the same functions. 8 is a collector depletion layer made of a first semiconductor containing almost no impurities, and 9 is an emitter depletion layer containing almost no impurities. As an example of each layer of the first embodiment, the semiconductor substrate 1 is n-'-GaA with a donor concentration of about IXIQ r''.
s, :I donor concentration is 5X10'' as the director layer 2
n+-GaAs with an acceptor concentration of about 3XIO"m-s, 1-GaAs as the collector depletion layer 8, p+-GaAs with an acceptor concentration of about 2XIO"m-s as the base layer 3, and 1-GaAs as the emitter depletion layer 9. Ga
As.
エミツタ層４としてドナー濃度が２ ＸＩＯ”ｎｔ ３
程度のｎ＋ Ｂ１）ｏ３Ｇａ ｏ７Ａｓ ｓ コレクタ
電極５としてＩｎ。As the emitter layer 4, the donor concentration is 2XIO”nt 3
degree n+ B1) o3Ga o7As s In as the collector electrode 5.
ベース電極６としてＡｕＺｎ、エミッタ電極７としてＡ
ｕＧｅ／Ａｕがある。AuZn as the base electrode 6, A as the emitter electrode 7
There is uGe/Au.
この第１の実施例の動作を前述の材料を用い、このバン
ド構造を示す第４図を用いて説明する。The operation of this first embodiment will be explained using the above-mentioned materials and with reference to FIG. 4, which shows this band structure.
第４図は第３図のエミッタ層、エミッタ空乏層。Figure 4 shows the emitter layer and emitter depletion layer in Figure 3.
ベース層、コレクタ空乏層、コレクタ層にわたる模式的
なバンド構造を示したものである。第１〜第３図と同じ
番号のものは第１〜第３図と同等物で同一機能を果すも
のである。This figure shows a schematic band structure spanning the base layer, collector depletion layer, and collector layer. Components with the same numbers as in FIGS. 1 to 3 are equivalent to those in FIGS. 1 to 3 and perform the same functions.
この本発明の動作の基本は従来構造のＷＧＢバイポーラ
トランジスタと同じであるが、動作パラメータとして次
の点が異なっている。The basic operation of the present invention is the same as that of the WGB bipolar transistor of conventional structure, but the following points are different as operating parameters.
（１）エミツタ層ふよびコレクタ層の抵抗が非常に低い
。(1) The resistance of the emitter layer and collector layer is extremely low.
（２）エミッタ・ベース間容量は従来構造ではほぼエミ
ツタ層に形成される空間電荷層により（７）
決められるが、本発明の構造ではほぼエミッタ空乏層で
決められる。(2) In the conventional structure, the emitter-base capacitance is determined almost by the space charge layer formed in the emitter layer (7), but in the structure of the present invention, it is determined almost by the emitter depletion layer.
（３）同様にベース・コレクタ間容量は従来構造ではほ
ぼコレクタ層に形成される空間電荷層により決められる
が、本発明の構造ではほぼコレクタ空乏層で決められる
。(3) Similarly, in the conventional structure, the base-collector capacitance is determined almost by the space charge layer formed in the collector layer, but in the structure of the present invention, it is determined almost by the collector depletion layer.
したがって、本発明の構造はエミッタ層、ベース層およ
びコレクタ層が低抵抗であり、エミッタ・ベース間容量
およびベース−コレクタ間容量が小さいという高速デバ
イスに要求される性質を満足している。また、従来構造
では、エミッタ側の空間電荷層およびコレクタ側の空間
電荷層にはイオン化したドナーが多数存在するため、こ
れらの領域では不純物散乱によりキャリアの拡散定数お
よび移動度が小さいが１本発明の構造ではエミッタ空乏
層およびコレクタ空乏層にはイオン化した不純物がない
かあるいはほとんどないため、キャリアの拡散定数およ
び移動度が太きい。さらに、ベース電極形成時に電極が
ベース電極をつき抜けてコレクタ空乏層に達しても、ト
ランジスタ特性に（８）
影響はは吉んどないため、ベース電極の形成が容易であ
りベース層も充分に薄くすることが可能である。Therefore, the structure of the present invention satisfies the characteristics required for high-speed devices, such that the emitter layer, base layer, and collector layer have low resistance, and the emitter-base capacitance and base-collector capacitance are small. In addition, in the conventional structure, since there are many ionized donors in the space charge layer on the emitter side and the space charge layer on the collector side, the diffusion constant and mobility of carriers are small in these regions due to impurity scattering. In this structure, there is no or almost no ionized impurity in the emitter depletion layer and the collector depletion layer, so the carrier diffusion constant and mobility are large. Furthermore, even if the electrode passes through the base electrode and reaches the collector depletion layer during the formation of the base electrode, it has little effect on the transistor characteristics (8), so the base electrode is easy to form and the base layer is sufficient. It is possible to make it thinner.
以上述べたように、本発明のトランジスタは従来のＷＧ
Ｅバイポーラトランジスタの特長を生かし、さらに高速
化に有利な構造を有しているため、超高速動作が容易で
ある。As described above, the transistor of the present invention is similar to the conventional WG.
It takes advantage of the features of the E bipolar transistor and has a structure that is advantageous for speeding up, making it easy to operate at ultra high speeds.
次に、本発明の第１の実施例の製造方法について説明す
る。結晶成長方法としてはＭＢＰＩ （Ｍｏｌｅ−ｃｕ
ｌａｒ Ｂｅａｍ Ｅｐｉｔａｘｙ ）を用い、ｎ＋−
ＧａＡｓ基板上にドナー濃度が５×１０１８コ３のｎ”
−ＧａＡｓ層を厚さＱ、５ μｆｉ、ノンドープのｔ
ＧａＡｓ層を厚さＱ、５μｍ％アクセプタ濃度が２Ｘ１
０１Ｑご３のｐ”−ＧａＡｓ層を厚さ５００Ａ、ノンド
ープの１−ＧａＡｓ層を厚さ６００ Ａドナー濃度が２
×１０１８ｃＩｃ３のｎ＋ −ＡＩｔ ｏ、ｓ Ｇａ
ｏ７Ａｓ 層を厚さ０．５μｍ を順次形成した。エミ
ッタ電極としてＡｕＧｅ／Ａｕを表面に蒸着した後、エ
ミッタ部を残してエミッタ電極およびｎ＋−Ｍｏ３Ｇａ
ｏ７ＡＳ層をエツチングで除去し、この除去した部分！
先Ｚｎを蒸着しベース電極とした。さらにコレクタ電極
（９）
として裏面にＩｎを着けＨ，雰囲気中でアロイして本発
明によるＷＯＥバイポーラトランジスタを完成させた。Next, a manufacturing method of the first embodiment of the present invention will be explained. The crystal growth method is MBPI (Mole-cu
lar Beam Epitaxy), n+-
n'' with a donor concentration of 5 x 1018 co3 on a GaAs substrate.
- GaAs layer with thickness Q, 5 μfi, undoped t
The GaAs layer has a thickness of Q and a 5 μm% acceptor concentration of 2×1.
The p"-GaAs layer of 01Q is 500A thick, the undoped 1-GaAs layer is 600A thick, and the A donor concentration is 2.
×1018cIc3n+ -AIt o,s Ga
O7As layers were sequentially formed to a thickness of 0.5 μm. After depositing AuGe/Au on the surface as an emitter electrode, the emitter electrode and n+-Mo3Ga are
The o7AS layer was removed by etching, and this removed part!
Zn was first deposited to form a base electrode. Further, In was applied to the back surface as a collector electrode (9) and alloyed in an H atmosphere to complete a WOE bipolar transistor according to the present invention.
その結果、トランジスタ布段尚りの遅延時間として２５
ｐｓが得られた。As a result, the delay time for the transistor stage is 25
ps was obtained.
第５図は本発明の第２の実施例を示す断面模式図である
。第５図において、第１〜第４図と同じ番号のものは第
１〜第４図と同等物で同一機能を果すものである。１０
は第１の半導体より禁止帯幅が広くキャリアカ月・ンネ
ル可能な厚さを有し極低不純物濃度の第１の固体層、１
１は該第１の固体層より禁止帯幅が狭く電子波長または
正孔波長以下の厚さを有し高濃度の不純物を含有した第
２の固体層である。第１．第２の固体層の積層構造によ
りエミツタ層が形成されている。これらの層の例として
は、第１の半導体層１０としてＩ ＡＩＡＳ、第２の半
導体層としてドナー濃度が１×１０１−〔３程度のｎ”
−ＧａＡｓがある。FIG. 5 is a schematic cross-sectional view showing a second embodiment of the present invention. In FIG. 5, the same numbers as in FIGS. 1 to 4 are equivalent to those in FIGS. 1 to 4 and perform the same functions. 10
1 is a first solid layer having a wider bandgap than the first semiconductor, a thickness that allows carriers to channel, and an extremely low impurity concentration;
Reference numeral 1 denotes a second solid layer having a bandgap narrower than that of the first solid layer, having a thickness equal to or less than the electron wavelength or hole wavelength, and containing a high concentration of impurities. 1st. An emitter layer is formed by the laminated structure of the second solid layer. Examples of these layers include IAIAS as the first semiconductor layer 10, and n'' with a donor concentration of about 1×101-[3 as the second semiconductor layer.
-There is GaAs.
この第２の実施例の動作を、第１の実施例および前述の
材料を用い、このバンド構造を示す第６図を用いて説明
する。The operation of this second embodiment will be explained using the first embodiment and the above-mentioned materials, and with reference to FIG. 6, which shows this band structure.
（１０） 第６図は第５図の積層構造を有するエミツタ層。(10) FIG. 6 shows an emitter layer having the laminated structure shown in FIG.
エミッタ空乏層、ベース層、コレクタ空乏層、コレクタ
層にオつたる模式的なバンド構造を示したものである。It shows a schematic band structure including an emitter depletion layer, a base layer, a collector depletion layer, and a collector layer.
第１図〜第５図と同じ番号のものは第１〜第５図と同等
物で同一機能を果すものであり、−は第１の固体層１０
と第２の固体層の積層構造により生ずる電子の最低位の
量子化準位、Ｅｈｑは同様な正孔の最低位の量子化準位
である。Items with the same numbers as in FIGS. 1 to 5 are equivalent to those in FIGS. 1 to 5 and have the same functions, and - indicates the first solid layer 10.
Ehq is the lowest quantization level of electrons generated by the stacked structure of the second solid layer and Ehq is the lowest quantization level of holes.
前述の条件を満足している１−ＡｌＡｓとｎ＋−ＧａＡ
ｓの積層構造では層全体にわたりＧａＡｓの伝導帯より
も高い電子の量子化準位およびＧａＡｓの充満帯より低
い正孔の量子化準位が形成されており、電子および正孔
はこの積層構造中を自由に動くことができる。よって、
この積層構造は等測的なワイドギャップの半導体として
ふるまう。したがってトランジスタの動作としては本発
明の第１の実施例と同じになり、超高速動作が可能とな
る。1-AlAs and n+-GaA that satisfy the above conditions
In the laminated structure of s, an electron quantization level higher than the GaAs conduction band and a hole quantization level lower than the GaAs filling band are formed throughout the layer, and electrons and holes are distributed throughout the layer. can move freely. Therefore,
This stack behaves as an isometric wide-gap semiconductor. Therefore, the operation of the transistor is the same as that in the first embodiment of the present invention, and ultra-high speed operation is possible.
この第２の実施例の構造をエミツタ層だけを変えて第１
の実施例と同様にして製作した。エミツタ層としては厚
さ１５ＡでノンドープのＡｌ１Ａｓと厚さ２３Ａでドナ
ー濃度が１×１０１９ｃｒＩＬ−３のｎ＋−ＧａＡｓと
の積層構造とし、０．５μｍ の厚さとした。これによ
りトランジスタ１段当りの遅延時間として２３ｐＳが得
られた。The structure of this second embodiment was changed to the first embodiment by changing only the emitter layer.
It was manufactured in the same manner as in Example. The emitter layer had a laminated structure of non-doped Al1As with a thickness of 15 Å and n+-GaAs with a thickness of 23 Å and a donor concentration of 1×10 19 crIL-3, and had a thickness of 0.5 μm. This resulted in a delay time of 23 pS per transistor stage.
以上述べた本発明の第１および第２の実施例ではｎｐｎ
のＷＧＥバイポーラトランジスタについてしか示さなか
ったが、ｐｎｐにも同様に適用できることは明らかであ
る。また、基板上への成長順序は逆にしてもかまわない
。さらに、エミツタ層とエミッタ空乏層の界面での組成
の変化は急激でな（ｇｒａｄｅｄ であってもかまわな
い。In the first and second embodiments of the present invention described above, npn
Although only the WGE bipolar transistor has been shown, it is clear that it can be applied to PNP as well. Furthermore, the order of growth on the substrate may be reversed. Furthermore, the change in composition at the interface between the emitter layer and the emitter depletion layer may be graded.
第１の半導体としてはＧａＡｓ ｊ、か示さなかったが
、８ｉ、Ｇｅ 等の元素半導体、ＩｎＰ 、 ＩｎＡｓ
、 ＧａＰ 。Although GaAs is not shown as the first semiconductor, elemental semiconductors such as 8i, Ge, InP, InAs, etc.
, GaP.
ＩｎＧａＡｓ 、 ＩｎＧａＡｓＰ等のＩ−Ｖ化合物半
導体、ＣｄＴｅ 、 ＺｎＴｅ等の■−■化合物半導体
およびその他の各種半導体でも良い。IV compound semiconductors such as InGaAs and InGaAsP, ■-■ compound semiconductors such as CdTe and ZnTe, and other various semiconductors may also be used.
第１の実施例のエミツタ層に用いる半導体は第１の半導
体に近い格子定数を持ち、第１の半導体より禁止帯が広
い半導体であれば良く、ＧａＡｓに対してＡｆｆｌＧａ
Ａｓ 、 ＩｎＧａＰやＡＡＩＡｓ 、 ＧａＰに対し
ＡＩ Ｐ 、 Ｉ ｎＧａＡｓに対しＩｎＡＡＩＡｓや
ＩｎＰ、 ＩｎＡｓに対しＧａＡｓＳｂやＡｆｆｌＡｓ
８ｂ、 Ｇａｒｂに対しＡＪＳｂ等がある。さらに、エ
ミツタ層として第２の実施例のような積層構造を用いれ
ば、はとんどの半導体についてそれよりも実効的に禁止
帯幅の大きなものが容易に得られる。この積層構造にお
いては、層間の格子定数がかなり違っていても界面でス
トレスが緩和されるためエピタキシャルすることが容易
である。積層構造を作る材料としては、半導体だけでな
くても良く、第１の半導体層として半導体のかわりに絶
縁体を用いても良い。例えば、第１の固体層にＣａＰ２
やスピネルを用い、第２の固体層にＳｉを用いわば、Ｓ
ｉのＷＧＢバイポーラトランジスタができる。第１の固
体層と第２の固体層の組合せとしては、Ａ−１１Ａｓ／
ＧａＡ、ｓ 、ＡＡ’ＧａＡｓ、／ＧａＡｓ 。The semiconductor used for the emitter layer of the first embodiment may be a semiconductor having a lattice constant close to that of the first semiconductor and a forbidden band wider than the first semiconductor.
As, InGaP and AAIAs, AIP for GaP, InAAIAs and InP for InGaAs, GaAsSb and AfflAs for InAs
8b, Garb, and AJSb. Furthermore, if a laminated structure such as that of the second embodiment is used as the emitter layer, it is possible to easily obtain a bandgap that is effectively larger than that of most semiconductors. In this laminated structure, even if the lattice constants between the layers are considerably different, stress is relaxed at the interface, so epitaxial formation is easy. The material for forming the laminated structure is not limited to semiconductors, and an insulator may be used instead of a semiconductor for the first semiconductor layer. For example, in the first solid layer CaP2
or spinel, and Si is used for the second solid layer, so to speak.
i WGB bipolar transistor is made. The combination of the first solid layer and the second solid layer is A-11As/
GaA,s, AA'GaAs,/GaAs.
Ｉ ｎＡＪＡｓ／Ｉ ｎＧａＡｓ 、）ＪＰ／ＤａＰ
、ＡＡｉ８ ｂ／Ｇａ Ｓｂ 、ＡｆｆｌＡｓ Ｓ ｂ
’ ／Ｉ ｎＰ 、 Ｉ ｎＧａＰ／ＧａＡｓ 、 Ｇ
ａ ＰＳ ｂ／ＧａＡｓ 、 Ｇａ ８ ｂ／Ｉ ｎＡ
ｓ 。InAJAs/InGaAs, )JP/DaP
, AAi8 b/Ga Sb , AfflAs S b
'/InP, InGaP/GaAs, G
a PS b/GaAs, Ga 8 b/I nA
s.
ＡＡＩ Ｓｂ／Ｉ ｎＡｓ 、 Ｉ ｎＰ／Ｉ ｎＧａ
Ａｓ 、 ＧａＰ／８ ｉ 、 ＧａＡｓ／Ｇｅ 。AAI Sb/I nAs, I nP/I nGa
As, GaP/8i, GaAs/Ge.
ＡｆｆｌＡｓ／Ｇｅ 、ＡＡ’ ＧａＡ ｓ／Ｇｅ 、
Ｃ／Ｓ ｉ 、 ＣｄＴｅ／ＨｇＴｅ 、 Ｚｎ ８
／Ｚｎ５ｅ、ＣｄＳｅ／ＺｎＴｅ、Ｚｎ５ｅ／ＧａＡｓ
、スビｉ、＋Ｖ０ａＡｓ。AfflAs/Ge, AA'GaAs/Ge,
C/S i , CdTe/HgTe, Zn 8
/Zn5e, CdSe/ZnTe, Zn5e/GaAs
, Subi, +V0aAs.
（１３）
Ｃａ ｘｓ ｒ １−ｚＦ１／ＧａＡｓ 、８ ｒｚＢ
ａ Ｉ−Ｘ”ｔ／’Ｉ ｎＰ 、ＣａＰ、／ＧａＰ等各
種の組合せが可能である。また積層構造としては２種の
固体層を積層したものしか示さなかったが、３種以上の
固体層の組合せであっても良いことは明らかである。(13) Ca xs r 1-zF1/GaAs, 8 rzB
Various combinations such as a I-X"t/'I nP, CaP, /GaP, etc. are possible. Also, although only two types of solid layers are shown as a stacked structure, three or more types of solid layers can be used. It is clear that a combination of these may also be used.
この積Ｉ−構造のエミッタの特長として前述の特長に加
え、ドーピングの活性化率を非常に高くし得るこさがあ
る。例えばｋｌ Ｏ，３Ｇａｏ、７Ａｓと同等の禁止帯
幅を有するＡＩＡ ｓ、／ＧａＡｓ積層構造ではＡｌＯ
，３Ｇａ Ｏ，７Ａｓに比べ３倍以上の８ｉ不純物の活
性化率を得た。したがって、低抵抗のエミッタを得るう
えでもこの積層構造のエミッタは重要である。In addition to the above-mentioned features, the product I-structure emitter has the ability to achieve a very high doping activation rate. For example, in the AIAs/GaAs stacked structure, which has a bandgap equivalent to that of klO, 3Gao, and 7As, AlO
, 3Ga O, 7As, the activation rate of 8i impurities was more than three times higher than that of 7As. Therefore, an emitter with this laminated structure is important in obtaining a low-resistance emitter.
本発明の構造を得るための結晶成長方法としては、原理
的にはどんな方法でも良いが、薄いベース層や積層構造
を有するエミツタ層の形成にはＭＨＤ法やＭＯＣＶ Ｄ
（Ｍｅｔａｌ Ｏｒｇａｎｉｃ ＣｈｅｍｉｃａｌＶ
ａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ ）法が適している。In principle, any crystal growth method may be used to obtain the structure of the present invention, but the MHD method and MOCVD method can be used to form a thin base layer and an emitter layer having a laminated structure.
(Metal Organic Chemical V
The apor deposition method is suitable.
第１図は従来構造のワイドギャップ・バイポー（１４）
ノバンド構造図である。
１・・・半導体基板、 ２・・・コレクタ層、３・・・
ベース層、 ４・・・エミツタ層、５・・・コレクタを
極、６・・・ベース電極、７・・・エミッタ電極、８・
・・コレクタ空乏層、９・・・エミッタ空乏層、１０・
・・第１の固体層、１１・・・第２の固体層、 ＥＣ・
・・伝導帯端、Ｅｙ・・・充満帯端、 ＥＦ・・・フヱ
ルミ準位、Ｅｅｑ・・・電子の量子化準位、
Ｅｈｑ・・・正孔の量子化準位、
ＶＥＲ・・・エミッターベース間電圧、ｖｎｃ・・・ベ
ース・コレクタ間電圧。
代理人弁理士内原 晋
（１５）
（ＪＬ ＞
ＬＬＩＬＬＩ ＬＬＩ
特開昭ＧＯ−５２０５５（６）FIG. 1 is a diagram of the conventional wide-gap bipolar (14) no-band structure. 1... Semiconductor substrate, 2... Collector layer, 3...
Base layer, 4... Emitter layer, 5... Collector as pole, 6... Base electrode, 7... Emitter electrode, 8...
... Collector depletion layer, 9... Emitter depletion layer, 10.
...first solid layer, 11...second solid layer, EC・
...Conduction band edge, Ey...Filling band edge, EF...Fulmi level, Eeq...Electron quantization level, Ehq...Hole quantization level, VER...Emitter Base-to-base voltage, vnc...Base-collector voltage. Representative patent attorney Susumu Uchihara (15) (JL > LLILLI LLI JP-A-Sho GO-52055 (6)
Claims (1)
レクタ層と、不純物をほとんど含有しない第１の半導体
からなるコレクタ空乏層と、前記コレクタ層と異なる導
電型を有し第１の半導体からなるベース層と、不純物を
ほとんど含有しない第１の半導体からなるエミッタ空乏
層と、前記コレクタ層と同一導電型を有し第１の半導体
より禁止帯幅が広い第２の半導体からなるエミツタ層と
を順に積層した構造を有し、コレクタ層、ベース層、エ
ミツタ層とそれぞれにオーミック接触を形成するコレク
タ電極、ベース電極、エミッタ電極を有することを特徴
とする半導体装置。a collector layer made of a first semiconductor having one conductivity type on a semiconductor substrate; a collector depletion layer made of the first semiconductor containing almost no impurities; and a first semiconductor having a conductivity type different from that of the collector layer. an emitter depletion layer made of a first semiconductor containing almost no impurities; and an emitter layer made of a second semiconductor having the same conductivity type as the collector layer and having a wider band gap than the first semiconductor. 1. A semiconductor device comprising a collector electrode, a base electrode, and an emitter electrode that form ohmic contact with a collector layer, a base layer, and an emitter layer, respectively.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15981583A JPS6052055A (en) | 1983-08-31 | 1983-08-31 | Semiconductor device |
| DE8484304300T DE3480631D1 (en) | 1983-06-24 | 1984-06-25 | SEMICONDUCTOR STRUCTURE WITH HIGH GRID DENSITY. |
| EP84304300A EP0133342B1 (en) | 1983-06-24 | 1984-06-25 | A superlattice type semiconductor structure having a high carrier density |
| US06/624,333 US4695857A (en) | 1983-06-24 | 1984-06-25 | Superlattice semiconductor having high carrier density |
| US07/043,046 US4792832A (en) | 1983-06-24 | 1987-04-24 | Superlattice semiconductor having high carrier density |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15981583A JPS6052055A (en) | 1983-08-31 | 1983-08-31 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6052055A true JPS6052055A (en) | 1985-03-23 |
Family
ID=15701848
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15981583A Pending JPS6052055A (en) | 1983-06-24 | 1983-08-31 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6052055A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61290759A (en) * | 1985-06-14 | 1986-12-20 | エイ・ティ・アンド・ティ・コーポレーション | Resonance tunnel transistor |
| JPS62130561A (en) * | 1985-12-03 | 1987-06-12 | Fujitsu Ltd | High speed semiconductor device |
| JPS62211953A (en) * | 1986-03-12 | 1987-09-17 | Nec Corp | Bipolar transistor |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58139464A (en) * | 1982-02-15 | 1983-08-18 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
-
1983
- 1983-08-31 JP JP15981583A patent/JPS6052055A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58139464A (en) * | 1982-02-15 | 1983-08-18 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61290759A (en) * | 1985-06-14 | 1986-12-20 | エイ・ティ・アンド・ティ・コーポレーション | Resonance tunnel transistor |
| JPS62130561A (en) * | 1985-12-03 | 1987-06-12 | Fujitsu Ltd | High speed semiconductor device |
| JPS62211953A (en) * | 1986-03-12 | 1987-09-17 | Nec Corp | Bipolar transistor |
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