JPS60102774A - Manufacture of semiconductor element - Google Patents

Abstract

PURPOSE:To produce the titled element with high performance stably by a method wherein N-I-P-I-N or P-I-N-I-P element is composed as a planar type element. CONSTITUTION:An n-GaAs(napprox.=10<18>cm<-3>) layer 2, an i-GaAs(napprox.=10<14>cm<-3>) layer 3, a p-GaAs(papprox.=10<18>cm<-3>) layer 4, an i-GaAs(napprox.=10<14>cm<-3>) layer 5, an n-GaAs(napprox.= 10<18>cm<-3>) layer 6, an insulating film 7, electrodes 8, 9 are successively laminated on an n<+>GaAs substrate 1 with a mesa structure on a part corresponding to an active region Ra. Crystal growth is performed by vapor epitaxial process and molecular beam epitaxial process etc. In such a constitution, a current component flowing outside the active region Ra may be neglected unless the space outside the active region Ra exceeds the active region Ra itself remarkably. In other words, a parasitic current component outside the active region Ra may be reduced by crystal growing process only utilizing a processed substrate to produce a planar type N-I-P-I-N or (P-I-N-I-P) terminal element 2 with ease.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an n-1-p-i-n structure (p-i-n-j-p
Although the present invention is similarly applicable to other structures, the present invention relates to an n-4-p-j-n structure (for simplicity, the description will be made using an n-4-p-j-n structure) and a manufacturing method thereof.

An n-1-p-i-n element has a thin p-layer of around 100^ formed in one layer of an n-1-n structure, and is an element in which majority carriers are mainly involved in conduction. It is expected to be a high-speed device, and recently, a three-terminal device using this structure has also been proposed.

Furthermore, this element can also be used as a highly sensitive photodetector element without excessive noise, and its range of applications is wide.

First, the operation of the n-i-p-i-n two-terminal element will be explained. Figure 1 shows a conventional n-1-
This figure shows the thermal equilibrium state of a p-j-n two-terminal element and the band structure when a voltage (2) is applied, where φBO represents the height 4- of the potential barrier between two n-layers. The density J of the current flowing when the voltage V is applied is expressed by the thermionic emission formula, and is expressed as follows. Here, A
The arrow is the effective Richardson constant, T is the absolute temperature, k is the Boltzmann constant, q is the electron configuration, αl, α2 are a
, + When d2 is the thickness of the two i layers, α+=d+
/ (d++dz), α22d2/ (dl+d2
) is given by d,\d2, asymmetry appears in the voltage-current characteristics. This type of diode can be referred to as forward direction or reverse direction, just like a normal pn junction diode.
For example, if d+<dz, then h in FIG. 1 is considered to be biased in the opposite direction.

When there is no light irradiation, no holes are injected into the device, so the response speed of the device is extremely fast, and it is expected to be an ultra-high-speed device. On the other hand, when light irradiation is performed, holes, which are photoexcited minority carriers, gather in the p-layer. Since this works to reduce the value of the barrier φ80, the electron current flowing through the element increases. In other words, a photocurrent flows due to light irradiation, and the sensitivity at this time is about 70OA, /W, and the gain is about 1000.
They have also reported double the value. On the other hand, values of response speed of 50 to 500 ps have been reported, and there are great expectations as a high-gain, high-speed light-receiving element.

Previous reports have used mesa-type devices in which the periphery of the active region has been removed by machining or etching, but in the case of mesa-type devices, the periphery of the mesa is easily affected by impurities from the outside, so it is better to use a planar-type device. It is easy to obtain stable elements. But now 1
However, there were no proposals regarding the specific structure of planar elements.

The present invention aims to reduce leakage current from the periphery of the active region when planarizing the n-1-p-i-n element, and provides a stable and high-performance planar type n-j-p-1-n The present invention provides a semiconductor device and a method for manufacturing the same.

The present invention will be explained in detail below.

The present invention will now be described in detail. The potential barrier φBO at the time of thermal equilibrium of the n-1-p-i-n element is obtained by solving the Boann equation, and for example, when the thickness XA of the p layer is sufficiently small compared to d+ + d2, it is given by . Here, NA is the accessor concentration in the p layer, εS is the dielectric constant, and e is the elementary charge. In the present invention, by changing the magnitude of xA or d1 or d2 in a plane, the height of the potential barrier to majority carriers inside and outside the active region is changed, thereby effectively limiting the area where current flows. It is something to do. First of all,
Let's consider the effect on the element when changing XA. In this case, φBO changes according to equation (2), so
As XA increases, φBO increases, and the current density decreases in both the forward and reverse directions as shown in equation (1). Next, d2(
Considering the case where d+ < d2) is increased, φBO,
α2 increases, αI decreases, and the overall current density decreases. As described above, increasing the thickness of XA or dl+d2, whichever is thicker, reduces the current density. Moreover, even if these are increased at the same time, the current density decreases.

Hereinafter, this will be explained in detail with reference to Examples.

[Example 1] Figure 2 shows a planar type n-1-p-i-n using the present invention.
This shows an example of a two-terminal element, (ω is a perspective view including the loading section, (l is a cross-sectional view, and 1 is n+-G
It is an aAs substrate, with a diameter of about 1 in the part corresponding to the active area.
A circular mesa structure (about 05 μm in height) with a diameter of 00 μm is formed. 2 is an n-GaAs layer (n = 1.0I8z”
), 3 is a 1-GaAs layer (n(10"crn"), 4 is a p-caAs layer (p=1018cn1-3), 5 is i
-GaAs layer (n':to14cm-3), 6 is n
-GaAs layer (n: 1018tyn"), 7 is an insulating film, and 8 and 9 are electrodes. Crystal growth is performed by vapor phase epitaxial growth, molecular beam epitaxial growth, metal organic chemical vapor deposition (MOCVD), etc. However, because there is a step in the substrate, there is a difference in the growth rate between the mesa part and the other parts.

For example, the thickness of each layer inside and outside the active area is ~0.5 μm for layer 2 and ~0.6 μm for layer 3, respectively.
20μm and ~2.4μm, layer 4 ~100X and ~1
20λ, layer 5 ~005 μm and ~006 μm, layer 6 ~1 μm. Here, the current density inside and outside the active region will be considered with reference to equations (1) and (2). Assuming that the dielectric constant of GaAsO is 13, φBO is 0.68 inside and outside the active region.
eV and 0.98 eV, and the density J outside the active region
Taking the ratio Jo/J1 of O and the density Jl inside the active region, Jo/Ji becomes 9×10 −6 at room temperature.

Therefore, with the structure shown in FIG. 2, the current component flowing outside the active region can be ignored unless the area outside the active region is extremely large compared to the active region portion. That is, by simply performing crystal growth using a processed substrate, the parasitic current component outside the active region can be sufficiently reduced, and the planar type n-
An i-p-i-n two-terminal device can be realized.

[Example 2] FIG. 3 shows n-i-p-i-n 2 using the present invention.
Another embodiment of the terminal element is shown, in which ←) is a perspective view including a cut section, and (G) is a sectional view. This embodiment is based on the planar type n-j-p-1- of [Embodiment 1] shown in FIG.
The active region Ra in an element having the same layer structure as the n2 terminal element is surrounded by a semi-insulating or p-type ring-shaped region 10, and this ring-shaped region 10 extends from layer 6 to layer 3. It is formed. The annular region 10 is only intended to prevent current from flowing outside the active region Ra, but by using it in combination with the structure of the present invention, the parasitic current component can be further reduced, and the planar type n- i-p-i
-n A two-terminal device can be realized.

Next, let's consider a three-terminal element (transistor). The three-terminal element has a structure in which two n-1-p-i-n structures are connected in series, with the n-layer part in the middle serving as a base and the n-layers at both ends serving as an emitter and a collector. FIG. 4 shows the band structure in a thermal equilibrium state and when a voltage is applied. Usually the base is positive with respect to the emitter,
The collector is also positively biased with respect to the base.

The height of the base-emitter barrier φBK is lowered by the applied voltage VBE between the base and emitter, and the number of electrons that cross the barrier increases accordingly, and the electrons that cross the barrier are accelerated. If the base region is made thin (1 μm or less) to the extent that electrons are not scattered, electrons will pass through the base region without losing energy, and the collector-base barrier φ
It also passes through cn and reaches the collector. Therefore, by changing the voltage at the base, the current flowing to the collector can be controlled. A distinctive feature of this device is that minority carriers (holes in this case) do not participate in the operation of the transistor, which eliminates the problem of minority carrier accumulation, making it very promising as an ultra-high-speed transistor. ing. However, it was not clear what kind of structure would actually be used to create the three-terminal structure in this case. The present invention can also be applied to such a three-terminal element, and examples in this case will be described in detail below.

[Example 3] FIG. 5 shows that using the present invention, ni-pi-n 3
This figure shows an example of the terminal element, and (a) shows the mounting cross section.
11 - Perspective view including (l is a sectional view. 21 is n+GaA
s substrate, with a diameter of about 10μ in the part corresponding to the active area.
A circular mesa structure (about 1 μm in height) is formed.

22, 26.30 is an n-GaAs layer (n = 1.01
8crn-3), 23, 25, 27, 29 are 1-
GaAs layer (n, p<10"crn"), 24,
28 is a p-GaAs layer (p = 1018cn1”
), 31. ．． Reference numeral 32 denotes a howling electrode separation region, which is made of a semi-insulating semiconductor or the like. 33 is an insulating thin film, 34,
35 and 36 are electrodes. Crystal growth is by vapor phase epitaxy/dial growth method.

Molecular beam epitaxial growth method or organometallic vapor phase deposition method (
Although this is done by MOCVD or the like, there is a difference in the growth rate between the mesa part and other parts because there is a step in the substrate. For example, the thickness of layers 22-25 inside and outside the active area is ~0.5 μm and ~06 μm, respectively.
Layer 23 is ~20 μm and ~24 μm 1 layer 24 is ~100 μm
λ and ~120 and layer 25 is ~005 μm and ~006
Crystals can be grown as small as μm. Also, layer 26 has a thickness of ~0.3μ
The crystals are grown so that the layer 27 is ~0.05 μm, the layer 28 is ~100 μm, the layer 29 is ~2 μm, and the layer 3o is ~3 μm. In this embodiment, layers 27 to 301 have active area portions.
It has a structure in which the etching is performed leaving only 12-, and furthermore, the ring-shaped regions 3l and 32 for electrode separation are formed so as to reach from layer 26 to layer 23 for 31, and from layer 30 to layer 27 for 32. ing. [Example t].

For the same reason as explained in [Embodiment 2], the current flowing between the electrode 35 and the electrode 36 is concentrated in the active region, and the current flowing outside the active region can be reduced, resulting in stable n-
An i-p-i-n three-terminal device can be realized. In addition,
In this embodiment, the thicknesses of layers 22 to 25 are varied inside and outside the active region, but the thicknesses of layers 26 to 30 may also be varied at the same time.

In the above explanation, GaAs was used as the material, but GaAtAs, InGaAsP, InGaA
Mixed crystals such as LAs can also be used, and instead of making n-1-p-i-n elements with materials of a single composition, materials with different compositions are used to create n-1-p-i-n elements with a Peter structure. p-
An i-n element may also be made. Moreover, it goes without saying that the above structure can also be applied to a p-1-n-1-p element in which the conduction type is reversed.

The structure as explained above can be obtained by forming the circular region of [Example 2] and [Example 3] by using vapor phase epitaxy/yaru growth method, molecular beam epitaxy growth method, organometallic vapor phase deposition method, etc. for crystal growth. can be formed by ion implantation or impurity diffusion, and the insulating film and electrodes can be formed using conventional techniques, so the present invention can be easily realized using conventional techniques.

- As explained in detail, using the present invention, it is possible to fabricate a planar type n-1-p-i-n device with stable operating characteristics, and it can be widely applied to ultra-high speed devices and high-sensitivity photodetecting devices. becomes possible.

[Brief explanation of drawings]

Figures 1 (a) and (b) are respectively n-1-p-i
-n band structure diagram of the thermal equilibrium state of the two-terminal element and when voltage is applied; A trunk view and a cross-sectional view including FIG. 3(a); FIG.
FIG. 4(a) is a perspective view and a sectional view including a mounting section of a two-terminal element. Figure 5(a) shows the band structure diagram of the thermal equilibrium state of the 3-terminal device and when voltage is applied.
. (b) are n-1-p, which are other embodiments of the present invention, respectively;
-i-n3 A perspective view and a sectional view including a mounting section of the terminal element. 1 ・n+-Ga As substrate, 2-n-Ga, As layer,
3..1-GaAs layer, 4.p-GaA, s layer, 5
-1-GaAs layer, 6- n-GaAs layer, 7... insulating layer, 8.9=electrode, 21, - n+-GaAs substrate, 2
2, 26, 30- n-GaA, s layer, 23, 2
5, 27, 29 ・= 1-GaAs layer, 24,
28-p-GaAs layer, 31. ．． 32...Howling electrode separation region, 33...Insulator thin film, 34, 35, 3
6...electrode. Patent applicant International Telegraph and Telephone Corporation Representative Inuzuka 1 person from outside the university ul? Isu1%I-Lee-378-

Claims (1)

[Claims] (]) A first semiconductor layer having a carrier concentration of 1.017cn1" or more and a second semiconductor layer having a carrier concentration of 1016c1n" or less.
a third semiconductor layer with a carrier concentration of 10I7z'' or more, a fourth semiconductor layer with a carrier concentration of 1016crn-3 or less, and a fifth semiconductor layer with a carrier concentration of 10I7crn-3 or more.
have a structure in which the first semiconductor layer and the fifth semiconductor layer are formed to have the same conductivity type and different from the conductivity type of the third semiconductor layer; In a semiconductor device in which electrodes are independently formed on the semiconductor layer and the fifth semiconductor layer directly or through a semiconductor of the same conductivity type as the first semiconductor layer and the fifth semiconductor layer, the active region The thickness of the third semiconductor layer is 300X or less, and the thickness of at least one of the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer is greater than the thickness of a portion other than the active region. A semiconductor device characterized in that the thickness of the active region is greater than the thickness of the active region. (2) A semi-insulating or circular region of the same conductivity type as the third semiconductor layer is formed around the active region as a trench extending from the fifth semiconductor layer to the second semiconductor layer. A semiconductor device according to claim 1, characterized in that: (3) A first semiconductor layer with a carrier concentration of 1017cn1-3 or more and a second semiconductor layer with a carrier concentration of 1016c1n-3 or less.
and a third semiconductor layer with a carrier concentration of 1017 cm-3 or more.
a fourth semiconductor layer with a carrier concentration of 1016 crn-3 or less, and a fifth semiconductor layer with a carrier concentration of 1017 crn'' or more are sequentially stacked, and the conductivity types of the first semiconductor layer and the fifth semiconductor layer are the same. and has a structure formed to have a conductivity type different from that of the third semiconductor, and the first semiconductor layer and the fifth semiconductor layer are directly or the same as the first semiconductor layer and the fifth semiconductor layer. In a semiconductor element in which electrodes are formed independently through conductive semiconductors, the thickness of the third semiconductor layer in the active region is 300 mm or less, and the thickness of the second semiconductor layer and the third layer semiconductor are ), and at least one of the fourth semiconductor layers is formed so that the thickness outside the active region is greater than the thickness of the active region portion, and further, the gearia concentration is formed in contact with the fifth semiconductor layer. A sixth semiconductor layer with a carrier concentration of 10177m" or less, an eighth semiconductor layer with a carrier concentration of 1o17cm" or less, a ninth semiconductor layer with a gear carrier concentration of 1o17crn-3 or more. Semiconductor layers are sequentially stacked, the conductivity type of the seventh semiconductor layer is equal to the conductivity type of the third semiconductor layer, and the conductivity type of the ninth semiconductor layer is the same as the conductivity type of the fifth semiconductor layer. Equally, the thickness of the fifth semiconductor layer is 1 μm or less, the thickness of the seventh semiconductor layer is 300^ or less, and the ninth semiconductor layer is directly or the same as the ninth semiconductor layer. A semiconductor device characterized in that electrodes are formed independently through conductive semiconductors. (4) The thickness of at least one of the sixth, seventh, and eighth semiconductor layers outside the active region. A semiconductor device according to claim 3, characterized in that the thickness of the active region is larger than the thickness of the active region.
The first semiconductor layer has a gear carrier concentration of 1017 crn-3 or more, the second semiconductor layer has a carrier concentration of 1.016 Lyn'' or less, and the first semiconductor layer has a carrier concentration of 1017 cm' or more.
a third semiconductor layer having a conductivity type different from that of the semiconductor layer and having a thickness of 300X or less at the position of the plateau-like structure; a fourth semiconductor layer having a carrier concentration of 1016 ctn-3 or less; and a gear carrier concentration of 10I7. Step 3 or more to sequentially form a fifth semiconductor layer having the same conductivity type as the first semiconductor layer, and further form an electrode conductive to the first semiconductor layer and the fifth semiconductor layer. As a result, an active region is formed at the position of the plateau-like structure, and at least one of the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer is located outside the active region 1. A method for manufacturing a semiconductor device, in which the thickness of the active region portion is larger than the thickness of the active region portion.