JPH0453110B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing a bipolar transistor with excellent high frequency characteristics.

Prior Art A typical structure of a conventional bipolar transistor is shown in FIG. In the figure, 12 is an n-type silicon substrate, 13 is an n + type collector provided thereon by epitaxial growth, 14 is a p-type base provided by diffusion, and 15 is provided by diffusion or alloying. 16 is a collector electrode, 17 is a base electrode, and 18 is an emitter electrode.

Although this is an npn transistor, a pnp transistor can be used as well.

In this example, the same semiconductor material, silicon, is used to form the emitter, base, and collector.

By the way, it is known that when the emitter is formed using a semiconductor having a wider forbidden band energy width than the base (heterojunction bipolar transistor), a very high current gain can be obtained. This is because by appropriately selecting materials, the band structure of the emitter-base junction can be configured so that it does not provide much of a barrier to electrons, but provides a large barrier to holes. A typical example is
Al _x Ga _1-x As on the emitter, base and collector
It uses GaAs.

Furthermore, it is known that such a structure can significantly improve high frequency characteristics. Maximum cutoff frequency of bipolar transistor
Fc is expressed as Fc=√1(8) (1) Rb: Base resistance Cc: Collector capacitance. When the emitter is formed using a semiconductor with higher forbidden band energy than the base,
As mentioned above, by choosing materials appropriately, the band structure of the emitter-base junction can be configured to provide a low barrier to electrons and a large barrier to holes. Therefore, the carrier concentration (hole concentration) of the base can be made very high. Therefore, the base resistance can be made extremely small, and as a result, a very large maximum cutoff frequency Fc can be obtained. However, since the junction area between the p-type base layer and the n-type collector layer is large and the collector capacitance is large, as can be seen from equation (1), sufficiently excellent high frequency characteristics could not be obtained.

Problems to be Solved by the Invention With such a conventional configuration, it is difficult to obtain an element with a small collector capacitance, and it is difficult to obtain an element with sufficiently excellent high frequency characteristics.

The present invention was made in view of this point, and an object of the present invention is to provide a structure with a small collector capacitance.

Means for Solving the Problems In order to solve the above problems, the present invention forms a semi-insulating semiconductor layer in advance, then removes a part of the semi-insulating semiconductor layer by etching, and then A structure with a small collector capacitance is provided by regrowing the base layer and emitter layer using an epitaxial growth technique such as molecular beam epitaxy.

Effects According to the present invention, the collector capacitance is small due to the above-described structure, so that high frequency characteristics are improved.

Embodiment FIG. 1 shows an embodiment of the structure of the present invention. In Fig. 1, 1 is a semi-insulating GaAs substrate, 2 is an n+ type GaAs collector layer (electrode extraction layer), 3 is an n type GaAs collector layer, 2 layers, and 4 is an Al _y
Ga _1-y As (y = 0.3) semi-insulating semiconductor layer, 5 is p-type
GaAs base layer, 6 is one n-type Al _x Ga _1-x As (0.3) emitter layer, 7 is two n+ type GaAs emitter layers (electrode extraction layer), 8 is collector electrode, 9 is base electrode, 10 is emitter electrode It is.

The thickness of each layer is 400μ for a semi-insulating GaAs substrate.
m, 2 n+ type GaAs collector 1 layer is 4000Å, 3
The n-type GaAs collector 2 layer is 2000 Å, 4 Al _y
Ga _1-y As semi-insulating semiconductor layer is 2000 Å, 5 p-type
GaAs base layer is 1000 Å, 6 n-type Al _x Ga _1-x As emitter layer is 1500 Å, 7 n+ type for electrode extraction
The GaAs emitter two layers are 1500 Å thick. Each layer 2-7 was formed by molecular beam epitaxy (MBE).

Next, a method for manufacturing the device of this example will be described. As shown in Figure 2, first, the semi-insulating
2 by molecular beam epitaxy on a GaAs substrate.
Each layer of 4 to 4 was formed to a predetermined thickness. Next, a resist mask is formed by a normal photolithography method, and a part of the Al _y Ga _1-y As semi-insulating semiconductor layer 4 is etched using this resist mask, as shown in FIG. A part of the collector 2 layer of No. 3 was exposed. In this case, the etching may proceed to the inside of the collector layer, as shown by the dotted line in FIG. Etching of Al _y Ga _1-y As is
This was carried out using a H ₂ SO ₄ −H ₂ O ₂ −H ₂ O mixed solution.
By using (001) as the GaAs substrate,
It was possible to form an etched portion in the shape of an inverted trapezoid as shown in FIG. 3 when viewed from the [110] direction.

Next, the resist was removed with acetone, and by molecular beam epitaxy, a 1000 Å p-type GaAs base layer, a 1500 Å n-type Al _x Ga _1-x As emitter layer,
Two 1500 Å n+ type GaAs emitter layers were regrown as shown in FIG.

Next, a certain portion of the semi-insulating semiconductor layer is converted into H ₂ SO ₄ −H ₂ O ₂ − by photolithography.
Etching was performed using a H ₂ O mixed solution to expose a portion of the base layer and collector 1 layer.

Next, the resist part is removed with acetone, and the part without the semi-insulating semiconductor layer is coated with 10
9 and 8 base electrodes and collector electrodes were formed on the exposed base and collector layers, respectively.

The collector capacitance Cc of the structure of this example is 5 and 3.
It is the sum of the junction capacitance of the p-n junction and the junction capacitance of the junctions 4 and 3.

Generally, the capacitance Cpn of pn junction is a; junction area q; charge NA1; acceptor concentration ND2 of p-type semiconductor; donor concentration ε1 of n-type semiconductor; dielectric constant ε2 of p-type semiconductor; dielectric constant Vb of n-type semiconductor; given by bias voltage.

From this, it can be seen that when the difference between the acceptor concentration and the donor concentration is large, the difference is approximately determined by the smaller one. The acceptor concentration of the p-type GaAs base layer in this example is 1.10 ¹⁹ /cm ³ , and the n-type
The donor concentration of the GaAs collector layer is 5·10 ¹⁷ /cm ³ . Therefore, the collector capacitance is approximately Cpn∝√2 (3).

On the other hand ^, the junction capacitance between the n-type GaAs layer and ^the Al _y Ga _1-y As semi-insulating semiconductor layer is , is proportional to the square root of this acceptor concentration,
The value is much smaller than the value of equation (3). If there is no semi-insulating semiconductor layer, 4
Since the carrier concentration of the n-type GaAs layer is as large as 1·10 ¹⁸ /cm ³ , the collector capacitance of this portion is large. Even if p-type Al _x Ga _1-x As is used instead of p-type GaAs, the junction capacitance remains almost the same. For the above reasons, by forming a semi-insulating semiconductor layer between the p-type base layer and the n-type GaAs collector layer as in this example,
If the configuration has the same area, the collector capacitance can be made much smaller. If the collector capacity becomes smaller,
It is clear from equation (1) that the high frequency characteristics are improved.

In this example, by taking advantage of the characteristics of a heterojunction bipolar transistor, the carrier concentration in the base region can be extremely high (1.10 ¹⁹ /cm ³ in this example).
), the base resistance Rb
is extremely small. Therefore, a transistor with excellent high frequency characteristics having an extremely high maximum cutoff frequency can be obtained.

As expected, the collector capacitance of the heterojunction transistor obtained in this example was significantly reduced, and the high frequency characteristics were greatly improved compared to the conventional transistor when the dimensions were the same.

Although molecular beam epitaxy technology was used in this example,
In addition, for example, metal organic chemical vapor deposition (MO-CVD) can also be used to create the same.

In addition, in this example, GaAs-Al _x
Ga _1-x As was used, but other semiconductor materials, e.g.
It can also be created using InP-InGaAsP or the like. Further, as the Al concentration, x=0.3 and y=0.3 were used, but these can be arbitrarily selected in the range of 0 to 1.

In this example, Al _y Ga _1-y As is used as the semi-insulating layer.
(0.3), but it is clear that even if y=0, that is, GaAs is used, the same effect can be obtained in terms of reducing the collector capacitance.

In this example, y=0.3 was used, but Al _y Ga _1-y
Since As has a larger forbidden band energy than GaAs, this makes it possible to use GaAs for p-type base electrode extraction.
Leakage current between the layer and the n-type collector layer can be further reduced. Since leakage current reduces the current amplification factor of the transistor, the current amplification factor can be improved by reducing the leakage current.

Although a − compound semiconductor was used in this example, a bipolar transistor with an extremely small collector capacitance could be obtained using silicon (Si) using a similar process using molecular beam epitaxy. The obtained Si bipolar transistor also showed excellent high frequency characteristics.

In this example, the emitter and collector are n-type,
Although the base is p-type, the emitter and collector are p-type.
The base can also be n-type.

Effects of the Invention As described above, the present invention provides a bipolar transistor with excellent high frequency characteristics by significantly reducing the collector capacitance.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG.
FIG. 4 is a diagram showing a structure in the process of being manufactured to realize the structure of the present invention, and FIG. 5 is a diagram showing the structure of a conventional bipolar transistor. 1...Semi-insulating GaAs substrate, 2...n+GaAs
Collector 1 layer (electrode extraction layer), 3...n type
GaAs collector 2 layers, 4... Al _y Ga _1-y As semi-insulating semiconductor layer, 5... p-type GaAs base layer, 6... n
Type Al _x Ga _1-x As emitter one layer, 7...n+GaAs emitter two layers (electrode extraction layer), 8...collector electrode, 9...base electrode, 10...emitter electrode, 11...resist.

Claims (1)

[Claims] 1. After forming a collector layer on a semiconductor substrate and forming a semi-insulating semiconductor layer thereon, a part of the semi-insulating semiconductor layer is removed to form a part of the collector layer. A base layer and an emitter layer are epitaxially grown on the base layer and an emitter layer in sequence. Next, an emitter electrode is formed on the emitter layer formed in the area where the semi-insulating semiconductor layer is not provided, and an emitter electrode is formed on the semi-insulating semiconductor layer. 1. A method of manufacturing a bipolar transistor, comprising: removing a certain portion of a semiconductor layer to expose a portion of the base layer and the collector layer, and forming a base electrode and a collector electrode on each of the base layer and the collector layer. 2. The method of manufacturing a bipolar transistor according to claim 1, wherein at least the forbidden band energy width of the emitter is larger than the forbidden band energy width of the base. 3. The method for manufacturing a bipolar transistor according to claim 1, wherein the forbidden band energy width of the semi-insulating semiconductor layer is larger than the forbidden band energy width of the base. 4 - A method for manufacturing a bipolar transistor according to claim 1, characterized in that a compound semiconductor is used.