JPH0453108B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing a bipolar transistor with excellent high frequency characteristics.

Prior Art A typical structure of a conventional bipolar transistor is shown in FIG. In the figure, 13 is an n-type silicon substrate, 14 is an n + type collector provided thereon by epitaxial growth, 15 is a p-type base provided by diffusion, and 16 is provided by diffusion or alloying. 17 is a collector electrode, 18 is a base electrode, and 19 is an emitter electrode.

Although this is an npn transistor, a pnp transistor can be used as well.

In this example, the same semiconductor material, silicon, is used to form the emitter, base, and collector.

Incidentally, the operating speed of a transistor, which is related to high frequency characteristics, depends on the transit time of electrons. The base running time is particularly important; the shorter the base length, the faster the operating speed. Therefore, the shorter the base length, the more desirable it is, but with this structure,
In practice, it is extremely difficult to reduce the base length to 1000 Å or less while maintaining good ohmic contact.

By the way, it is known that when the emitter is formed using a semiconductor having a wider forbidden band energy width than the base (heterojunction bipolar transistor), a very high current gain can be obtained. This is because by appropriately selecting materials, the band structure of the emitter-base junction can be configured so that it does not provide much of a barrier to electrons, but provides a large barrier to holes. A typical example is
Al _x Ga _1-x As on the emitter, base and collector
It uses GaAs.

Furthermore, it is known that such a structure can significantly improve high frequency characteristics. Maximum cutoff frequency of bipolar transistor
Fc is expressed as Fc=√1(8) (1) Rb: Base resistance Cc: Collector capacitance. When the emitter is formed using a semiconductor with higher forbidden band energy than the base,
As mentioned above, by choosing materials appropriately, the band structure of the emitter-base junction can be configured to provide a low barrier to electrons and a large barrier to holes. Therefore, the carrier concentration (hole concentration) of the base can be made very high. Therefore, the base resistance can be made extremely small, and as a result, a very large maximum cutoff frequency Fc can be obtained. However, it is difficult to shorten the base length as it is, and for this reason, it is not possible to obtain sufficiently excellent high frequency characteristics.

FIG. 6 shows a conventional example (Japanese Patent Publication No. 55-9830) in which the extraction of the base electrode is improved. In the figure, 20 is an n-type GaAs substrate, 21 is an n-type GaAs forming a collector, 22 is a p-type GaAs forming a base, and 23 is an n-type Al _x forming an emitter.
Ga _1-x As, 24 is p for taking out the base electrode
Type Al _x Ga _1-x As, 25 is a collector electrode, 26 is a base electrode, and 27 is an emitter electrode.

First, layers 21, 22, and 23 are formed on a GaAs substrate 20 by a liquid phase epitaxial method. Next, a part of the collector layer 21 is exposed by mesa etching, and a p-type Al _x Ga _1-x As layer for taking out the base electrode 24 is formed on that part again by liquid phase epitaxy. This is an electrode formed.

However, with this method, the initially formed 2
2 p-type GaAs base layer and 24 formed later.
The base resistance cannot be reduced so much due to the existence of an energy gap between the p-type Al _x Ga _1-x As base electrode extraction layer and an electron trap at the interface formed during regrowth. First, it was virtually impossible to obtain a base length of 1000 Å or less.

Furthermore, since the junction area between the p-type base layer and the n-type collector layer is large and the collector capacitance is large, as can be seen from equation (1), sufficiently excellent high frequency characteristics could not be obtained.

Problems to be Solved by the Invention With such a conventional configuration, it is difficult to obtain an element with a short base length and a small collector capacitance, and it is difficult to obtain an element with sufficiently excellent high frequency characteristics.

The present invention has been made in view of these points, and an object of the present invention is to provide a structure with an extremely short base length and a small collector capacitance while maintaining ease of taking out the base electrode.

Means for Solving the Problems In order to solve the above problems, the present invention forms in advance a thick base electrode extraction layer separated from the collector by a semi-insulating semiconductor layer,
After removing a portion of the base electrode extraction layer and the semi-insulating semiconductor layer by etching, an extremely thin base layer is regrown using an epitaxial growth technique such as molecular beam epitaxy, and an emitter layer is formed on top of it. By growing this, it is possible to provide a structure with an extremely short base length and a small collector capacitance while maintaining ease of taking out the base electrode.

Effects According to the present invention, the base length is extremely short and the collector capacitance is small due to the above-described structure, so that high frequency characteristics are improved.

Embodiment FIG. 1 shows an embodiment of the structure of the present invention. In Figure 1, 1 is a semi-insulating GaAs substrate, 2 is an n+ type GaAs collector layer (electrode extraction layer), 3 is an n type GaAs collector layer, 2 layers, and 4 is a p type
GaAs base 1 layer (electrode extraction layer), 5 is p type
2 layers of GaAs base, 6 is 1 layer of n-type Al _x Ga _1-x As (0.3) emitter, 7 is 2 layers of n+ type GaAs emitter (electrode extraction layer), 8 is collector electrode, 9 is base electrode, 10 is emitter Electrode, 11 is Al _y Ga _1-y As
(y=0.3) It is a semi-insulating semiconductor layer.

The thickness of each layer is 400μ for a semi-insulating GaAs substrate.
m, 2 n+ type GaAs collector 1 layer is 4000Å, 3
The n-type GaAs collector layer of 2 is 2000Å, and the p-type of 4 is 2000Å.
1 layer of GaAs base is 5000 Å, 2 p-type GaAs base layers of 5 are 400 Å, 1 layer of n-type Al _x Ga _1-x As emitters of 6 are 1500 Å, 2 layers of n+ type GaAs emitters for electrode extraction are 1500 Å, 11 The Al _y Ga _1-y As semi-insulating semiconductor layer is 2000 Å. Layers 2 to 7 and 11 were formed by molecular beam epitaxy (MBE).

Next, a method for manufacturing the device of this example will be described. As shown in Figure 2, first, the semi-insulating
By molecular beam epitaxy on GaAs substrate,
Each of layers 2, 3, 11, and 4 was formed to a predetermined thickness. Next, a resist mask is formed by the usual photolithography method, and as shown in _{FIG .} A portion of the insulating semiconductor layer was etched to expose a portion of the second collector layer of No. 3. In this case, the etching may proceed to the inside of the collector layer, as shown by the dotted line in FIG. Etching of GaAs and Al _y Ga _1-y As was performed using a H ₂ SO ₄ −H ₂ O ₂ −H ₂ O mixture. By using (001) as the GaAs substrate, it was possible to form an etched portion in the shape of an inverted trapezoid as shown in FIG. 3 when viewed from the [110] direction.

Next, the resist was removed with acetone, and by molecular beam epitaxy, two 400 Å p-type GaAs base layers, one 1500 Å n-type Al _x Ga _1-x As emitter layer,
Two 1500 Å n+ type GaAs emitter layers were regrown as shown in FIG.

Next, a part of the base 1 layer (electrode extraction layer) was removed using photolithography.
Etching was performed using a H ₂ SO ₄ -H ₂ O ₂ -H ₂ O mixed solution to expose a portion of the base 2 to 1 layers and the collector 1 layer.

Next, the resist portion is removed with acetone, and using conventional photolithography, vacuum evaporation, and heat treatment techniques, 10 emitter electrodes are formed on the portions where the base layer is not present, and 9 emitter electrodes are formed on the exposed base and collector layers, respectively. 8 base electrodes and collector electrodes were formed.

The collector capacitance Cc of the structure of this example is 5 and 3.
It is the sum of the junction capacitance of the pn junction and the junction capacitance of the junctions 11 and 3.

Generally, the capacitance Cpn of pn junction is a; junction area q; electric charge NA1; acceptor concentration of p-type semiconductor ND2; donor concentration of n-type semiconductor ε1; dielectric constant of p-type semiconductor ε2; dielectric constant of n-type semiconductor Vb; given by bias voltage.

From this, it can be seen that when the difference between the acceptor concentration and the donor concentration is large, the difference is approximately determined by the smaller one. The acceptor concentration of the p-type GaAs base layer in this example is 1.10 ¹⁹ /cm ³ , and the n-type
The donor concentration of the GaAs collector layer is 5·10 ¹⁷ /cm ³ . Therefore, the collector capacitance is approximately Cpn∝√2 (3). On the other hand, the n-type GaAs layer and the semi-insulating Al _y
The junction capacitance with Ga _1-y As layer is semi-insulating Al _y Ga _1-y
Since the acceptor concentration of the As layer is 1·10 ¹⁴ /cm ³ or less, the junction capacitance is proportional to the square root of this acceptor concentration, and its value is much smaller than the value of equation (3). If there is no semi-insulating layer, the collector capacitance of the junction capacitance between 11 and 3 will be large because the carrier concentration of the n-type GaAs layer is as high as 1·10 ¹⁸ /cm ³ . p-type
Even if p-type Al _x Ga _1-x As is used instead of GaAs, the junction capacitance remains almost unchanged. For the above reasons, as in this example, a
By forming a semi-insulating layer between the GaAs layer and the n-type GaAs collector layer, the collector capacitance can be made much smaller if the structure has the same area. It is clear from equation (1) that if the collector capacitance becomes smaller, the high frequency characteristics will be improved.

Furthermore, the base length of the structure of this example is 400 Å.
extremely short. It is known that the transit time ts of electrons in a bipolar transistor can be expressed approximately as follows.

ts=(5/2)Rb・Cc+(Rb/RL)・tb +(3Cc+CL)RL (4) RL: Load resistance tb; Base running time Cc; load capacity On the other hand, the base running time is tb＝Lb／Ve (5) Lb; base length Ve: velocity of electron at base is given by

In this example, by taking advantage of the characteristics of a heterojunction bipolar transistor, the carrier concentration in the base region can be extremely high (1.10 ¹⁹ /cm ³ in this example).
), the base resistance Rb
is extremely small. Furthermore, even if the base length Lb is formed to be extremely short as 400 Å, the base electrode can be easily formed, so that a transistor with excellent high frequency characteristics having an extremely high maximum cutoff frequency can be obtained.

The heterojunction transistor obtained in this example exhibited the following characteristics as expected. First 400
We were able to form a good ohmic electrode on a very thin base with a thickness of 1.5 Å. As a result, the base running time became shorter. Furthermore, since the collector capacitance has been reduced, the high frequency characteristics have been greatly improved compared to the conventional type when the dimensions are the same.

In this embodiment, an example of a base length of 400 Å is shown, but it is possible to make it even thinner by using molecular beam epitaxy technology. Alternatively, a similar thin base can be created using, for example, metal organic chemical vapor deposition (MO-CVD).

In addition, in this example, GaAs-Al _x
Although Ga _1-x As was used, other semiconductor materials, e.g.
It can also be created using InP-InGaAsP or the like. Further, as the Al concentration, x=0.3 and y=0.3 were used, but these can be arbitrarily selected in the range of 0 to 1.

In this example, Al _y Ga _1-y As is used as the semi-insulating layer.
(0.3), but it is clear that even if y=0, that is, GaAs is used, the same effect can be obtained in terms of reducing the collector capacitance.

In this example, y=0.3 was used, but Al _y Ga _1-y
Since As has a larger forbidden band energy than GaAs, this makes it possible to use GaAs for p-type base electrode extraction.
Although the leakage current between the layer and the n-type collector layer can be further reduced, the leakage current reduces the current amplification factor of the transistor, so reducing the leakage current improves the current amplification factor. can be done.

In this example, a − compound semiconductor was used, but silicon (Si) could also be used using a similar process using molecular beam epitaxy with a base length of 400 mm.
We were able to obtain a bipolar transistor with a diameter of . The obtained Si bipolar transistor also showed excellent high frequency characteristics.

In this example, the emitter and collector are n-type,
Although the base is p-type, the emitter and collector are p-type.
The base can also be n-type.

Effects of the Invention As described above, the present invention significantly shortens the base length and reduces the collector capacitance while maintaining the ease of taking out the base electrode.
Bipolar transistors with excellent high frequency characteristics,
This is what we provide.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG.
FIG. 4 is a diagram showing a structure in the process of being manufactured to realize the structure of the present invention. FIG. 5 is a diagram showing the structure of a conventional bipolar transistor, and FIG. 6 is a diagram showing the structure of a conventional heterojunction transistor. 1...Semi-insulating GaAs substrate, 2...n+GaAs
Collector 1 layer (electrode extraction layer), 3...n type
GaAs collector 2 layers, 4... p-type GaAs base 1
layer (electrode extraction layer), 5...2 p-type GaAs base layers, 6...1 n-type Al _x Ga _1-x As emitter layer, 7
...n+GaAs emitter 2 layers (electrode extraction layer),
8...Collector electrode, 9...Base electrode, 10...
...Emitter electrode, 11...Al _y Ga _1-y As semi-insulating semiconductor layer, 12... Resist.

Claims (1)

[Claims] 1. After forming a collector layer on a semiconductor substrate,
A semi-insulating semiconductor layer is formed thereon, a base electrode extraction layer having the same conductivity type as the base is further formed thereon, and then the base electrode extraction layer and a part of the semi-insulating semiconductor layer are etched. After exposing a part of the collector layer, a base layer is formed thereon.
The emitter layer is epitaxially grown in sequence, and then the emitter electrode is etched on the emitter layer formed in the area where the base electrode extraction layer is not provided, and a part of the part where the base electrode extraction layer is. A method of manufacturing a bipolar transistor, characterized in that a part of the base layer and the collector layer are exposed, and a base electrode and a collector electrode are formed on each of the base layer and the collector layer. 2. The method of manufacturing a bipolar transistor according to claim 1, wherein at least the forbidden band energy width of the emitter is larger than the forbidden band energy width of the base. 3. The method for manufacturing a bipolar transistor according to claim 1, wherein the forbidden band energy width of the semi-insulating semiconductor layer is larger than the forbidden band energy width of the base. 4 - A method for manufacturing a bipolar transistor according to claim 1, characterized in that a compound semiconductor is used.