JPS61294860A - Manufacture of bipolar transistor - Google Patents

Abstract

PURPOSE:To obtain a structure, in which the length of a base is short and the capacity of a collector is small, by removing a part of a base-electrode taking out layer and a part of a semi-insulating semiconductor layer by etching, regrowing a very thin base layer, and growing an emitter layer thereon. CONSTITUTION:On a semi-insulating GaAs substrate 1, layers 2, 3, 11 and 4 are formed. Then, a resist mask is formed. a part of the P-type GaAs base 1 layer 4 and a part of the semi-insulating semiconductor layer 11 are etched, and a part of the collector 2 layer 3 is exposed. Then, the resist is removed. The P-type GaAs base 2 layer, the N-type AlGaAs emitter 1 layer, and the N<+> type GaAs emitter 2 layer are grown again. A part of the base 1 layer is etched. A part of the base 2 or 1 layer and a part of the collector 1 layer are exposed. The resist part is removed. An emitter electrode 10 is formed at a part, where the base 1 layer is not present. A base electrode 9 and a collector electrode 8 are formed on the exposed base and collector layers. Thus the base length can be made very short and the collector capacity can be made small. In this way, excellent high frequency characteristics can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a bipolar transistor with excellent high frequency characteristics.

Prior Art A typical structure of a conventional bipolar transistor is shown in FIG. In the figure, 13 is an n-type silicon substrate, 14 is an n+ type collector provided thereon by epitaxial growth, 16 is a p-type base provided by diffusion, 1
6 is an n-type emitter provided by diffusion or alloying;
17 is a collector electrode, 18 is a base electrode, and 19 is an emitter electrode.

Although this is an npn transistor, a pnp transistor may be used as well.

This example uses the same semiconductor material, silicon, to
It forms the emitter, base, and collector.

Incidentally, the operating speed of a transistor, which is related to high frequency characteristics, depends on the transit time of electrons. The base running time is particularly important; the shorter the base length, the faster the operating speed.

Therefore, the shorter the base length, the more desirable it is.
With this structure, good ohmic contact and υ
However, it is extremely difficult in practical terms to reduce the base length to 1000 Å or less in terms of thermal processing.

By the way, it is known that when the emitter is formed using a semiconductor having a wider forbidden band energy width than the base (heterojunction bipolar transistor), a very high current gain can be obtained. This is due to the fact that by appropriately selecting materials, the band structure of the emitter-base junction can be configured so that it does not provide much of a barrier to electrons but provides a large barrier to holes. A typical example is
A/xGa, -xAs is used for the emitter, and GaAs f is used for the base and collector.

Furthermore, it is known that such a structure can significantly improve high frequency characteristics. The maximum cutoff frequency Fc of a bipolar transistor is expressed as follows: Fc = 7CτI蔚%了 (1) Rb; Base resistance CC; Collector capacitance. As mentioned above, if the emitter is formed using a semiconductor with higher forbidden band energy than the base,
By choosing materials appropriately, we can modify the band structure of the emitter-base junction to be less of a barrier to electrons.
It can be configured to provide a large barrier to holes. Therefore, 8. the base carrier concentration (hole concentration) can be made very high. Therefore, the base resistance can be made extremely small, and as a result, a very large maximum cutoff frequency Fc can be obtained. However, it is difficult to shorten the base length as it is, and therefore it is not possible to obtain sufficiently excellent high frequency characteristics.

FIG. 6 shows a conventional example (Japanese Patent Publication No. 55-9830) in which the extraction of the base electrode is improved.

In the figure, 2o is an n-type GaAs substrate, 21 is an n-type Gaps that forms a collector, and 22 is a p-type that forms a base.
type GaAs, 23 is n-type A/)(G
a, -xAs, 24 is a p-type A7 for taking out the base electrode! zGa+zAs, 26 is collector electrode, 26
27 is a base electrode, and 27 is an emitter electrode.

First, layers 21, 22, and 23 are formed on a Ga S substrate 20 by a liquid phase epitaxial method.

Next, a part of the collector layer 21 is exposed by mesa etching, and a p-type A4x (ra
, -zAs layers are formed, and electrodes are formed on each layer.

However, in such a method, the 22 p-type Ga base layers formed first and the 24 p-type Ga S base layers formed later
Because there is an energy gap between the G & 1-z AS base electrode extraction layer and an electron trap at the interface formed during regrowth, the base resistance cannot be reduced so much, and in fact It was not possible to obtain a base length of less than 100Å.

Since the junction area between the p-type base layer and the n-type collector layer is large and the collector capacitance is large, it was not possible to obtain sufficiently excellent high frequency characteristics as shown by equation (1).

Problems to be Solved by the Invention With such a conventional configuration, it is difficult to obtain an element with a short base length and a small collector capacitance, and it is not possible to obtain an element with sufficiently excellent high frequency characteristics.

The present invention has been made in view of these points, and an object of the present invention is to provide a structure with an extremely short base length and a small collector capacitance while maintaining ease of taking out the base electrode.

Means for Solving the Problems In order to solve the above problems, the present invention forms in advance a thick base electrode extraction layer separated from the collector by a semi-insulating semiconductor layer, and then removes the base electrode by etching. After removing the layer and a portion of the semi-insulating semiconductor layer, the extremely thin base layer is regrown using an epitaxial growth technique such as molecular beam epitaxy, and the emitter layer is grown on top of it, thereby removing the base electrode. The present invention provides a structure with an extremely short base length and small collector capacitance while maintaining the ease of operation.The present invention has an extremely short base length and small collector capacitance due to the above-described structure, which improves high frequency characteristics. be done.

Example FIG. 1 shows an embodiment of the structure of the present invention.

In FIG. 1, 1 is a semi-insulating GaAs substrate, 2 is an n-type GaAs collector layer (electrode extraction layer), 3 is an n-type GaAs collector layer, 2 layers, and 4 is a p-type GaAs base layer (1 layer).
(electrode extraction layer), 5 is a p-type GaAs base 2 layer, and 6 is an n-type GaAs base layer. xG2Lt-x 1 layer of S(0,3) emitter, 2 layers of n+ type GaAs emitter (electrode extraction layer)
, 8 is the collector electrode, 9 is the base electrode, 1o is the emitter electrode, 11 is AJyG & 1-yAs (Y ==0
．． 3) It is a semi-insulating semiconductor layer.

The thickness of each layer is 400 pm for 1 semi-insulating GaAs substrate.
, 4000 people for 1st layer of n-type Ga S collector in 2, 2000 people in 2nd layer of n-type GaAs collector in 3, 2000 people for 2nd layer of n-type GaAs collector in 4, p-type Ga in 4
As base 1 layer 5000 people, 6 p type G&Mu S base 2
400 people for the first layer, 1500 people for the 1st layer, 6th type n-type GaA for electrode extraction
s emitter 2 layer has 1500 people, 11 people, JyGal-
yAs semi-insulating semiconductor layer is 20008 02-7
．． A method of manufacturing the device of this example will be described in which each layer of No. 11 is formed by molecular beam epitaxy (MBIC).

As shown in Figure 2, first, each layer of 2.3.11.4 is formed to a predetermined thickness on a semi-insulating GaAs substrate of 1 by molecular beam epitaxy using the 0-order normal photolithography method. A resist mask is formed, and as shown in FIG.
Part of the base 1 layer and 11 semi-insulating semiconductor layers is etched, and the collector 2 of 3 is etched.
Part of the layer was exposed. In this case, the etching may proceed to the inside of the collector layer, as shown by the dotted line in FIG.

GILAS and JyGat-ym S were etched using a H2SO4-H2O2-H20 mixture.

By using (001)"i as the G&M S substrate, we were able to form an etched part in the shape of an inverted trapezoid as shown in Figure 3 when viewed from the [11o] force direction.Next, the resist was coated with acetone. 400 p-type GaAs-based bilayers and 16
00 n-type Muj? xGa1-xAsz emitter 1 layer, 1
Two layers of 600 n-type GaAsz emitters were regrown as shown in FIG.

Next, a part of the base 1 layer (electrode extraction layer) was coated with H2S04-H2 by photolithography.
Etching was performed using a 02-H20 mixed solution to expose a portion of the base 2 to 1 layers and the collector 1 layer.

Next, the resist part is removed with acetone, and 10 emitter electrodes are formed on the part without the base layer, and 9 and 8 emitter electrodes are formed on the exposed paste and collector layers, respectively, using conventional photolithography, vacuum evaporation, and heat treatment techniques. A base electrode and a collector electrode were formed.

The collector capacitance Go of the structure of this embodiment is the sum of the junction capacitance of the pn junctions 5 and 3 and the junction capacitance of the junctions 11 and 3.

In general, the capacitance Cpn of a p-n junction is a; junction area q; charge NA1; acceptor concentration HD2 of the p-type semiconductor; donor concentration ε1 of the n-type semiconductor; dielectric constant ε2 of the p-type semiconductor; dielectric constant vb of the n-type semiconductor; bias From this, it can be seen that when the difference between the acceptor concentration and the donor concentration is large, it is approximately determined by a small force of the magnitude. The concentration is 1·10"/G11'% n-type (, the donor concentration of the aAs collector layer is 5·10"/an"0. Therefore, the collector capacitance is approximately c p n c r "■i(s) - Force, n-type Ga layer and semi-insulating AjJyG
&, -yAs The junction capacitance with the layer is semi-insulating U yG
! The acceptor concentration of the L t -ym S layer is 1.10
/an' or less, the junction capacitance is proportional to the square root of this acceptor concentration, and its value is much smaller than the value of equation (3). If there is no semi-insulating layer, the junction capacitance between 11 and 3 will be because the carrier concentration of the n-type G & M S layer is as large as 1.1o18/-, and the collector capacitance in this part will be large. Even if p-type GaAs is used instead of op-type GaAs, the junction capacitance hardly changes. For the above reasons, as in this embodiment, it is used for counting the number of p-type base electrodes.

By forming a semi-insulating layer between the GaAs layer and the n-type eaAs collector layer, the collector capacitance can be made much smaller if the structure has the same area. It is clear that if the collector capacitance becomes smaller, the high frequency characteristics υ will be improved according to equation (1).

Furthermore, the base length of the structure of this example is extremely short, 400 people. Transit time ts of electrons in bipolar transistor
is known to be approximately expressed as follows.

ts=(5/2)Rb-Cc+(Rb/RL)Goodtb
+(360+cL)RL (4>RL; Load resistance tb; Base running time CC; Load capacity On the other hand, the base running time is tb=Lb/We (5) Lb;
Base length ve: given by the velocity of electrons at the base.

In this embodiment, the carrier concentration in the base region can be extremely high by taking advantage of the characteristics of a heterojunction bipolar transistor (a carrier concentration of 1.10 2 /af was used in the embodiment), so the base resistance Rb is extremely small. Furthermore, even if the base length Lb is made extremely short, such as 400, the base electrode can be easily formed, so that a transistor with excellent high frequency characteristics having an extremely high maximum cutoff frequency can be obtained.

The heterojunction transistor obtained in this example exhibited the following characteristics as expected. First, we were able to form good ohmic electrodes on a very thin base made of 400 people. As a result, the base running time became shorter. Furthermore, since the collector capacitance has been reduced, the high frequency characteristics have been greatly improved compared to the conventional type when the dimensions are the same.

In this embodiment, the base length is set to 400 mm, but it is possible to make it even thinner by using molecular beam epitaxy technology. Alternatively, a similar thin base can be created using, for example, metalorganic chemical vapor deposition (M□-CVD).

In addition, in this example, GaAs-N11xG is used as the semiconductor.
Although IL1-1As was used, other semiconductor materials such as I
It can also be created using nP-ZnGaAsP or the like. Still a person! As concentration, x = 0.3, 7
=0.3 is used, but this can be arbitrarily selected within the range of 0 to 1.

In this example, A4yG2L1-7g(0,3) was used as the semi-insulating layer, but even if y=o, that is, eaAS was used, it would not be possible to have the same effect in terms of reducing the collector capacitance. it is obvious.

In this example, 7 = 0.3 was used, but A ly
Since G &+-7AS has a larger forbidden band energy than GaAs, this makes it possible to use Ga for calculating the number of p-type base electrodes.
Leakage current between the As layer and the n-type collector layer can be further reduced. Since leakage current reduces the current amplification factor of the transistor, the current amplification factor can be improved by reducing the leakage current.

Although an IV compound semiconductor was used in this example, a bipolar transistor with a base length of 400 A could be obtained using silicon (Si) using a similar process using molecular beam epitaxy.

The obtained S1 bipolar transistor also showed excellent high frequency characteristics.

In this embodiment, the emitter and collector are in-type and the base is p-type, but the emitter and collector may be p-type and the base is in-type.

Effects of the Invention As described above, the present invention provides a bipolar transistor with excellent high frequency characteristics by significantly shortening the base length and reducing the collector capacitance while maintaining the ease of taking out the base electrode. It is something.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIGS. 2 to 4 are diagrams showing a structure in the process of being manufactured to realize the structure of the present invention. FIG. 5 is a diagram showing the structure of a conventional bipolar transistor, and FIG. 6 is a diagram showing the structure of a conventional heterojunction transistor. 1... Semi-insulating GILAs substrate, 2...
・N-1-GaAs collector 1 layer (electrode extraction layer),
3...N-type GaAs collector 2 layers, 4...
... p-type GaAs base 1 layer (electrode extraction layer), 5.
...p-type GaAs base 2 layers, 6...n
Type Muj? xG & 1-xAs emitter 1 layer, 7...
・n-1-GaAs emitter 2 layers (electrode extraction layer),
8...Collector electrode, 9...Base electrode, 1o...Emitter electrode, 11...
Mu/yG&1-yAs semi-insulating semiconductor layer, 12...
...Resist. Name of agent: Patent attorney Toshio Nakao and 1 other person f-
Base, love, b, lid f (9 stones, knights, LF, 1st Fig. 4--1.--S IC store 4, 1L fake) To, 2, f--1, Emi, ri 1 (house) Unη# Climb〕7--- Smell
Z.

Claims (4)

[Claims] (1) After forming a collector layer on a semiconductor substrate, a semi-insulating semiconductor layer is formed on it, a base electrode extraction layer of the same conductivity type as the base is further formed on it, and then the base electrode After etching a part of the extraction layer and the semi-insulating semiconductor layer to expose a part of the collector layer, a base layer and an emitter layer are sequentially epitaxially grown thereon, and then the base electrode extraction layer is etched. etching an emitter electrode on the emitter layer formed in the non-existent part, and etching a part of the part of the base electrode extraction layer,
A method for manufacturing a bipolar transistor, characterized in that parts of the base layer and the collector layer are exposed, and a base electrode and a collector electrode are respectively formed thereon. (2) The method for manufacturing a bipolar transistor according to claim (1), wherein at least the forbidden band energy width of the emitter is larger than the forbidden band energy width of the base. (3) The method for manufacturing a bipolar transistor according to claim (1), wherein the forbidden band energy width of the semi-insulating semiconductor layer is larger than that of the base. (4) A method for manufacturing a bipolar transistor according to claim (1), characterized in that a III-V compound semiconductor is used.